1

Multichannel Wireless Neural Signal Acquisition

System

Paras Salunkhe

Submitted in partial fulfillment of the requirements of

The University of Reading for the degree of

Master of Science in Cybernetics

Supervisors:

School of Systems Engineering,

Dr. Slawomir Nasuto.

School of Pharmacy,

Dr. Benjamin Whalley.

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Abstract

Advances in fields of neuroscience, neuroprosthetics, neurophysiology has led to the study of

neural signals obtained from electrodes implanted in animal brain. In such experiments the subject is

required to be tethered with wires to the signal acquisition hardware. This restricts the scope of experiments

where free movement of animals is required and affects quality of the signal. This work has tried to solve the

problem by presenting a design of multichannel neural signal acquisition hardware which will act as an

interface between the implanted electrodes and a host computer for signal analysis. The designed system

consists of an analogue front end to buffer, amplify and filter the neural signals, a digital back end to

multiplex, digitise and transmit the signals to the receiver end. At the receiver the signal is demultiplexed

and converted back in to analogue signals to interface with neural signal analysis hardware. In this work the

author has designed and tested the analogue front end and provided the design for digital back end and

receiver end. Testing results are discussed for analogue front end and analogue to digital converter.

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Acknowledgement

The Author would like to thank number of people who have helped him during his time at

Reading. He is truly fortunate to have surrounded by such an energetic and intellectual cast of characters.

First and foremost the author would like to extend his sincerest gratitude to his supervisor, Dr.

Slawomir Nasuto, who with his intellect and expertise guided the project in right direction. Dr. Nasuto has

been both a teacher for sharing his expertise and a parent for being kind towards author‟s mistakes. The

author is a better person and a better engineer for having known him.

The author will forever be indebt to Jonathan Farrimond, for being a mentor and a great friend. John

helped the author in every stage of this project and guided him in right direction every time he needed. With

his immense patience, experience and enthusiasm supported the author to keep going and help built right

attitude towards science.

The author is especially thankful to Dr. Benjamin Whalley for providing all the necessary support,

enthusiasm and for sharing his expertise in neurophysiology. The author is also thankful to Steve Gould for

providing him the necessary laboratory equipments as and when required and sharing his expertise in PCB

board development.

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List of Figures

Figure 2.1: Schematic of action potential (Image web version [23]). The figure shows typical shape of action potential

characterised by threshold excitation, rising phase, falling phase and undershoot………… ………………………13

Figure 2.2: a b) Two views of a 3-D 1024-site 128-channel fully integrated neuro-electronic interface.

(Image credited to Wise et.al. [19]). c) 100 channel neural interface (Image credited to Harrison et.al [24])

……………………………………………………………………………………………………………...…17

Figure 2.3: Commercially available neural recording systems. a) Wireless receiver and transmitter from

Plexon Neurotechnology Research Systems, USA [26]. b) Wireless preamplifier connected to head stage

available from Alpha Omega technologies, Israel [27]. ……………………………………………..............19

Figure3.1: Block Diagram of the System ………………………………………………………………........20

Figure 3.2: a) Microwire electrodes connected to Plexon Connectors b) Close view of tip of connector c) The

Plexon Connector………………………………………………………………………………………….....22

Figure 3.3.1: Simulation circuit of high pass filter formed with capacitor C1 and resistor R1. XFG1 is signal

generator used to provide sinusoidal input. XBP1 is the bole plotter and XSC1 is an oscilloscope…...........24

Figure 3.3.2: Simulation result of the high pass filter. The Bode plot shows -3dB gain at 16 mHz which is the

cutoff frequency…………………………………………………………………………………….………..24

Figure 3.3.3: Circuit diagram of a second order Sallen-Key low pass filter…………………………..........25

Figure 3.4.1: Multisim Simulation of Analogue front end. XFG1 is the signal generator and XSC1 is the

oscilloscope………………………………………………………………………………………………..…26

Figure 3.4.2: Multisim simulation Bode plot for Low pass filter. The figure shows maximal flat response till

the cutoff frequency of 9.933 KHz with a gain of 61.672 dB and a fourth order roll off there after…..……27

Figure 3.4.3: Simulation output for the analogue circuit. The red sinusoid is the input signal and the green

sinusoid the amplified output. The output is amplified and slightly phase shifted version of the input…….28

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Figure 3.5: Block Diagram of ADC conversion……………………………………………………….……..29

Figure 3.7: Receiver end block diagram……………………………………………………………………...30

Figure 4.3.1: Circuit Layout for the analogue front end. a) High Pass Filter b) Non-Inverting Amplifier

c) Low-pass filter d) Connector and bypass capacitors for the battery e) Positive Voltage Regulator

f) Negative Voltage Regulator…………………………………………………………………….……….…32

Figure 4.3.2: PCB prototype of Analogue front end ………………………………………………………....33

Figure 5.2.1: Laboratory setup for the test of analogue front end. Figure shows the Signal generator, digital

storage oscilloscope and the analogue front end…………………………………………………………….35

Figure 5.2.2: Output from the digital storage oscilloscope. The figure shows the input signal and the

amplified output signal. The output signal is slightly phase shifted as compared to the input signal……35

Figure 5.2.3: Frequency response of analogue front end. Figure shows maximally flat response with gain of

65.41 in pass band with cutoff frequency at 10 KHz and a fourth order roll-off thereafter………………….36

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List of Abbreviations

ADC: Analogue to Digital Converter

ASIC: Application Specific Integrated Circuit

CMOS: Complementary Metal-Oxide-Semiconductor

CMRR: Common Mode Rejection Ratio

DC: Direct Current

FSK: Frequency Shift Keying

IC: Integrated Circuit

ICD: In-circuit debugger

IEEE: Institute of Electronic and Electrical Engineers

IrDA: Infrared Data Association

LFP: Local Field Potential

Op-amp: Operational Amplifier

RF: Radio Frequency

RMS: Root Mean Square

SNR: Signal to Noise Ratio

SMD: Surface Mount Device

SPI: Serial Peripheral Interface

TSOP: Thin Small Outline Package

USB: Universal Synchronous Bus

VLSI: Very Large Scale Integration

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List of Tables

Table 5.3: Testing results of Analogue Front End

Table 5.4: Testing results for the Analogue to Digital Converter

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Contents

Multichannel Wireless Neural Signal Acquisition System ............................................................................... 1

Abstract............................................................................................................................................................ 2

List of Figures .................................................................................................................................................. 4

List of Abbreviations ....................................................................................................................................... 6

List of Tables ................................................................................................................................................... 7

Chapter 1 ....................................................................................................................................................... 10

Introduction: .................................................................................................................................................. 10

Chapter 2 ....................................................................................................................................................... 12

Literature Review: ......................................................................................................................................... 12

2.1Neural Signals ........................................................................................................................................... 12

2.1.1 Action Potential .................................................................................................................................... 12

2.2 Noise ........................................................................................................................................................ 13

2.3 Signal Transduction ................................................................................................................................. 14

2.4 Nature of neural signal. ............................................................................................................................ 15

2.5 Commercial Wireless Technology ........................................................................................................... 15

2.6 Published designs ..................................................................................................................................... 16

Chapter 3 ....................................................................................................................................................... 20

System Design ............................................................................................................................................... 20

3.1 Overview ................................................................................................................................................. 20

3.2 Electrodes ................................................................................................................................................ 21

3.3 High Pass filter ........................................................................................................................................ 22

3.4.1 Highpass filter design ........................................................................................................................ 23

3.4.2 Highpass filter simulation ................................................................................................................. 23

3.5 Lowpass filter ........................................................................................................................................ 24

3.5.1 Lowpass filter design ............................................................................................................................ 25

3.6 Analogue Front End simulation ............................................................................................................... 27

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3.7 Analogue to Digital Conversion ............................................................................................................... 29

3.8 Wireless Module ...................................................................................................................................... 30

3.9 Digital to Analogue Converter ................................................................................................................. 31

3.10 Power Supply ......................................................................................................................................... 32

Chapter 4 ....................................................................................................................................................... 33

Methods ......................................................................................................................................................... 33

4.1 Overview ................................................................................................................................................. 33

4.2 Analogue front end .................................................................................................................................. 33

4.3 Analogue to digital converter. .................................................................................................................. 35

4.4 Wireless link. ........................................................................................................................................... 35

Chapter 5 ....................................................................................................................................................... 36

Results ........................................................................................................................................................... 36

5.1 Overview ................................................................................................................................................. 36

5.2 Analogue Front End ................................................................................................................................. 36

5.2.1 Discussion ............................................................................................................................................. 39

5.3.1 Digital to Analogue Converter .............................................................................................................. 40

5.3.2 Discussion ............................................................................................................................................. 41

Chapter 6 ....................................................................................................................................................... 42

Discussion ...................................................................................................................................................... 42

6.1 Analogue Front End ................................................................................................................................. 42

6.2 Digital Backend ....................................................................................................................................... 44

6.3 Future Work ............................................................................................................................................. 45

Chapter 7 ....................................................................................................................................................... 46

Conclusion ..................................................................................................................................................... 46

References: .................................................................................................................................................... 47

Appendix ....................................................................................................................................................... 50

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Chapter 1

Introduction:

Interfacing the brain with computers is an old concept and neural signals have long been studied

by neuroscientists; either to record the electrical activity in a particular brain area and infer its function or to

emulate the function by providing an electrical stimulus [1]. Analysis of neural signals has given a new

direction to the field of neuroscience towards understanding the functioning of different parts of the brain.

The development of translational neuroprosthetics has given a hope of providing a direct interface for neural

rehabilitation to aid the patients who suffer from neurological disorders. Study of neural signals is required

in neuropharmacology to understand the effect of different drugs on functioning of the brain. This new field

of science has coined the terms like „brain-machine interface‟, „brain-computer interface‟, „neural

prosthetics‟ and „neuro-robotics‟[2]. Neural signals from neuronal population recordings of the motor

cortices have been used for real time control of robot arm [9]

This increase in importance of study of neural signals has led to development of neural

interface hardware. Over the past decades electronic systems have been designed to record signals from the

brain and efforts have been made to use computers to return feedback information to the brain. Technology

has helped scientists to develop a number of varied techniques to design hardware for amplification,

conditioning, digitising and the wireless transmission of these signals. The breakthrough in integrated

circuits (IC) fabrication technology and the shrinking size of electronics has led to embedding multi-

electrode arrays with Very Large Scale Integration (VLSI) chips. This helped scientists to integrate all the

required hardware for the real time neural signal acquisition on a single chip [3], designs with on the shelf

available discrete components have also been reported [4]. Different types of wireless transmission systems

for example Bluetooth, RF (Radio Frequency), Ethernet [4][5][6] have been applied with their own

advantages and disadvantages. Varied technology has also been used to develop invasive neural interfaces;

for example, the microwire array, multielectrode array, and tetrodes for interfacing with live animal brain as

well as neural tissue cultures [7][8].

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Most of the current research requiring the brain machine interface has been performed on animals

[10][11][4]. In such experiments the subject is required to be tethered by wires to the neural recording

systems thus restricting its movement. This imposes great limitation on studying the animal behaviour and

the information quality of signals [4][12]. This work is aimed at designing a multi-channel wireless data

acquisition system in order to facilitate free movement of animal under study. In this work the author has

designed and explored a hardware technique to successfully acquire neural signals and transmit them

wirelessly to a remote computer. The author‟s research has been carried out at the School of Systems

Engineering and School of Pharmacy, University of Reading; it is a part of wider project which includes

study of behavioural feeding studies and histology to investigate the mechanism through which cannabinoid

acting at cannabinoid type 1 receptors modulate hypothalamic activity using in vivo electrophysiological

techniques.

This dissertation describes the design of a wireless multichannel data acquisition platform

for use in real time brain machine interface. The system was designed to be worn in a backpack of freely

moving rat and therefore needed to be lightweight, low power and had to run on batteries. The finished work

includes an analogue front end for buffering, amplifying and filtering the signals and an analogue to digital

converter. The hardware was designed as a test bed for design strategies for a completely wireless module.

The remainder of this dissertation is divided in to six chapters. Chapter 2 presents the background

information required for the design of such system and the review of previously published works. Chapter 3

presents the detailed hardware design of each block of the system. Chapter 4 presents the methods used

towards implementation of some of the blocks. In chapter 5 results of the implemented blocks are presented.

Chapter 6 discuss the overall research, listing the limitations and making enhancements for the future and

finally chapter 7 presents the conclusion.

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Chapter 2

Literature Review:

2.1Neural Signals

A neurone or a nerve cell is a core component of brain. It is made up of a cell body (soma), input

source (dendrites), and an output source (axon). It is separated from the external environment by a cell

membrane. Connection between two neurons is called as a synapse. Neurone is responsible for transmission

and processing of neural signals in the brain. The neural signal is generated through a process of ion

exchange across the synapse.

The neural signal typically consists of two components; an action potential which is the voltage

spike generated by single neuronal synaptic activity and a local field potential which is the summation of

synaptic activity from a volume of tissue. During the process of acquisition this signal is combined with

noise from implanted microelectrode [13] and the background noise of the neuronal activity [14]. The signal

voltage level is referenced to the skull which is electrically passive; a screw drilled in a craniotomy inside a

skull serves for this purpose.

2.1.1 Action Potential

An action potential is the intersynaptic neuronal activity characterised by rapid reversal

of voltages across the cell membrane of the neurone; mediated by the voltage gated ion channels found in the

membrane. An action potential occurs when neurone sends information through the axon, away from the cell

body. It has a typical shape characterised by depolarisation and polarisation hence called as a „voltage spike‟

or an „impulse‟.

The cell membrane maintains slightly negative potential (-70mv) called resting potential

for readiness of response. This electrical gradient is caused due to selective permeability for ionic channels.

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Sodium (Na+) and potassium (K

+) are the main constituents of the neurone cell; however the mammalian

brains contain more complex combination of ionic channels which shape the properties of action potential.

If membrane potential is slightly perturbed (i.e. given a stimulus) it quickly returns to the resting potential.

However if the stimulus is sufficiently large an action potential is triggered which is a massive and rapid

depolarisation followed by slight reversal of the polarisation [25].

Figure 2.1 Schematic of action potential (Image web version [23]). The figure shows typical shape of action potential

characterised by threshold excitation, rising phase, falling phase and undershoot.

2.2 Noise

Noise is inherent in all the signal measurement instrumentation. For the measurement of

neural signals the main noise sources are electrode noise, biological noise, electronic noise and the noise

from the external sources. Electrode noise is thermal in nature, follows the standard Johnson noise equation

and is associated with metal-electrolyte interface [15]. It is directly proportional to the electrode impedance;

the signal to noise ratio (SNR) can be increased by decreasing the impedance levels. The external noise

sources include the 60 Hz line power, circuitry etc. For neural recordings the signal levels of interest are in

order of microvolts, the voltage generated due to electromagnetic interference from the line power is in order

of few millivolts. Thus the noise level is considerably large and overpowers the signal. This can lead to the

problem of amplifier saturation and malfunctioning of entire circuit. Electromagnetic interference can be

reduced by shielding of the circuit board with metal foil. Electronic configurations like differential

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measurements can also be used to reduce the effect of the common mode interference noise on the measured

signals.

Electronic systems consisting of operational amplifiers (Op-amps) always have intrinsic

minimal noise levels due to internal noise sources. This noise cannot be completely eliminated but can be

minimised by using op-amps with minimum input referred noise. Current op-amps are available with the root

mean square (rms) noise voltage levels down to nanovolts; this gives sufficiently high SNR and allows

faithful measurement of desired signals.

Biological noise is generated due to active neurones in the vicinity of the measuring electrode.

This noise has the spectral energy in the same frequency band as the desired signal but significantly low

voltage levels depending on the distance of noise source from the measuring electrode. These signals

superimpose on the action potential of the cell(s) to be monitored and contribute to the overall noise of the

system [13].

2.3 Signal Transduction

The relative geometry between the implanted electrode tip and electrically active

neurones in its vicinity determine nature of the transduced signal [15]. When a neurone fires an action

potential is transmitted along the length of the axon, thus altering the ion concentration in the extracellular

medium in the vicinity of recording electrode. This creates a potential gradient between the recording

electrode and the neural reference electrode. The amplitude and the shape of the recorded signal depends

upon various factors like, distance from the neurone, neuronal size, relative angle between the spike and the

electrode, and the surface of neurone closest to the electrode. The signal is also affected by synchronous

firing of local group of neurones (local field potential) and activity from distant (far field) neurones.

Neurones located beyond 140µm from the electrode became indistinguishable from the noise [5].

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2.4 Nature of neural signal.

Neural signals obtained from the electrodes implanted in the hypothalamus show number

of characteristic features which determine the analogue system design. The signal is typically dominated by

the action potential and the local field potential (LFP). The LFP‟s occupy the lower bandwidth below 100 Hz

and have amplitude up to 1.5 mV. The action potential are higher frequency signals ranging between 100- 10

KHz and their amplitudes are 10‟s to few 100‟s of µV peak to peak [3]. The biological noise from far field

neurones, electronic noise and electrode noise account for the voltage levels up to 20µVrms [5].

2.5 Commercial Wireless Technology

Currently there are number of options available to integrate wireless technology with the

signal acquisition hardware. These include Bluetooth, Infrared data association (IrDA), Radio Frequency

(RF) transceivers and the IEEE 802.11x Wireless adapters. These technologies differ in their on air data

throughput, power consumption, range, data security, and they come in different range of sizes.

Currently available Bluetooth technology features a data rate of 750 kbps. The designed

module demands datarate of up to 2 mbps. With lower datarates either the numbers of channels that can be

used for recording have to be decreased or the signal bandwidth has to be reduced. Bluetooth devices with an

enhanced data rate giving throughput up to 2.1 Mbps are available but they require USB adapters for their

use which adds up to number of components used. Bluetooth modules feature range from 10-100m, small

sizes (2.5 mm x 14.5 mm, BT-20 RainSun) and are available in packages like SMD (surface mount device)

and they consume low power this makes Bluetooth a good option for a single channel recording [4].

The IEEE 802.11x wireless adapters have range up to about 400 meters and datarates up to

54 mbps, this makes them ideal for multichannel recordings, however they have relatively more processing

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overloads and consume more power (on account of range). IrDA transceivers come in data rates of 16 mbps

but they require line of site communication which makes them disadvantageous for our application [5].

RF chips come in wide variety of data rates ranging from few kbps to 2 mbps [16]. The

Nordic semiconductors nRF24L01 RF chips comes in SMD package with size of 4mm x 4mm, low power

consumption (11 – 13 milliampere when active down to few µA in stand by mode) and features data rate of 2

mbps. This makes it ideal for using in multichannel wireless systems which need to operate on high data

rates [16].

2.6 Published designs

Currently numerous designs for neural signal acquisition systems have been published. These

designs can be classified under two main categories. First category includes the systems which consist of all

the signal acquisition and conditioning blocks integrated on a single ASIC chip. These chips vary in the

number of channels, gain and system bandwidth. The second category includes the systems designed with

discrete hardware components for each block. Such designs are implemented with high density multilayer

PCB‟s and surface mount component packages to reduce the system size.

Harrison et.al [24] have published a design of 100 channel neural recording chip shown

in figure 2.1.c. The chip contains 100 amplifiers, 10 bit ADC and 902-928MHz FSK transmitter. Neural

signals from one amplifier are sampled by ADC at 15.7 ksps and telemetered over the FSK wireless data

link. Power clock and command signals are sent to the chip wirelessly over a 2.765-MHz inductive link. The

chip requires only two off-chip components; a coil to receive power and command signals and a 100nF

capacitor to assist in power supply regulation.

Y. Perelman et.al. [3] have designed an analogue front end for multichannel wireless

recording, the system is designed for 12 differential channels and features band separation, digital offset

calibration, digitally programmable gains up to 60 to 80 dB, and second order low pass filter with digitally

programmable cut-off frequency. It is manufactured on a single die the system has shown a considerably low

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input referred noise of 3µV. Perelman has separated the measured signal in a low frequency band (local field

potential) and a high frequency (spike data) band by filtering and then amplifying them separately. This has

helped to decrease the dynamic range of the system and consequently lower numbers of bits are required for

ADC. The detailed discussion of this is provided in section 6.

Figure 2.2 a b) Two views of a 3-D 1024-site 128-channel fully integrated neuro-electronic

interface. (Image credited to Wise et.al. [19]). c) 100 channel neural interface (Image credited to Harrison

et.al [24])

Mohseni et.al. [18] have developed a four channel telemetric microsystem featuring on chip

alternating current amplification, direct current baseline stabilisation clock generation, time division

multiplexing and wireless frequency modulation and transmission. Morizio et.al. [17] have published design

of a 16 channel neural preconditioning device that is designed to acquire data from electrodes implanted in

animal brain. It is fabricated using CMOS technology. The system features buffer amplifier, band pass filter

and selectable gains.

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The advantage of ASIC chips is; due to integration on single die the system noise is reduced to

great extent and the signals are reproduced faithfully and reliably. Their major disadvantage is that only

analogue circuitry and part of digital circuit like multiplexer can be integrated and embedded with the

electrode array. Such systems still require the digital microcontroller for digitising the signals and interfacing

with the wireless technology. Moreover the power requirement including that of the microcontroller and

wireless devices put heavy demand on size of battery required. All the published designs have further

interfaced their ASIC chips to the microcontroller and the transmission boards, this makes the ASIC‟s very

little advantageous. The development time required and the IC fabrication cost incurred further make such

chips costly for laboratory research. However ASIC have been proved most efficient and reliable for human

brain interfacing [19]. Currently silicon micromachined electrode arrays with fully integrated, high density

signal processing electronics consisting up to 1024 multiplexed sites have been reported( figure 2.1.a). These

electrode arrays have been used for inter-cortical neural signal recordings from human subjects [2].

The second category of system include design with off-the shelf available discrete components,

numerous of such designs have been published [4][20][21][22]. Op-amps with input referred noise down to

nanovolts have made possible systems with very low input referred low noise. Furthermore these op-amps

are available in number of miniature surface mount packages like TSOP, SOT etc, which has kept the size of

such designs within the required limits.

Hsin-Yung Chen et.al. [4] have published a design of 8-channel, Bluetooth based wireless data

acquisition system. The designed analogue front end is made up of precision instrumentation amplifiers

(INA2128, Burr-Brown, USA), which feature very low input referred noise and a high common mode

rejection ratio. The module is packed in box of size 4 cm x 3.5 cm x 1cm and weighed 25.3 gm, which is a

considerably small size even for lab animal like rat.

Gosselin et.al. [20] have published design of low noise 16 channel neural data acquisition system,

analog channel features a low noise (10nV/√Hz), high common mode rejection ratio (CMRR =83.4dB) input

stage, a 4th order bandpass filter and a selectable gain (60.8dB – 100.8dB). Downe et.al. [10] have published

the design of 4 channel system, their bandwidth is 1Hz to 3 KHz, signals are sampled at 10ksps and have

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used Bluetooth module for wireless transmission. These published works differ in the number of channels

used, order of the filter, gain, wireless technology etc.

Currently there are few companies which commercially manufacture neural recording systems;

namely Plexon (Dallas, TX), Neuralynx (Tuc-son, AZ), Tucker-Davis Technologies (Alachua, FL), and

Alpha Omega (Nazareth, Israel) [5]. The products feature wide variety of options which include channel

count, gain, operating frequencies, input impedance, output impedance and dimensions.

Wireless neural headstage system available from Plexon (Fig 2.3.a) features 15 channels, system gain of 500,

input impedance of 22 MΩ at 1 KHz, input referred noise of 10 µV rms and the bandwidth of 0.5 Hz to 8

KHz.

Figure 2.3: Commercially available neural recording systems. a) Wireless receiver and transmitter from

Plexon Neurotechnology Research Systems, USA [26]. b) Wireless preamplifier connected to head

stage available from Alpha Omega technologies, Israel [27].

Neural signal system available from Alpha-Omega (Fig 2.3.b) has an integrated microswitch

which can instantly switch between recording and stimulation mode from any electrode, thus this is a

bidirectional system. It features variable gain 100x or 1000x; different highpass filter (1 Hz 0.8 Hz) or low

pass filter (10 – 15 KHz) filter options. How ever these products are heavy, sizes exceeds 10 cm x 10cm, and

require the subject to be tethered by wires thus not suitable for our application.

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Chapter 3

System Design

3.1 Overview

This chapter presents the design of a wireless neural data acquisition system. The

system was designed to be worn in a backpack of freely moving subject thus facilitating signal recording in

an unrestrained subject.

Figure: 3.1 Block diagram of the designed system, a) System blocks for buffering, filtering,

amplification, conditioning and transmission of signal. b) System blocks for receiving, conditioning and

analysis of signal.

The figure 3.1 shows block diagram of the proposed system. The subject is implanted

with eight electrodes (NB labs, Texas), such that the tip of the metal wire lie in the desired hypothalamic

region. The interested signal amplitude is in the range of +/- 10 μV to +/- 1.5 mV and the signal frequency of

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interest is from 1 Hz to 10 KHz. The design is divided in to two main stages the transmitter end and the

receiver end.

The input stage to the system consists of an analogue front end and a digital back end. A

passive highpass filter is designed to remove any DC component present at the input. The second stage is a

non-inverting amplifier with gain 11 followed by an active low pass filter with an amplification factor of

121. The low pass filter has cut-off frequency of 10 KHz, this act as an anti-aliasing filter. The third stage is

a time division multiplexer to choose from one of many inputs to the Analogue to Digital converter (ADC).

The fourth stage is ADC converter to convert the analogue signal in to digital for data transmission. The

third and fourth stage is included in to the microcontroller. The fifth stage is a wireless transmitter. The

design utilises RF communication with a data rate of 2 mbps.

On the receiver side the first stage is the receiver module. The data is received as a digital

stream. The second stage consists of data pre-processor which is a microcontroller which reads the digital

bits and then demultiplexes in to the respective channels. This signal is then fed to the digital to analogue

converter to reproduce the original signal.

All the circuit simulation was done in the National instruments Multisim software.

3.2 Electrodes

Chronically implanted electrodes are the first stage in the neural recording hardware.

Consequently the quality of interface between the electrode and extracellular electrolyte determine the

quality of the signals measured. At the tip of the electrode the neuronal activity develops a potential gradient

between the electrode and the reference screw. This voltage is amplified and measured by the electronic

circuitry. As the brain machine interface require chronic implants the electrodes must be inert to the

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extracellular electrodes and should not produce any toxic effects affecting the subject.

Figure 3.2: a) Microwire electrodes connected to Plexon Connectors b) Close view of tip of connector c) The

Plexon Connector.

Microwires are set of 8 to 32 very thin wires typically made up of Quartz-Platinum/ Tungsten. The outer

diameter is few tens of micrometer (µm) and tip is about 10-15 µm. The input impedance is 0.2 MΩ- 4MΩ

at 1 KHz. Because of their small size and geometry tetrodes provide isolation of more neurones with higher

reliability.

3.3 High Pass filter

The first stage of the analogue front end consists of passive highpass filter. This stage acts as

a DC (direct current) voltage rejection circuit. The amplifier circuit has amplification of 1500 and the supply

voltage to the Op-amps is +/- 3.3 V. Thus the minimum voltage that can saturate the amplifiers is 3.3/1500 =

2.2 mV. With a high gain amplifier any amount of DC level is a disadvantage, as the signals of interest will

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be superimposed on this voltage. This leads to unnecessary power consumption in amplifying of this voltage

and may drive the amplifiers to saturation. The input to the highpass filter is the neural signal from the

implanted electrodes and the output is given to the amplifier. The input stage of the amplifier has high input

impedance and the highpass filter is in series with the amplifier, thus the overall circuit exhibits high input

impedance.

3.4.1 Highpass filter design

This filter is primarily required to reject any DC component in the signal while pass all other

frequencies. The passive RC filter is implemented as shown in figure 3.4.1 the resistor R1 comes in parallel

with input impedance of the circuit. Hence to increase the input impedance and to decrease the current

flowing through R1, value of R1 is kept very high equal to 10 MΩ. The capacitor C1 is in series with the

input signal and is of 1µF. R1 and C1 form the required highpass filter with cut-off frequency given by,

Fh = 1 / (2π R1C1) (1)

= 1 / (6.28) (2)

= 0.16 Hz. (3)

Thus DC component of 0Hz is rejected while all other frequencies are passed.

3.4.2 Highpass filter simulation

As shown in figure 3.4.1 capacitor C1 and resistor R1 form the passive highpass filter with

cutoff frequency 16 mHz. The figure 3.4.2 shows the bode plot simulation result of highpass filter obtained

in Multisim. It can be seen that the DC component of the signal is rejected while all other frequencies are

passed.

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Figure 3.4.1 Simulation circuit of high pass filter formed with capacitor C1 and resistor R1. XFG1 is

signal generator used to provide sinusoidal input. XBP1 is the bole plotter and XSC1 is an oscilloscope.

Figure 3.4.2 Simulation result of the high pass filter. The Bode plot shows -3dB gain

at 16 mHz which is the cutoff frequency and a maximally flat frequency response there after.

3.5 Lowpass filter

The signal from the highpass filter is direct coupled to the next stage. After filtering and

amplification the analogue signal needs to be sampled at finite frequency and then converted in to digital

form. If the signal is not sampled at sufficiently high frequency then it leads to distortion of signal called as

25

„aliasing‟. Aliasing is caused when the sampling frequency of the signal is less than twice the maximum

frequency content of the signal.

The sampling frequency determines the rate at which data is produced by the ADC. With

higher sampling rates the signal fidelity increases and quantisation noise decreases however this leads to

increase in datarate. The wireless modules have finite datarates up to 2 mbps. This sets an upper limit to the

datarate of the overall system, the sampling frequency and consequently the maximum frequency content of

the system. The lowpass filter limits the maximum frequency content of the signal so as to avoid aliasing and

determine the sampling frequency.

3.5.1 Lowpass filter design

For our system the maximum frequency of interest is 10 KHz, this is the cutoff frequency of

the filter. To suppress all the frequencies above the cutoff for neural interface we require a minimum of 4th

order roll off slope for the frequency response [5] and for signal amplification without introducing any non

linearity by different amplification factor at different frequencies we require a maximally flat response in

pass band this requirement is satisfied by sallen-key filters thus we have implemented a fourth order sallen-

key analogue filter. An over gain of 1331 is designed to amplify the signals without saturating the amplifiers

this is divided in three stages, each stage exhibits a gain of 11.

26

Figure 3.5.1 Circuit diagram of a second order Sallen-Key low pass filter. The op-amp is in

non-inverting configuration, gain is set by R3 and R4. The capacitors C1, C2 and resistors R1,R2 form the

filter.

The cutoff frequency for the second order Sallen-Key low pass filter is given by,

(4)

(5)

With R1 = 5.1 K Ω, R2 = 15.4 KΩ, C 1= 1nF, C2 = 3.3nF

fc = 9885.9 Hz (6)

This is designed cutoff frequency.

The gain for a non-inverting amplifier is given by,

A = 1 + (R4/ R3) (7)

With R4 = 100 K Ω and R3 = 10 K Ω

A = 11. (8)

27

3.6 Analogue Front End simulation

Figure 3.6.1 shows the simulation circuit diagram for the analogue front

end it includes the highpass filter, the non-inverting amplifier and the low pass filter. The overall gain of

1331 was distributed as 11 x 11 x 11 among the three op-amps. The input is given to the capacitor C1

through the signal generator XFG1 and the output is observed using the oscilloscope XSC1.

Figure 3.6.1 Multisim Simulation of Analogue front end. XFG1 is the signal generator and XSC1 is

the oscilloscope. The op-amp U1A forms the non inverting amplifier, U1B and U1C form the form the 4th

order low pass filter.

28

Figure 3.6.2 Multisim simulation Bode plot for Low pass filter. The figure shows maximal flat response till

the cutoff frequency of 9.933 KHz with a gain of 61.672 dB and a fourth order roll off there after.

Figure 3.6.3 Simulation output for the analogue circuit. The red sinusoid is the input signal and the green

sinusoid the amplified output. The output is amplified and slightly phase shifted version of the input.

29

3.7 Analogue to Digital Conversion

In order to transmit the signal in digital form the analogue signal is required to be converted

in to digital bytes, the ADC servers this purpose. The system is designed for 8 parallel channels. The signals

from these 8 channels need to be time division multiplexed so that one of the eight channels at a time is

connected to the ADC and all the channels are sequentially scanned. The maximum signal frequency and the

signal amplitude are the deciding factors for the design of ADC. The maximum frequency content of the

signal is 10 KHz. To avoid aliasing the signal should be sampled at 20 KHz. The quantisation error should

be minimum and depends of the resolution of ADC. For a 12 bit ADC the SNR is given by

SNRdb = 1.761 + 6.0206*Q ; Q is number of bits (8)

For a 12 bit ADC we have,

SNRdb = 74 db (9)

For signal of 1mV this adds to noise level of 200 nV. This is sufficiently low for required signal

fidelity of our application.

The required datarate is given by,

D = sampling frequency x ADC resolution x number of channels (10)

= 20 x 103 x 12 x 8 (11)

= 1.92 mbps. (12)

Currently available microcontroller packages like PIC24 (Microchip technologies) come with inbuilt

multiplexer and ADC. Thus the control and timing signals required for the same can be generated internally

in the microcontroller itself. This decreases the number of components as well as the size of the board.

30

Figure 3.7 shows the block diagram of ADC conversion. The first block is time division multiplexer with

eight analogue inputs, the second block is analogue to digital converter and the third block is wireless

module for transmission of the signal.

3.8 Wireless Module

The wireless module will be mounted on subject‟s backpack and hence should be considerably

small in size. The required wireless transmission datarate is 1.92 mbps. Currently available Bluetooth

modules feature on air data rate of upto 750 kbps. Enhanced Datarate (EDR) Bluetooth module WT12

available from Bluegiga Technologies feature datarate of 2.1 mbps and comes in surface mounted device

(SMD) package of size 26mm x 14 mm. To use this module with full datarate of 2.1 mbps require it to be

interfaced with a USB adapter to stream input data. This increases the number of components and hence the

power consumption. Thus Bluetooth can be used with reduced datarates for such applications.

Digital transmission using radio frequency (RF) chips feature wide variety of on air data rates

ranging from few kbps to maximum upto 2 mbps. nRF24L01+ RF chip available from Nordic

Semiconductor features on air datarate of 2mbps, available in compact 4mm x 4mm, 20 pin QFN package

and ultra low power consumption (900nA) in power down mode. It features four wire SPI (Serial peripheral

31

interface), 8 byte FIFO (first in first out) buffer and is a transceiver module can be configured as transmitter

or a receiver. It can be directly interfaced with the microcontroller and is suitable for application.

3.9 Digital to Analogue Converter

The data received at the wireless receiver is in digital form. In order to be interfaced with neural

signal analysis software (Neuroexplorer Nex Technologies) it is required to be converted in to an analogue

signal.

Figure 3.8 Block diagram of the receiver side. The first block is the receiver module, the second block is 8:1

de-multiplexer which demultiplexes the input digital stream in to respective analogue channels, and the

fourth block is signal analysis software.

The received signal is made up of data from all the 8 parallel channels as a serial bit

stream. This data should be demultiplexed in to respective 8 channels before it is given to digital to analogue

converter (DAC). The analogue signal is then fed to the computer for further analysis.

32

3.10 Power Supply

Power for the board is supplied by 3.7 V, 1.1 Ah, Li-ion battery. It measures 54 mm x

35 mm x 7 mm and weighs 20 g. As the neural signal contains positive as well as negative voltage levels the

op-amp needs a dual power supply. Positive voltage of 3.3V is supplied through high precision, low drop out

voltage regulator KF33BD (STmicroelectronics, Geneva, Switzerland). It comes in 8 pin SOIC8 (Small

Outline Integrated Circuit) package. The negative voltage is supplied through voltage inverter IC AMD8828

(Analog Devices, Shanghai, China). It is a charged pump inverter and comes in 6 pin SOT23 package.

33

Chapter 4

Methods

4.1 Overview

This chapter presents the methodical approach towards development of the 8 channel

wireless neural signal acquisition module. The schematic of the circuit diagrams, Printed circuit board (PCB)

design and layout was done in Eagle layout editor (Cadsoft technologies) software package. Prototype for the

single channel analogue front end was built and tested. The PIC24 was configured for single channel ADC

and was tested. The code was completed to interface the RF chip with PIC24 and configure it to transmit a

character.

4.2 Analogue front end

A two layer PCB was designed for the single analogue channel, voltage regulator and the

voltage inverter. High board density was achieved using smallest available hand-solderable parts (size 0402

for the passive components), 0.4 mm signal track and 0.6 mm drill holes. The amplifier stages were

protected from electromagnetic radiation by shielding the board by a grounded metal shield placed over both

side of the board. Figure 4.3.1 shows the circuit layout for the analogue front end and figure 4.3.2 shows the

designed PCB for the single channel analogue front end. The IC TLC994 which comes in SMD package of 4

op-amps in single chip and low input referred noise of 9 nV/√Hz was selected to build the Analogue front

end.

34

Figure 4.3.1: Circuit Layout for the analogue front end. a) High Pass Filter b) Non-Inverting Amplifier

c) Low-pass filter d) Connector and bypass capacitors for the battery e) Positive Voltage Regulator

f) Negative Voltage Regulator

Figure 4.3.2 PCB prototype of Analogue front end. The connectors are of the input signal, power

supply and output signal.

35

4.3 Analogue to digital converter.

PIC24F microcontroller (Microchip, Shanghai, China) was programmed for single channel ADC.

The code was implemented and tested on Explorer16 development board (Microchip, Shanghai, China). It

consists of onboard potentiometer to vary the voltage at the analogue input pin. The ADC was configured for

operating frequency of 500 KHz and the converted digital voltage was displayed on onboard Liquid Crystal

Display (LCD) screen.

4.4 Wireless link.

The following section gives the method to setup the wireless link for a single channel. The

signal from the ADC (which is part of microcontroller) is given to the RF transceiver over the serial

peripheral interface (SPI) line of the microcontroller. The RF transceiver needs to be configured as a

transmitter; this is done by sending the appropriate control commands to the resistors of RF transceiver.

Once it is configured as transmitter then the digitised data is written on the First in First out (FIFO) buffer of

the transceiver chip. When there is some data on the buffer the RF chip this data is then converted in to

packet by adding start and stop bits at the beginning and end of the data byte and then the data is transmitted.

On the receiver end; first the RF chip is configured as the receiver by writing appropriate control

signals in the control register of the RF chip through the SPI. The chip then monitors the signals received

from the receiver antenna for data. Once it receives the start bit, it identifies the data signal and it is written

in to the FIFO receiver buffer. This byte can then be read by the microcontroller to be given to the digital to

analogue converter to convert it back in to analogue signal.

36

Chapter 5

Results

5.1 Overview

This chapter presents the results for testing of the analogue front end and the ADC. The analogue

front end was tested with test inputs from the laboratory instruments and the test signal from the saline

solution which are identical to the neural spike signals. The ADC was implemented on the Explorer16 board

and the test inputs were provided by varying the onboard potentiometer. The tables show the results for the

analogue front end and the ADC.

5.2 Analogue Front End

The prototype was tested by giving frequencies from the signal generator (Thrulby Thander

Instruments) as the input and the output was observed on two channel digital storage oscilloscope (Tektronix

TSD1002) The input was fed over the range of frequencies from 1 Hz to 10 KHz. The minimum input signal

from the signal generator was 500 mV; this was above the maximum input limit of the analogue front end

and would saturate the amplifiers. To solve this problem the input signal was fed through a voltage divider

which divided the input voltage by a factor of 10000 (10-4

) so that now the minimum input voltage to the

analogue front end is 50μV.

37

Figure 5.2.1 Laboratory setup for the test of analogue front end. Figure shows the Signal generator, digital

storage oscilloscope and the analogue front end.

Figure 5.2.2 Output from the digital storage oscilloscope. The figure shows the input signal and the

amplified output signal. The output signal is slightly phase shifted as compared to the input signal.

Following tests were carried out for the testing of analogue front end

1) Connect the signal generator output to the voltage divider circuit.

2) Connect the battery to power the analogue circuit.

3) Connect the voltage divider output to the input of the circuit.

4) Connect the output of the analogue circuit and the signal generator to the oscilloscope.

5) Observe the output on the oscilloscope.

38

Table 5.2 Testing result for the Analogue Front End.

No

Frequency in

Hz

Input Voltage peak to

peak (Vp-p)

In microvolts

Output Voltage

peak to peak (Vp-p)

In Volts

Gain in dB

1 500 500 0.933 65.41

2 1K 500 0.933 65.41

3 2K 500 0.933 65.41

4 5K 500 0.933 65.41

5 7K 500 1.066 66.57

6 8K 500 1.1 66.84

7 9K 500 1.133 67.10

8 10K 500 0.986 65.90

9 11K 500 0.986 65.90

10 12K 500 0.640 62.14

11 13K 500 0.5 60

12 15K 500 0.345 56.77

Figure 5.2.3 Frequency response of analogue front end. Figure shows maximally flat response with

gain of 65.41 in pass band with cutoff frequency at 10 KHz and a fourth order roll-off thereafter.

39

For neural signals a minimum fourth order low pass filter is required for good replication of signal [5].

Figure 5.3 shows the actual frequency response, it is evident that any frequencies above the cutoff will be

rejected.

5.2.1 Discussion

The results obtained from the testing of the analogue front end are in conformation to the

initial system specification. As can be seen from the figure 5.2.3 the circuit shows maximally flat frequency

response in the pass band; this ensures that the signal fidelity is maintained as the signal is equally amplified

over the entire frequency range without introducing any non linearity by the circuit. The response shows an

overshoot before the cutoff frequency, this is the characteristic response of the sallen-key filters. The

overshoot is 1.7 dB which is low and is in the upper end of the frequency band where the signal amplitude is

in microvolts thus the non-linearity introduced by this overshoot can be neglected. Figure also shows the

fourth order roll off after the cutoff frequency. This is ideal as it ensures that any frequency after 10 KHz is

not passed through the filter.

The non-inverting amplifier at the input stage ensures very high input impedance but before the

actual implementation of the circuit to the implanted electrodes the actual input impedance exhibited by the

circuit must be tested as any stray capacitance can cause surge current which may prove harmful for the

brain tissue.

40

5.3.1 Digital to Analogue Converter

PIC24F (Microchip, Shanghai, China) microcontroller was programmed as single channel

ADC. The voltage levels were varied using an onboard potentiometer. The available voltage range was from

0 – 3.3V. The output from the analogue front end is in the same positive voltage level. The voltage across the

potentiometer was measured with the multimeter so as to compare with the ADC reading.

Following steps were carried out to test the ADC

1) Power the Explorer16 board for PIC24.

2) Connect the MPLAB ICD2 (in-circuit debugger) to the PC and Explorer board.

3) Burn the C code in the PIC24 through ICD2.

4) Vary the input voltage to the microcontroller via the potentiometer.

5) Read the voltage on the LCD.

6) Check the voltage across the potentiometer using a multimeter.

Table 5.3 Testing result for the Digital to Analogue Converter.

No Multi-meter Reading

in milivolts

PIC Reading in

milivolts

Error in mV

1 100 100 0

2 202 200 2

3 300 300 0

4 405 400 5

5 400 500 0

6 1002 1000 2

7 1500 1500 0

41

8 2000 2000 0

9 2500 2500 0

10 3000 3000 0

11 3300 3296 0

5.3.2 Discussion

The result obtained from the test show that the PIC24F ADC an accurately convert the input

analogue voltage in digital form. The C code to configure PIC24F as ADC was implemented on Explorer16

development board and hence the range of test input voltage was limited to positive side from 0 to 3.3 volts.

For validation of the ADC to be incorporated in the system design the ADC should be tested over the entire

input range from -3.3 V to 3.3 V. More over it should be tested with the sinusoidal input with frequency

varying over the range of the actual neural signal. When the ADC is implemented for multichannel data

acquisition; it scans several analogue inputs at a finite frequency. This scanning frequency should be

sufficiently high in order that the sampling frequency requirement to avoid aliasing should be satisfied. This

depends on the total sampling and conversion time of the ADC which should be sufficiently small. However

with small sampling and conversion times the accuracy of ADC decreases and this is a bottleneck in

selection of the ADC. Thus for the practical implementation of the ADC it should be tested with multiple

inputs and with the signals over the required frequency range.

42

Chapter 6

Discussion

The work presented in this dissertation was motivated by the long term goal of developing a

wireless link between chronically implanted electrodes and a host computer where the signals can be

analysed. Such a system when mounted in subjects backpack will allow complete freedom of movement to

the subject without causing any discomfort. Such devices need not be limited to use on laboratory animals

but can be enhanced to use as neural interface for neuroprosthetics where the signals from the cortex can be

used for real time control of prosthetic arms, wheel chair and even to emulate human voice.

An ideal system configuration for a fully implantable neural interface would include a low noise

analogue front end with desired number of channels operating over desired frequency band and a digital back

end to multiplex the channels and convert the analogue signal to digital with minimal quantisation noise. The

wireless module should provide enough on air datarate without imposing the limit on maximum frequency

contained. An alternate approach is to employ data compression techniques so that given channel and

frequency specifications can be met within the datarate of the wireless module. The system should consume

low power thus resulting in lasting battery life. Spike detection algorithms can be implemented on the

onboard processor in order to reduce the amount of information that is required to be transmitted wirelessly

to the external receiver. A number of technical obstacles prevent such a system from being a reality. The

work presented in this dissertation has attempted to engineer solutions to few blocks while merely

uncovering others.

6.1 Analogue Front End

The analogue front end was designed to investigate the noise performance, gain and filter matching

and buffering that will be required for the first stage of the implantable neural interface. Initially an active

highpass filter was implanted instead of a passive high pass filter but the performance for rejection of the DC

was found to be same. An active filter requires an additional op-amp for its implementation and hence

43

increases the number of components. As the overall size of the board should be small and additional

components increase the noise in the system it is preferable to reduce the number of components. Hence the

system was designed with a passive high pass filter. The simulation results as well as the actual

implementation on PCB showed desired rejection for the DC component of the signal. As the designed

resistor value of the filter is in mega ohms the attenuation caused by the filter is negligible. This resistor

comes in parallel with the internal resistance of the first amplifier stage. The input impedance of op-amp is

high in order of mega ohms this gives very high input impedance to the overall circuit and hence there is

negligible amount of input current. This assures that the current flowing through the electrodes does not

cause any harm to the brain tissue. The circuit was built with surface mount package in order to reduce the

board size.

The system was designed to have an overall gain of about 1000-1500 so that the signals over the

interested voltage levels are amplified without saturating the amplifier. The maximum gain for a single op-

amp depends on its gain bandwidth product hence the overall gain was divided in to three stages of gain

11.The signals from the high pass filter are direct coupled to the first amplifying stage which is the non-

inverting amplifier. This stage amplifies the smallest amplitude signals without causing any distortion or any

phase change in the signal. Due to the capacitors the filtered signal is slightly phase shifted than the input

signal. This will only add small amount of time lag without affecting the signal integrity.

A minimum fourth order lowpass filter is required to minimize signal distortion and preserve

signal fidelity [5]. One low pass filter requires seven components to build it; this account for considerable

amount of board space and will be problematic when the design will be implemented for number of

channels.

In a signal recorded by an extracellular microelectrode, the action potential i.e. the neuronal firing

activity occupies the frequency band of 100 Hz-10 KHz and its amplitude is in range of microvolt. The

LFP‟s occupy lower frequencies, below 100 Hz, with amplitude below 5 mV. This difference in the voltage

levels result in to high system dynamic range. As the entire combined signal is passed the minimal required

precision of the subsequent data acquisition is 10 bit, defined by the signal SNR. Since the firing action

44

potentials have 10 times lower magnitude than the LFP‟s, it can be amplified only to one tenth of the output

swing. The maximum amplifier gain is limited by the LFP magnitude and chip supply voltage. If the

amplifier gain is set high enough that the action potential are amplified to the maximum voltage then the

amplifiers are saturated by the LFP‟s on contrary if the amplifier gain is set so that the amplifiers are not

saturated by the LFP‟s then higher resolution ADC is required as the action potential are represented by

lower voltages. With higher resolution ADC the datarate increases.

These limitations can be overcome by splitting the signals in to two bands, as shown by

Perelman et.al. [3]. Thus the LFP and action potential parts can be processed by separate channels

amplifying both to the full swing. Consequently the system dynamic range also decreases as determined by

the SNR of the action potential signal. With an ADC of seven bits and 500μV action potential signal, the

LSB becomes 4.5μV and the associated quantisation noise becomes 1.3μV which is lower than 5μV signal

noise.

6.2 Digital Backend

The digital backend is required to be implemented after the analogue front end for completion of

the entire module. The main parts of the digital back end are the multiplexer, ADC and the wireless digital

transmitter. The microcontroller modules like PIC24F come with inbuilt ADC with an ability to serially scan

multiple inputs, hence the multiplexer and ADC come in single chip of the microcontroller. The same

microcontroller can also be used for generating timing signals. This design has got a limitation that at higher

sampling and signal frequencies the accuracy of the ADC decreases. Hence this design is required to be

tested and validated to be implemented in actual system. An alternate approach would be to use an IC

dedicated for ADC which can offer good accuracy at high frequencies.

The analogue (including RF) and digital circuitry work on different voltage levels. The digital

signal lines swing between ground and positive power supply of 3.3 V and switching time for digital lines is

fast in nano second range. Due to large amplitude and fast switching time the signal will contain

45

considerable amount of high frequency components irrespective of switching frequency. On the analogue

side the input signal from the electrodes and the amplifiers is in the range of microvolts and the RF chip also

operates in range of microvolts. The magnitude difference between digital and analogue signal is therefore

large; this may cause corruption of the RF or the analogue signals due to electromagnetic interference. Thus

these signal lines are required to be separated properly and should be provided separate power supplies.

6.3 Future Work

The future work for the project will include completing the hardware implementation of the

designed module and validating it for eight channels. The further work needed for this is to test the ADC

over the range of input voltage and frequencies. Interface the analogue front end with the ADC and validate

it with the actual neural signals. The wireless RF link will first be established and tested with test digital data

and then the output from the ADC will be interfaced to the wireless link. At the receiver end the received

signal will first be demultiplexed and then converted back in to analogue signal. The DAC is required to be

implemented and tested with signals over the voltage and frequency range. The output from the DAC is

required to be conditioned so that it can be fed to the PC for neural signal analysis.

This work can further be to increase the number of channels. The amount of data transmitted

can be reduced by implementing onboard spike sorting algorithms and transmitting only the required

information. An alternate approach can be to implement the data compression techniques before transmitting

the data. It will be interesting if bidirectional data transmission can be made possible for such modules so

that not only the neural signals be read from the implanted electrodes but also the brain cells can be

stimulated.

46

Chapter 7

Conclusion

Analogue front end and ADC remain the implemented part of the project. Following

conclusions can be drawn from the testing results of analogue front end; the passive highpass filter acts ideal

to reject the DC frequency component, implementing an active high pass filter will lead to increase of

components on board. The low pass filter implemented with sallen key design gives an ideal flat response in

pass band and hence is a good choice. The gain set for the analogue front end is sufficient to amplify the

required range of neural signals without saturating the amplifiers. The testing results for the ADC conclude

that the PIC24F gives sufficiently accurate conversion results.

The neural interface designs with discrete components are bulky and weigh more as compared

to the system designed with ASIC chips. However they are low cost and time efficient alternative for

experiments on lab animals where few hours of recording is needed.

47

References:

1. Delgado, J.M. Physical control of the mind (Harper and Rowe, New York, 1969)

2. John P. Donoghue, “Connecting Cortex to Machines: recent advances in brain interfaces”, Nature

Neuroscience supplement, volume 5, nov 2002

3. Yevgeny Perelman , Ran Ginosar, “Analogue front end for multichannel neuronal recording

system with spike and LFP separation”, Journal of Neuroscience Methods 153 (2006) 21–26

4. Hsin-Yung Chen, Jin-Shang Wu, Brian Hyland, Xiao-Dong Lu, Jia Jin Jason Chen, “A low

noise remotely controllable wireless telemetry system for single-unit recording in rats navigating in a

vertical maze”, Med Biol Eng Comput (2008) 46:833–839

5. Iyad Obeid, “A Wireless Multichannel Neural Recording Platform for Real Time Brain Machine

Interfaces”, Doctoral Thesis, Department of Biomedical Engineering Duke University. 2004

6. J. Morizio, P. Irazoqui, V. Go, J. Parmentier, “Wireless Headstage for Neural Prosthetics”

Proceedings of the 2 International IEEE EMBS Conference on Neural Engineering

Arlington, Virginia · March 16 - 19, 2005

7. J. K. Chapin and K. A. Moxon, Eds., “Neural Prostheses for Restoration of Sensory and Motor

Function”, Methods and New Frontiers in Neuroscience. CRC Press, Boca Raton, 2001.

8. C. T. Nordhausen, E. M. Maynard, and R. A. Normann,”Single unit recording capabilities of a

100 microelectrode array, Brain Res, vol. 726, no. 1-2, pp. 129-40., 1996.

9. J. K. Chapin, “Using multi-neurone population recordings for neural prosthetics, “Nat Neurosci,

vol. 7, no. 5, pp. 452-5., 2004.

10. R.W. Downe, J.H. Blaise, and J.D. Bronzino, “Design of a Digital radio- frequency telemetry

system For recording of electrophysiological data in freely moving

Rats”, 29th IEEE proceedings of Bioengineering Conference March 2003

11. Shaohua Xua, Sanjiv K. Talwar, Emerson S. Hawley, Lei Li, John K. Chapin, “A multi-channel

telemetry system for brain microstimulation in freely roaming animals”, Journal of Neuroscience

Methods 133 (2004) 57–63

48

12. Moosung Chae Kuanfu Chen Wentai Liu Jungsuk Kim Sivaprakasam, M, “A 4-Channel

Wearable Wireless Neural Recording System”, IEEE International symposium on Circuits and

Systems 2008.

13. Borkholder D.A, “Cell based biosensors using microelectrodes”. Ph.D. Thesis, University of

Stanford, 1998.

14. Guillory K, Normann R. “A 100-channel system for real time detection and storage of extracellular

spike waveforms”. J Neurosci Meth 1999; 91:21–9.

15. Gesteland, R.C., Howland, B., Lettvin, J.Y. and Pitts, W.H, “Comments on Microelectrodes”

Proceedings of the IRE, 47:1856-1862 (1959).

16. www.nordicsemi.com

17. J. Morizio, D. Won, I. Obeid, C. Bossetti, M. Nicolelis, P. Wolf, “16-Channel Neural pre-

conditioning device”, Proceedings of the 1st International IEEE EMBS Conference on Neural

Engineering Capri Island, Italy. March 20-22,2 003

18. Pedram Mohseni, Khalil Najafi, Steven J. Eliades, and Xiaoqin Wang, “Wireless Multichannel

Biopotential Recording Using an Integrated FM Telemetry Circuit”, IEEE Transactions on Neural

Systems and Rehabilitation Engineering, Vol. 13, No. 3, September 2005

19. K.D Wise, D. J Anderson, J.F. Hetke, K. Najafi, “Wireless implantable Microsystems: High

density electronic interfaces to Nervous Systems”, Proceedings of the IEEE volume 92, No.1, Jan

2004.

20. Benoit Gosselin, Mohamad Sawan, “A low power portable multichannel neural data acquisition

system”, 10th Annual Conference of the International FES Society July 2005 – Montreal, Canada

21. Shaohua Xua, Sanjiv K. Talwar, Emerson S. Hawley, Lei Li, John K. Chapin, “A multi-channel

telemetry system for brain microstimulation in freely roaming animals”, Journal of Neuroscience

Methods 133 (2004) 57–63

22. Chia-Nan Chien, Fu-Shan Jaw, “Miniature telemetry system for the recording of action and field

potentials”, Journal of Neuroscience Methods 147 (2005) 68–73

23. Characteristics of Action Potential [Online] [Cited: 07 26, 2007]

http://courses.cit.cornell.edu/bionb441/FinalProjects/f2006/sjj26/491_SJJ26/NeuroJhun.htm

24. Harrison, R.R, Kier, R.J, Greger, B, Solzbacher, F, Chestek, C.A, Gilja, V, Nuyujukian,

P, Ryu, S.I Shenoy, K.V, “Wireless neural signal acquisition with single low-power integrated

circuit”, IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008.

49

25. E.R Kandal, Principals of Neuroscience, 4th

edition, The McGraw-Hill Companies, Inc.

26. Plexon Neurotechnology Research systems, USA. Wireless Headstage system product datasheet,

[Online] [Cited: 6 3, 2009]

27. Alpha Omega Neuroscience Technology, Israel. 4 channel Headstage Preamplifier Product datasheet

[Online][Cited: 10 6 2008]

50

Appendix

1. Datasheet of PIC24F

2. Datasheet of TLC994

3. Datasheet of nRF24L01 RF chip

4. Datasheet of KF33 voltage regulator

5. Datasheet of AD8828

6. C code for ADC conversion