Multichannel Time-Variant Readout Electronics of DePMOS based APS for the XEUS Wide Field Imager

Matteo Porro MPI Halbleiterlabor [email protected] FEE 2006 Perugia

Multichannel Time-Variant Readout Multichannel Time-Variant Readout Electronics of DePMOS based APS for the Electronics of DePMOS based APS for the

XEUS Wide Field ImagerXEUS Wide Field Imager

M. Porro, S. Herrmann, L. Strueder, J. Treis

P. Lechner

G. Lutz, R. H. Richter

C. Fiorini, L. Bombelli, G. Langfelder, A. Longoni

W. Buttler

MPI for extraterrestrial physics

PNSensor GmbH

MPI for physics

Politecnico di Milano & INFN

Ingenieurbuero Werner Buttler


XEUS projectXEUS project ((XX-ray-ray EEvolvingvolving UUniverseniverse SSpectroscopy)pectroscopy)

Exploring the early universe by imaging spectroscopy in the X-ray band

(100 eV – 30 keV)Observation of the hot Universe at high redshifts

Device active area 7.68 x 7.68 cm2

Device thickness 450 mPixel size: 75 x 75 m2

Position resolution ca. 30 mTotal 1024 x 1024 pixel cells

Energy resolution @ Mn-K 125 eVEnergy resolution @ C-K 50 eV

System noise 3-5 e- ENC


XEUS WFI specificationsXEUS WFI specifications

XMM EPIC XEUS WFI

energy range 0.1 ... 15 keV 0.1 ... 20 keV

focal length 7.5 m 50 m

angular resolution 15 arcsec 2 arcsec

focal plane res. 36 µm / arcsec 250 µm / arcsec

field of view 30 arcmin 5 arcmin

collection area 1 keV 0.5 m² 6 m² (30 m²)

time resolution 70 msec 1 ... 5 msec

operating temp. 130 K > 180 K

thickness 300 µm ➞ 500 µm

pixel size 150 µm ➞ 75 µm

detector area 6 x 6 cm² ➞ 7.68 x 7.68

cm²

format 400 x 400 ➞ 1024 x 1024

readout speed

readout speed

leakage currentActive Pixel Sensor » 1 preamp / pixel

» random accessible pixels

» no charge transfer

Specifications


The DePMOS ConceptThe DePMOS Concept

p-channel MOSFET integrated on high-ohmic, sideward depleted n-substrate

a potential minimum is formed by S/D potentials aided by a deep n implantation

electrons are collected in an internal gate close to the surface

the transistor current is modulated by charge collected in the

internal gate

the transistor can be switched on/off by an external (top) gate

An n+ clear contact surrounded by a clear gate is used to remove the charge from the internal gate


DePMOS PropertiesDePMOS Properties

DePMOS provides detection and amplification jointly

DePMOS is free of interconnection capacitances

The internal gate exists regardless of a current flowing in the DePMOS channel or not. Power consuption is minimized

Multiple non-desctructive readout is possible

matrix pixel 75 x 75 µm²

DEPFET• geometry W = 47 µm

L = 5 µm

dedicated technology• 2 polysilicon layers• 2 metal layers

leakage current level• 100 pA/cm²• 16 fA/pixel


APS – matrix organisationAPS – matrix organisation

• global contacts for drain (source) , back contact, substrate, …

• 1 active rowDEPFETs ON » readout & reset

• all other pixelsDEPFETs OFF » integration

• random accessible pixels» window mode, mixed mode

• sources connected column-wise

• gate, clear & cleargate connected row-wise


APS for the WFIAPS for the WFI

1024 x 1024 pixel7.68 x 7.68 cm²5 arcmin FOV

full frame modereadout time: ~ µsec / row

~ msec / framewindow mode

mixed mode

fast timing modee.g. 16 x 16 pixel

~ 100.000 cps» fast transients of

bright point sources

APS readout modes


CAMEX 64 G / K

• 64 channel low noise voltage amplifier• 64 channel 8-fold CDS filter• 64/1 analog multiplexer• source follower gain 3.7 µV/el.

Switcher II

• 64 channel control chip• 2 ports / channel • integrated sequencer• high voltage CMOS process (> 20 V p-p)• 50 MHz clock

DEPFET APS – prototypes for the DEPFET APS – prototypes for the XEUS WFIXEUS WFI


incomplete clear!

DEPFET – signal measurementDEPFET – signal measurement(time variant readout)(time variant readout)

measure signal levels

1. before clear -» signal2. after clear -» baseline3. calculate difference


DePMOS LinearityDePMOS Linearity

The drain current is measured

Laser intensity is calibrated with an X-ray source

Variation of the total charge by increasing number of the laser pulses per cycle

time

clear pulses

laser pulses

output measurements

drain current Integral non-linearity <0.4%

input range of 200 keV


Front end Configurations and Front end Configurations and Equivalent Input CapacitanceEquivalent Input Capacitance

source follower readout drain current readout

Charge/Voltage Gain 4-6 V/el. Charge/current gain (gQ) 200-350pA/el.

The signal and the noise sources are referred to the external gateDefinition of Equivalent Input Capacitance CEQQIN in the internal gate -> VS or IDVEG external gain signal that produces the same VS or IDCEQ=QIN/EG

QIN

QIN

VS IDVEG

VEG

CEQ=QIN/EG

CEQ=QIN/EG

Measured CEQ=35-40fF

gm=50SID=60A


Noise Spectral DensityNoise Spectral Density

ID 60A

gm 50S

√af=3V

√a=18nV/ √Hz

√(8/3)kT/gm= =14nV/ √Hz

noise corner 30kHz


Readout RequirementsReadout Requirements

electronics requirements:

multichannel ASIC

time-variant readout

variable readout speed

maximum readout speed 4S

total ENC <4 el. r.m.s.

dynamic input range: 40keV

Linearity <1%

DePMOS parameters

CEQ=40fFgm=50SgQ=200pA/el.V/c=4V/el.√a=14nV/ √Hz√af=3V

322

122 2 AbACaACaENC eqfeq


ASIC DevelopmentASIC Development

CAMEX Chip

In collaboration with Mr. W. Buttler

IMS 0.8m CMOS 5V

8-fold Multi-correlated Double Sampling

Source Follower readout

First Prototypes already tested -64 channels -no adjustable bandwidth

128 channel version with adjustable bandwidth under design

VELA Chip

In collaboration with Politecnico di Milano and INFN (Vlsi ELecrtonics for Astronomy)

AMS 0.35m CMOS 3.3V

Trapezoidal Weighting Function with Switched Current Technique

Source Follower readout

Drain Current readout

First submission June 2006

First prototypes in September 2006


MCDS-CAMEXMCDS-CAMEX

CAMEX 64 G / K

ac-coupled, low noise voltage amplifier64 channel parallel 8-fold CDSinternal PMOS current loadintegrated CDS sequencer

64/1 analog output serializerpower consumption ≤ 0.6 W row processing time ≥ 4 µsec128 channel version in design


Energy resolution of the matrixEnergy resolution of the matrix

shaper parameters:

A1/t=1.26x106 A2=1.27

cycle time: 16sPredicted ENC:3.4 el. r.m.s.32

21

22 2 AbACaACa

ENC eqfeq

Ceq=40fF

Measured ENC on noise peak:3.6 el. r.m.s.

with single pixel hits spectrum

133 eV @ 5.9 keV, T = -40 °C


MCDS Filtering optimizationMCDS Filtering optimization

A1/t A2 Cycle time [s] Predicted ENC Measured ENC

1.26x106 1.27 16 3.4 3.6

1.26x106 1.27 4 3.4

0.32x106 1.16 16 2.1

The used WF has quite high slope

The bandwidth is not optimized for the used speed

Optimizing the bandwidth an ENC of 2.1 el. is predicted

With the used bandwidth it should be possible to read-out the pixel in 4s

The bandwidth must be adjusted for every speed setting

A scalable trapezoidal WF would provide the near optimum filter for Series noise at every speed setting


Trapezoidal WF with SCTTrapezoidal WF with SCT

subtractionout

timeVout

timeVout

1° integration 2° integration

Current proportional to the input charge deposited into the DePMOS

Double integration of this current

Subtraction of the output of the two integrating stages after the first integration

The output is maximized when the input signal arrives between the two integration phases (Flat-top region)

timeVout

subtraction

current proportional to

the charge stored into the

pixel


Practical ImplementationPractical Implementation

1

2

3

1

2 3

the charge integrated in the first integration is transferred to a second stage (subtraction stage)

the first stage is resetted before the second integration

at the end of the second integration the output of the second stage gives the difference between the two integrated values

out

integrator stage subtraction stage


MCDS vs SCTMCDS vs SCT

MCDSBenefits:

The gain is almost independent on the timing

An offset of the input signal is not critical

Drawbacks:

The equivalent bandwidth depends on the timing (An adjustable low-pass filter is needed)

A real finite width WF is not feasible

Higher switching noise

SCTBenefits:

The equivalent bandwidth is independent from timing

A finite width filter function is feasible

Lower switching noise

Drawbacks:

An offset of the input signal is critical and can heavily deteriorate the dynamic range

The gain depends on the timing (an adjustable gain is needed)


Source Follower vs. Current readoutSource Follower vs. Current readoutBenefits:

The input signal is AC coupled. It is relatively easy to cope with: - non homogeneity of the DePMOS matrix - eventual Vth shifts

Drawbacks:The speed of the system is limited by the gm of the DePMOS and by the Capacitance of a matrix Source Line (30-40pF)

The voltage step at the source must be converted into a current (more suitable for MCDS)

Only a small signal amplification is possible because of the limited dynamic range

Benefits:The DePMOS drain current is directly used as the input signal of the integrator (pixel gain 200-300 pA/el)

all DePMOS terminals are at a fixed potential

The speed is no more limited by the Source line capacitance

Drawbacks:It is more complex to cope with the non homogeneity of the Matrix.

A current cancellation circuit is needed for each individual pixel

Source FollowerSource Follower

Current ReadoutCurrent Readout

V2I

gate

drain

Bias current source

gatedrain

source

Bias current

subtraction


Source Follower: V2ISource Follower: V2I

CC

RV2ICF

CIN

dominant pole

MBsecond pole

0V

0V 0V

IOUT

VinThe output current is not set by a feedback: mismatch can be important

Output current must be in the range of few mA to limit the size of the capacitances of the integration stage

Converted current in injected into the output mirror by a drain (MB drain)

The second pole of the loop gain is given by CF and 1/gmMB. The stability is independent from RV2I that can be high (tens of k).

MRCC

VI

IVF

IN

IN

OUT 11

2

M 1


V2I Noise analysisV2I Noise analysis

DePMOSDePMOSIN gm

KTe 1432

,

AMPnAMPIN ee ,,

2

22, 4

IN

FIVIRVIN CC

KTRe

222

,, MRCC

ieIN

FMIRnMIRIN

2

,114

DePMOSSRIN gmR

KTeS

RV2ICF

CIN

4kT/RS

(8/3)kTgm

M 1

en,AMP

in,MIR

4kT/RV2I

RS>1/gmDePMOS=20K -> RS>100K

en,AMP at the input. gmAMP 10mS W/L 800/.5

RV2I attenuated by (CF/CIN)2=100 RV2I=16K

in,MIR=(2/3)KTgmMIR multiplied by (RV2IM)2 dominant noise source


S.F. Noise spectral densityS.F. Noise spectral density

1 10 100 1000 10000 100000 1000000Frequency [Hz]

1E-027

1E-026

1E-025

1E-024

1E-023

1E-022

1E-021

Noi

se O

utpu

t Spe

ctra

l Den

sity

[A2 /

Hz]

Tota lO utput M irro rA m plifierR V2I 16K

1 10 100 1000 10000 100000 1000000Frequency [Hz]

1E-017

1E-016

1E-015

1E-014

1E-013

1E-012

Equ

ival

ent I

nput

Noi

se [V

2 /H

z]

Total input spectra l density

ElecronicseN=3e-17 V^2/Hz (5.5 nV/Hz)af=1.7e-13 V^2

DePMOSeN=3e-16 V^2/Hz (17 nV/Hz)eN=2e-16 V^2/Hz (14 nV/Hz)

[gm=50uS]af=9e-12 V^2


S.F. SimulationsS.F. Simulations

0 1E-005 2E-005 3E -005Tim e [s]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

Am

plitu

de

0 0.01 0.02 0.03 0.04Input Voltage [V ]

-1 .6

-1 .2

-0 .8

-0 .4

0

Out

put V

olta

ge [V

]

-0 .6

-0 .4

-0 .2

0

0.2

Inte

gral

Non

Lin

earit

y [%

]

Simulated weighting functions voltage step applied to the input of the V2IDePMOS rise-time is not considered

Input dynamic range: 0-40mVequivalent to 0-10000 el. with S.F. DePMOSOutput Range: 0-1.6 V

total width: 4s, 8s, 16s non linearity <0.4%


S.F. ENCS.F. ENC

Flat-top 500ns

DePMOS theoretical noise

gmDePMOS 50S

CS resistor 100K

DePMOS rise-time not considered


Line capacitanceLine capacitance

The Capacitance of one matrix column:

mainly given by the crossing of metal lines

crossing 10x10 mm2

COX=5.5 fF

4 crossing/pixel 500pixel/column

Crossing with Silicon and polysilicon

CGS and CCD give a minor contribution

column capacitance for the final APS 30-40pF


S.F. Rise TimeS.F. Rise Time

RISE TIME:

V2I: 15ns

DePMOS+V2I: 700ns

6.96E-006 7E-006 7.04E-006 7.08E -006t im e [s]

0

4E-007

8E-007

1.2E-006

V2I o

utput

curre

nt [A

]

6E-006 7E -006 8E-006 9E-006 1E -005t im e [s]

0

4E-007

8E-007

1.2E -006

V2I o

utpu

t cur

rent

[A]

RV2I

30pF

10-90%15ns

10-90%700ns

gm 100SrO=150K


S.F. WF distortionS.F. WF distortion

0 1E -005 2E -005 3E -005T im e [s]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

Am

plitu

de

0 4E-006 8E-006 1.2E -005Tim e [s]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

Am

plitu

de

integration time: 1.5sflat top:.5stotal width: 4s

integration time: 6sflat top:2stotal width: 14s


Drain Current readoutDrain Current readout

Bias current cancellation

Integrator Stage Subtraction stage

The DePMOS Drain signal current is sent directly to the integrator.An individual bias current cancellation circuit is needed


Current Readout: Current storageCurrent Readout: Current storage

electron signal in the internal gate

IBIAS+IS+n(t)

VH

IBIAS+IS+n(t)

The integrator is disconnected

The DePMOS current (bias+signal) is stored in a memory cell

At the end of this phase an unavoidable mismatch nO exists due to:

1) sampled noise when the switch opens

2) finite gain of the amplifier

VH+nH

IBIAS+IS+nO


Current Readout: double integrationCurrent Readout: double integration

IBIAS+IS+n(t)

VH+nH

IBIAS+IS+nO

n(t)-nO

electron signal in the internal gate

1° integration: The noise n(t) + offset nO is integrated

pixel is cleared

2° integration: the noise n(t) + offest + signal IS is integrated

from the subtraction of the two integrated quantities the offset nOis cancelled

internal gate empty

n(t)-nO-IS

noiseTInoiseTITnTndtIntndtntn INTSINTSINTOINTO

T

SO

T

OINTINT

00)()(


Weighting Function 4usWeighting Function 4us

Trapezoidal weighting functions low-pass at 25MHhz

width 3.5us


ENC evaluations: noise sourcesENC evaluations: noise sources

Conditions ENC DepMos ENC Rs ENC CAS ENC AMP1 ENC AMP2 ENC vela ENC tot ENC add

NOMINAL 3.26 1.65 2.10 0.72 0.79 2.88 4.35 1.09

•gm = 50uS•Cstray = 30pF•Rs = 100Kohm•gain = 200pA/el

Weighting functions width = 3.5us


ConclusionConclusionDePMOS characteristics match the requirements of XEUS Mission

A First Multi Channel MCDS Readout ASIC has already been tested with a 64x64 APS prototype. Obtained results are in agreement with theoretical predictions:

-3.6 el. r.m.s. measured -line readout speed of 16 s

To overcome the limitations of the available electronics two new circuits are under development

-Trapezoidal Weighting Function ●Source Follower ●Drain Readout

From simulations the most promising solution for fast timing is the current readout mode:

-Line readout speed 4s -around 4 el. r.m.s.

To further improve the performance of the system two ways are possible:

-increase the gain of the pixel (gm and gq) -increase the number of readout channel ( time available for each

measurement)


Radiation HardnessRadiation Hardness

(Laci ANDRICEK MPI HLL)

Documents

Multichannel Time-Variant Readout Electronics of DePMOS based APS for the XEUS Wide Field Imager