2004

Multichannel integrated circuits

for digital X-ray imaging

with energy windowing

Krzysztof Świentek

Department of Nuclear Electronics FPNT, AGH Kraków

K.Swientek@ftj.agh.edu.pl

2004

• Introduction – multichannel ASICs

• Noise in MOS transistors

• Crosstalk in mixed–mode integrated circuits

• Random matching

• RX64DTH – digital imaging using silicon detectors

• Measurements results – chip tutorial

• Summary

Content

2004

Introduction multichannel ASIC

Input signals - small amplitude (Qin = 1400 el) - stochastic character (amplitude, time)

SET OF SENSORS ( silicon strip detector)

MULTICHANNEL INTEGRATED CIRCUITS (analogue & digital blocks)

CROSSTALKdigital analogue

LIMITS: power & area

LOW LEVELOF NOISE

UNIFORMITY OFPARAMETERS

6.5

mm

RX64DTH

2004

Noise in MOS transistors

mth kTg

df

di

3

82

saturation

dsth kTg

df

di4

2

linear

Simulations (HSPICE)

NLEV=3 GDSNIOa

aaVV

L

WC

kT

df

diTGSox

th

1

1

3

8 22

BSIM3v3 (NIMOD=2) inveff

effth QL

kT

df

di2

2 4

1. Thermal noise of channel

Measurments – short channel effects (2-10x):

( velocity saturation, hot electrons)

2. Flicker noise

Simulations (HSPICE)

NLEV=2, 3 AFeffeff

m

ox

f

fLW

g

C

KF

df

di 122/1

Measurments – short channel effects

( hot electrons, RST noise)

BSIM3v3 (NIMOD=2)

2004

CROSSTALK

Transfer:– common supply lines: parasitic inductance and resistance (Vind=LdI/dt)– common substrate: (substrateepi, VT=f(VSB), gmb)

Effects for analogue blocks: switching noise, oscillation etc.

Minimisation:– reducing the noise generation,– increasing the immunity of analogue part,– isolation techniques.

GENERATION

TRANSFER EFFECT

DIGITALBLOCKS

ANALOGBLOCKS

SILICON SUBSTRATE

2004

RANDOM MATCHINGMATCHING - identically design devices have different parameters

P=P1-P2 (P/P)

222

2 DSWL

AP P

P

For MOS transistors: VT0 , ,

ox

BFs

ox

oxFMST0 C

Nq

C

QV

42

L

WCox

ox

Bs

C

Nq

2

CMOS 0.7m - (VT0) NMOS PMOS

W/L=2m/0.7m 9.72 mV 19.43 mV

W/L=1500m/1.5m 0.31 mV 0.63 mV

L

W

L

W

D

Num

ber

of c

ases

P/P [%]

2004

1. Matching bias condition

differences: VT, , R VDD VDD

IBIAS

IREF

M1 M2

R1 R2

IN1 IN2

OUT1 OUT2

M0 M1 M2

IDS1 IDS2

a) b)

R

RVVVV TGS

Tosr 2

4. Symmetry in layout– bias, temperature, orientation,

– common centroid geometry, unit cells,

– surrounding, metal coverage

TTGSDS

DS VVVI

I 2

2. Reduce sensitivity - proper configuration (Kv Ci/Cj)

3. Monte-Carlo analysis using HSPICE (matching data for given technology)

a)

b)

2004

data, control

Silicon strip detector Integrated circuit

PC computer

100 m

current pulses

X-rays

Signal 10x smaller

Stochastic

High Energy Physics

Key system issues:

– fully parallel signal processing for all channels.

– only binary information (yes/no) is extracted from each strip.

– data from each channel must be stored in the local buffer for the whole measurement period.

X-ray imaging using silicon strip detectors

2004

RX64DTH - fully integrated 64-channel chip (CMOS 0.8 m process)

RX64DTH consists of:– 64 front-end channels (preamplifier, shaper, two discriminators)– 128 pseudo-random counters (20-bit)– internal DACs: two 8-bit threshold setting and and three 5-bit for

bias– internal calibration circuit (square wave 1mV-30 mV)– control logic– I/O circuit (interface to external bus)

37006500 m2

2004

Single analogue channel

Key design issues:

– low noise (ENC 200 el. rms, sensor )

– low power (3-5 mW/channel)

– relatively fast shaping (Tp = 0.5 1s)

– uniformity from channel to channel (gain, offset, noise)

– immunity to switching noise

0

1

t

V

t

V

PreamplifierShaper

Discriminators

C2 C5

C3t

V

Tp

VT-HIGH

VT-LOW

0

2004

Preamplifier & shaper

piinvfp

inv TcFCbFT

CFaENC 2

2

fLWC

K

gkT

df

dv

ox

f

m

n 111

3

8

112

1

2

fedbiasDET

n

R

kT

R

kTqI

df

di 442

2

1. POWER

2. PEAKING TIME

3. SENSOR

4. PSRR, stability, matching.

LIMITATIONS

SENSOR:Cdet

Idet

Rbias

t

V

Tp

Minimum of noise (transistor dimensions, bias)

cdf

di

f

ba

df

dv

n

n

2

2

Hand calculation SimulationHSPICE

Other transistors

Measurements(bias, temp., Tp)

M1: 500/1 M5: 2/120 M4: 100/10 Id = 500 A

t

V

DAC currents – IFED– IFEDSH – ICAS

2004

ENC versus Peaking Time

ENC – total noise

ENCW – white voltage noise

ENCf – 1/f voltage noise

ENCi – white current noise

t

V

TpNoise types

TP [s]

Peaking time TP

• Optimal the lowest noise

• Fast Front-end increasing noise

2004

Discriminator – offsets, crosstalk

• AC coupling

• differential stage (CMRR)

• hysteresis

• power supply lines, guard rings

0

1

t

V

Tp

VT-HIGH

VT-LOW

0

1

2004

Pseudo-random counters

– 20 bit counters (large dynamic range of the image)

– small layout area (only 8 transistor per bit)

– 128 counters are grouped in the 8 blocks of 16 counters each (8 bit I/O bus to minimize the dead time)

2004

I/O circuits:

• LVDS standard (command, clock)

• 8-bit data bus (tristate),

• 3-bit address (up to 8 chips)

Functionality & testability

Calibration circuits: Qinj=CtVcal (500 el - 13000 el)

Internal DACs: threshold setting, gain, peaking time

2 x threshold 8-bit 3 x bias 5-bit1 x calibration 4-bit

6 dacs

Command code Action

000 SetGateStatus

001 ReadoutDestructive

010 ReadoutNonDestructive

011 CalibrationPulseLong

100 CalibrationPulseShort

101 CounterPulse

110 LoadDac

111 Unused code

2004

LAYOUT - floor plan, bias lines, pads

Isolation techniques – reduce inductance (separate bias line,pads),

– floor plan, bias lines

– keep “clean” substrate – LVDS

– RC filters

– guard rings, shielding

109

Floor plan– preamplifier & shaper

– discriminators

– counters & IOs

– digital outputs

– control logic

– calibration

– bias DACs

2

3

4

5

6

7

Digitalguard ring

Digitalground

Analogguard ring

Analogground

Middlering

11 14

1312

8

2004

0 50 100 150 200 250

0

5

10

15

20

Diff

eren

ce [L

SB

]

Diff

eren

ce [m

V]

Dac value [LSB]

0

1

2

3

4

5

6

Dif

fere

nce

[mV

]

Dif

fere

nce

[LS

B]

Dac value [LSB]Silicon:

3,67eV/el

Window – threshold DAC’s

0 50 100 150 200 250

0

100

200

300

400

500

600

700

800

Vol

tag

e [m

V]

Dac value [LSB]

-0,5

-0,4

-0,3

-0,2

-0,1

0,0

0,1

0,2

0,3

0,4

0,5

Err

or

[LS

B]

Dac value [LSB]

– two independent DACs

– common centroid matrix

– mixed matrices

– matching problem

– need software correction

Difference betweenDAC HIGH and LOW

7 LSB

2004

IFED

[LSB]

IFEDSH

[LSB]

ICAS

[LSB]

Temp. Gain

[V/el]

()

Offset

[mV]

()

ENC

[el. rms]

8 keV

ENC

[el. rms]

20 keV

ENC

[el. rms]

Cal 10

32 32 32 room 57.63

(0.34)

-9.23

(1.91)

248

(6.1)

232

(7.7)

232

(24)

32 32 32 room 56.79

(0.34)

-11.84

(1.91)

251

(6.1)

234

(8.5)

32 32 40 room 219

(24)

32 32 48 room 56.30

(0.37)

-11.50

(1.96)

233

(7.5)

217

(7.3)

213

(15)

32 32 56 room 203

(13)

32 32 56 25° 191

32 32 63 25° 185

32 32 63 20° 175

32 32 63 18° 163

Noise versus ICAS & Temp

Source Pu238 + Cu

Vdet = 130 V

Vdd = 4.0 V

Vddd = 4.0 V

Peltier element for temp.

ControledTemp.

VTH = 255VTL = scan

VTH = scanVTL = 255

2004

IFED

[LSB]

IFEDSH

[LSB]

ICAS

[LSB]

Temp. Gain

[V/el]

()

Offset

[mV]

()

ENC

[el. rms]

8 keV

ENC

[el. rms]

20 keV

24 32 63 20° 54.86

(0.39)

-17.62

(1.33)

198.9

(5.1)

205.9

(16.7)

32 32 63 20° 54.85

(0.44)

-17.85

(1.09)

203.1

(6.6)

201.5

(8.22)

40 32 63 20° 54.86

(0.45)

-17.55

(1.26)

220.7

(8.5)

213.7

(9.47)

48 32 63 20° 54.84

(0.49)

-16.96

(1.30)

238.2

(9.2)

228.6

(9.46)

Noise versus IFED

– gain & offset const

– window is 5 LSB

– Peltier element

pin-holes in detector leakeage current

fastnoiseincreasing }

dead channels becauseout of operating point

rescueincrease IFED but ...

2004

Simulation: TP & Gain as a function of IFEDSH

shaper output

TP

Imp

uls

e h

eigh

t

• TP = 0.7 – 1 s• Impulse fall ends 4 s 200 kHz

2004

IFED

[LSB]

IFEDSH

[LSB]

ICAS

[LSB]

Temp. Gain

[V/el]

()

Offset

[mV]

()

ENC

[el. rms]

20 keV

32 16 63 20° 80.54

(0.57)

-0.8

(0.9)

177.5

(4.91)

32 24 63 20° 63.74

(0.52)

-11.68

(1.11)

197.6

(8.69)

32 32 63 20° 54.85

(0.44)

-17.85

(1.09)

201.5

(8.22)

32 40 63 20° 50.2

(0.36)

-20.59

(1.24)

206.5

(9.42)

32 48 63 20° 47.64

(0.35)

-21.67

(1.39)

209.9

(8.92)

32 63 63 20° 45.52

(0.32)

-22.82

(1.22)

210.7

(9.36)

Gain, Offset & Noise versus IFEDSH

– window is 5 LSB

– Peltier element

min (fast)

max (slow)

TP

peakingtime

2004

1. Multichannel mix-mode ASIC :— critical parameters connected together— looking for a golden solution

2. Software corrections : — DACs problem — differences between the chips

3. Noise controling :IFED – better detector lower noiseICAS – the highier the beter (cooling ?) IFEDSH – high gain gives low noise and speed

4. To do – measurements— speed— uniformity in 6-chip module

Summary