Multi-path filter design

998 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Tunable High-Q N-Path Band-Pass Filters:Modeling and Verification

Amir Ghaffari, Student Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE,Michiel C. M. Soer, Student Member, IEEE, and Bram Nauta, Fellow, IEEE

Abstract—A differential single-port switched-RC N-path filterwith band-pass characteristic is proposed. The switching fre-quency defines the center frequency, while the RC-time and dutycycle of the clock define the bandwidth. This allows for high-Qhighly tunable filters which can for instance be useful for cognitiveradio. Using a linear periodically time-variant (LPTV) model,exact expressions for the filter transfer function are derived. Thebehavior of the circuit including non-idealities such as maximumrejection, spectral aliasing, noise and effects due to mismatch inthe paths is modeled and verified via measurements. A simpleRLC equivalent circuit is provided, modeling bandwidth, qualityfactor and insertion loss of the filter. A 4-path architecture isrealized in 65 nm CMOS. An off-chip transformer acts as a balun,improves filter-Q and realizes impedance matching. The differen-tial architecture reduces clock-leakage and suppresses selectivityaround even harmonics of the clock. The filter has a constant3 dB bandwidth of 35 MHz and can be tuned from 100 MHz

up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm,dBm and the noise figure is 3–5 dB, while the power

dissipation increases from 2 mW to 16 mW (only clocking power).

Index Terms—Band-pass filter, CMOS, cognitive radio, commu-tated capacitors, frequency translated filter, high linearity, high-Q,inductorless filter, linear periodically time variant circuit, LPTV,N-path filter, software-defined radio, tunable filter.

I. INTRODUCTION

I N software-defined radio (SDR) and cognitive radio trans-ceivers, programmability is not only desired in the digital

back-end, but also for analog front-end functions. A major chal-lenge for such radios is the realization of an RF band-pass filter,with tunable center frequency over a wide frequency span. Forcognitive radio applications in the TV-bands, relatively few andrather narrow spectral holes may exist between strong incum-bent TV transmitter signals [1]. To reject the strong signals inorder to avoid blocking of the receiver, such a filter should havevery high linearity, high compression point but also very highQ (e.g. for 10 MHz bandwidth around 500 MHz).Although off-chip passive filters provide these properties, in-

tegrated CMOS alternatives are highly desired for reasons of

Manuscript received September 02, 2010; revised January 14, 2011; acceptedJanuary 21, 2011. Date of publication April 05, 2011; date of current versionApril 22, 2011. This paper was approved by Guest Editor Yuhua Cheng. Thiswork was supported by the Dutch Technology Foundation STW, Applied Sci-ence Division of NWO and the Technology Program of the Ministry of Eco-nomic Affairs (project 08081).The authors are with the University of Twente, CTIT Institute, IC Design

Group, 7500 AE Enschede, The Netherlands (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2011.2117010

Fig. 1. Architecture of an N-path filter [5] (p and q are the mixing functionsand T is the period of the mixing frequency).

size and cost. On-chip LC filters can be implemented but withlimited tuning range and low Q, especially below 1 GHz wherethe achievable Q of on-chip inductors is poor and coils take largearea. Q-enhanced techniques [2]–[4] can improve filter qualityfactor but degrade linearity and noise. Thus alternative tunablefilters without inductors are highly wanted.Inductor-less tunable filters based on periodically time

variant networks have been addressed in literature underdifferent names such as N-path filters, sampled data filters,commutated capacitors, etc. [5]–[11]. Discrete-time switchedcapacitor N-path filters are probably best known [8], but herewe focus on their continuous-time predecessors. Fig. 1 showsa block diagram of an N-path filter composed of identicallinear time-invariant (LTI) networks with impulse response

and 2 frequency mixers (or modulators), driven bytime/phase shifted versions of the clock and . The timeshift between two successive paths is , where is the pe-riod of the mixer clock. If the LTI networks exhibit a low-passcharacteristic around DC, the mixing results in a band-passaround the mixing frequency. Simply put, the input signal isdown-converted to baseband, filtered by the LTI network andthen up-converted again to the original band of . The centerfrequency is determined by the mixing frequency, insensitiveto filter component values. A high mixing frequency combinedwith a narrow low-pass filter bandwidth allows for a very highfilter Q.While time-continuous N-path filters have been proposed for

kHz operating frequencies in the 1960s [6], they seem to havebeen largely forgotten until recently. CMOS technology now al-lows N-path filters to work at TV-band RF frequencies [9], [10]and even above 1 GHz [11]. In [9] an 8-path single-ended struc-ture is used, and in [10] we proposed a differential 4-path filter

0018-9200/$26.00 © 2011 IEEE

GHAFFARI et al.: TUNABLE HIGH-Q N-PATH BAND-PASS FILTERS: MODELING AND VERIFICATION 999

Fig. 2. (a) Switched-RC N-path filter. (b) Single port, single ended N-pathfilter. (c) Multiphase clocking. (d) Typical (in-band) input and output signal.

combined with a broadband off-chip transformer. In [11] thedifferential 4-path filters are applied in a quad-band SAW-lessreceiver. This paper aims to model and verify N-path filter per-formance. Using linear periodically time-variant (LPTV) anal-ysis, exact expressions for the frequency response of differentialN-path filters are derived. In [7] state-space analysis was used toderive the steady state and transient response for a single-endedN-path filter, which is however not directly applicable to our dif-ferential architecture. We will derive one set of equations thatcharacterizes filtering but also possible imperfections like har-monic folding, noise and the effects of the clock phase imbal-ance and mismatch. Moreover, an equivalent RLC tank circuitwill be derived to approximate N-path filter behavior around thecenter frequency. Finally, we will verify the model via extendedexperimental results compared to [10].In Section II, we will derive the differential N-path filter

architecture starting from Fig. 1 and then analyze its transferfunction in Section III. Section IV presents basic characteristicsof the differential N-path filter. Its chip implementation isdiscussed in Section V and Section VI covers the measurementand verification versus the model.

II. N-PATH FILTER

We will now derive the differential N-path filter fromFig. 1, where we aim for a high-linearity implementation usingMOS-switches as passive mixers, and RC low-pass filters [seeFig. 2(a)]. Furthermore we will try to develop some intuitiveunderstanding of the filter behavior.

A. Single Ended Switched RC N-Path Filter

Fig. 2(c) shows a multi-phase clocking scheme for theswitches with non-overlapping on-times. Thus no charge ex-change between capacitors can occur. For this reason and sincea resistor is a memory-less element, it can be shared by allpaths and shifted in front of them [Fig. 2(b)]. Moreover, if theclocks for the first and second set of switches are identical,the first set can also implement the function of the second set.

becomes then available between the shared resistor and

Fig. 3. Single port differential 4-path filter.

switches. Fig. 2(b) shows the resulting single-port single-endedN-path filter ( is both input and output port). If we woulduse the capacitor voltages as outputs, the circuit behaves as ahighly linear multiphase passive mixer [12], [13].To intuitively understand the filter behavior of Fig. 2(b) it is

useful to model it as a two-step process: 1) the input signal expe-riences down-conversion and low-pass filtering passing throughthe switches to the capacitors; 2) the same switches up-convertthe filtered capacitor voltages to the output node. Another wayto understand the filtering is to realize that at any moment oneand only one capacitor is connected to the output node. If weassume that the time constant , the output voltagewill be the average of the input voltage over the time that thecapacitor “looks at ”. If the frequency of is equal to theswitching frequency, a particular capacitor will periodically ob-serve the same part of the input waveform during every period.As each capacitor sees another part, the result is a staircase ap-proximation of , see Fig. 2(d) (4-path example). In fact, thecapacitors experience a steady DC voltage and, in first order ap-proximation, conduct no current. If the input frequency deviatesfrom the clock frequency the signal portion seen by a capacitorwill “travel over the period” and the capacitors experience anAC voltage (with ). Thus the capacitors conduct currentwhile switches are on and the average voltages on the capacitorsbecomes closer to zero. Consequently signals at input frequen-cies below or above the switching frequency will be suppressedwith an amount depending on the offset from the switching fre-quency, on-time of the switch and RC time.

B. Differential Switched RC N-Path Filter

If we repeat the analysis for input signals around the har-monics of the clock frequency, we also find non-zero averagevalues. This fits to the comb-like characteristic of N-path fil-ters [5], i.e., its repetitive selectivity around harmonics of theswitching frequency. The differential architecture of Fig. 3 aimsto cancel the even harmonic responses. Each path is differen-tial-in and differential-out, but contains one grounded capac-itor connected to two anti-phase driven switches. A 4-phase25%-duty-cycle clock provides all required clocks (see Fig. 3).Now, for input signals around the even harmonics of the clock


frequency, no net charge is stored on the capacitors in steadystate and no up-converted signal appears at the output.

III. ANALYSIS

To model the behavior of the N-path filter quantitatively, wewill now apply LPTV state space analysis [14], [15] to derivethe exact shape of the transfer function of a differential N-pathfilter.

A. State Space Analysis of LPTV Circuits

For an LPTV network which is periodic with the frequency, the output spectrum is related to the input spectrum

as [16]

(1)

where represents the shifted version of the inputspectrum to account for frequency translation (mixing), while

describes the spectral shaping (filtering) propertiesof an LPTV network. To simplify analysis, we make twoassumptions: 1) the switches are ideal, i.e., their off-impedanceis infinite and on-impedance is zero; 2) switching occursinstantaneously.The time interval is divided intoportions ( is the number of the states) and each portion

identified by can be represented as, and (see Fig. 4). During each

interval there is no change in the state of the switches and thenetwork turns to an LTI system. The state equations for intervalcan be written as

(2)

where is the input vector, the state vector andthe output vector. If we define and to be equal to theinput and output respectively during the th interval,and zero otherwise, the state equations in (2) can be reformu-lated as [14]

(3)

In (3) the Dirac’s delta function has been used to add theeffects of the initial conditions to the equations at the beginningof an interval, while subtracting it at the interval’s end. Thenthe output is the sum of all responses from states in thesystem:

(4)

Since we are interested in the spectrum of the output of thesystem we need to take the Fourier transform from (4). It canbe shown [15] that if we apply a complex exponential

as input, the output state at discrete moments can be

Fig. 4. Time intervals for the state space analysis.

calculated by reforming the state equations to a set of differenceequations at the switching moments. Consequently the relationbetween the input and the output will be of the form

(5)The input spectrum can be represented as a summation of

sinusoidal signals. As a result the infinite summation in (3) takesthe form

(6)

By applying (6) to (3) and taking the Fourier transform, thespectrum of the state vector becomes

(7)

where is the length of the th time interval (see Fig. 4) andis an identity matrix.

B. Analysis of the Differential Single Port N-Path Filter

We will apply the analysis procedure described in the pre-vious part to derive the output spectrum of the differentialN-path filter. Although Fig. 3 illustrates a 4-path architecture,analysis is done for a general differential N-path system. At anymoment two capacitors are connected to the differential outputthrough two switches, which are activated with the same phaseof the input clock. The resulting time-domain output signalis the superposition of the signals from different capacitors


Fig. 5. Differential single path circuit and the clock phases for the switches.

at different moments without any overlap. Since there is nointeraction between capacitor voltages, the analysis of thesimple network illustrated in Fig. 5 suffices, where just onepath is illustrated with its timing diagram for the switches. Thestate equations for this circuit are

(8)

where is the voltage on the capacitor in Fig. 5. If one of thetwo switches is on, the output voltage will track the voltage onthe capacitor. When switches are off, the voltage on the capac-itor will be held, but will not affect the output. Hence, the outputspectrum contribution will be calculated in the track-mode. Asthe capacitor will deliver either ( on) or (on), this contribution is . As a result, andin (7) should be defined from either the first or the third equationin (8), depending on which switch is on. As a result, accordingto (8) for and :

, where is defined as the3 dB bandwidth of a single low-pass filter with resistor andcapacitor (see Fig. 5).Applying as the input in the state equations

in (8) and also assuming that and , we can findin (6) for as

(9)

Assuming the output voltage is following the voltage on ca-pacitor during interval , based on (8) the Fourier trans-form of the output can be found as

(10)

The output spectrum is the superposition of contributions forall paths, and taking into account the phase shifts betweenthe contributions the complete output spectrum can be found as

(11)

where for each path (see Fig. 5). Accordingto (11) is composed of components generated by thepaths. We will now derive filter characteristics from (11).

IV. CHARACTERISTICS OF A DIFFERENTIAL N-PATH FILTER

A. Filtering and Harmonic Folding Back Effects

For an ideal N-path filter we assume, where is the duty cycle of the multiphase

clock. Analysis of (11) shows that is undefined for, but we can take the limit of when approaches con-tinuously to zero to find . Moreover, in deriving (11) weassumed (non-overlapped switching). When

, there are periodic time intervals that all the switches areoff and the output signal is tracking the input signal (instead ofthe voltages on the capacitors). The output spectrum contribu-tion generated due to this fact is not considered in (11). In orderto include this effect in , the factor should be


Fig. 6. Theoretical and simulated curve for at MHz for, and pF.

added to the part which is derived from (11) by taking the limitfor to zero. The final result becomes

(12)

Although (12) includes the clock duty cycle effectin the output spectrum, in an ideal N-path filter:. In (12) represents the desired filtering charac-

teristic without any frequency translation. for a 4-pathfilter with the values of , , pF and

MHz is shown in Fig. 6. In Fig. 6 the comparisonbetween the theoretical transfer function from (12) and the sim-ulated results applying Spectre RF PSS-PAC is shown, which fitcompletely on top of each other. Fig. 6 shows band-pass filteringaround the switching frequency, for this case with 1.8 dB inser-tion loss. However, there are also response peaks around oddharmonics of the switching frequency, related to repetitive polesin the denominator of (12). Thanks to the differential architec-ture, peaking around even harmonics does not occur. From (11)we see that for whereand is zero for other values of . Thus the filter not only showsa comb-filter characteristic, but also “folding back” from inputfrequencies around to the desired band around. The strongest terms which result in down-conversion in a

4-path filter are shown in Fig. 7. For instance, rendersnon-zero , modeling folding from and to(both with frequency shift ). For an 8-path architecture thefirst folding back will happen from . In general, increasingthe number of paths will increase the distance between andthe first folded component around .Often, a low-pass pre-filter will be needed in front of the

N-path filter to sufficiently suppress harmonic folding. For radioreceiver applications, the pre-filter requirements depend onspecific blocker scenarios. In fact the folded back power fromblockers to the desired band and the amount of degradation in

Fig. 7. around the switching frequency for a 4-path filter. This deter-mines the folding back from odd harmonics of the switching frequency

MHz .

Fig. 8. N-path filter with switch resistance.

the sensitivity of the receiver must be acceptable. Note that theimplementation of a low-pass pre-filter is likely to be feasible,because it does not need to be tunable. In the proposed differ-ential N-path filter, second harmonic folding is cancelled whichrelaxes the pre-filter transition band. Moreover, increasingcan relax the pre-filter transition band requirements.

B. The Effect of the Switch Resistance

In order to include the effect of the switch resistance in ouranalysis, we consider the model shown in Fig. 8. Since in thearchitecture illustrated in Fig. 3, at any moment just two of theswitches are on, the model in Fig. 8 includes two switch resis-tances in front of an ideal N-path filter with zero switch resis-tances. Employing (11) with , thetransfer function from to can be easily found. Using su-perposition of the and contributions we find

(13)

If is set to zero in (13) it returns to the previous formof (11). Switch resistance can have strong impact on the max-imum achievable rejection in N-path filters. To understand this,consider the frequency transfer function including the switch re-sistance effect for :

(14)


Fig. 9. Switch resistance effect on the maximum rejection of a 4-path filter( , pF, MHz, ).

According to (14), close to the switching frequency the ef-fect of the switch resistance is not significant ( term is closeto 1 and dominates). But for frequencies further away from theswitching frequency, where is close to zero, the firstterm often dominates and the output can be approximated as

. Thus, the maximumfilter rejection is limited by the switch resistance, as exemplifiedby Fig. 9 for the same 4-path filter used for Fig. 6 but now with

added. As a conclusion, in order to increase themaximum rejection of the filter, the switch resistance should bevery small with respect to the source resistance .

C. Harmonic Selectivity in an N-Path Filter

In this section we will discuss the selectivity in the har-monics of the switching frequency both in an analytical andintuitive way. Around filter response peaks the filter becomeshigh-ohmic. To quantify the selectivity around the harmonicsof the switching frequency, we approximate (12) for ,

for odd , resulting in

(15)where and is the duty cycle ofeach clock phase. As an example, if we substitute and

and , then , i.e., 1.8 dB in-sertion loss in the pass-band, which fits to Fig. 6. According to(15) increasing N will reduce the insertion loss. As an example,for an 8-path system the insertion loss becomes 0.4 dB. Equa-tion (12) was used to produce Fig. 10(a), comparing a 4-pathand 8-path filter with a fixed total amount of capacitance. Thisfigure suggests that the filter attenuation around harmonics isreduced by increasing the number of paths. To understand thisfact better, notice that the achievable rejection of the filter atthe odd harmonics of the switching frequency can be approxi-mated by (15). Assuming ideal clocking (substitutein (15)) the suppression at the harmonics is solely defined bythe number of paths. Fig. 10(b) shows the calculated harmonicrejection applying (15). In most cases indeed harmonic suppres-sion decreases by increasing the number of paths, but there area few exceptions [see Fig. 10(b)].To get some intuitive insight how harmonic rejection and har-

monic folding occurs, we added Fig. 10(c). It shows the timesignals for a sine-wave with a frequency of applied to the4-path filter of Fig. 2(b). Each of the capacitors now

Fig. 10. (a) Harmonic selectivity comparing the 4-path filter of Fig. 6 with an8-path filter with the same total capacitance. (b) Odd harmonic selectivity fordifferent number of paths and (eqn.(15)). (c) Waveforms intuitivelyillustrating 3rd harmonic selectivity and 3rd harmonic folding (down-mixingfrom to ) for a 4-path filter.

“sees” the sine-wave for 3/4 of a period. The output after in-tegration is a square wave with frequency , which containsboth the fundamental and the third harmonic, illustrating thatboth harmonic selectivity and harmonic folding occurs. Similarsignals can be drawn for a larger number of paths. Doing so,we can observe that for more paths, i.e., greater number of timeslots in Fig. 10(c), there is less time to cancel the positive partsof a signal with the negative parts during the integration takingplace on each individual capacitor . Larger leads toless attenuation of harmonics at the output [Fig. 10(b)], but lessfolding back since the staircase approximation in Fig. 2(d) re-sembles the actual input signal better.

D. Input Impedance of an N-Path Filter

Now by applying (14) and (15) we can derive simple expres-sions for the input impedance of the N-path filter in Fig. 8 atthe switching frequency, its odd harmonics and for frequenciesfar away from the peak points in Fig. 9. It will be shown thatthese impedances are all resistive. The effect of the switch re-sistance can easily be taken into account by substituting (15) in(14) to find an approximate equation for . To findthe equivalent input impedance of the N-path systemwe define . As aresult, . For a4-path system ( , ) we find

(16)

Equation (16) predicts that at the switching frequency theinput impedance of the N-path system is resistive, which is sim-ilar to a tank circuit at the resonance frequency. For , (16)corresponds to the energy conservation based derivation in [12],but (16) can also be used for other values of . For frequenciesfar away from the switching frequency and its odd harmonics,using (14) we again find purely resistive input impedance:

(17)


Fig. 11. (a) Effects of increasing and decreasing of the clock duty cycle. (b) Insertion loss changes due to the duty cycle reduction.

For an ideal system (17) reduces to . In-tuitively this can be understood because the capacitors act likea short circuit for .We can conclude that for the switching frequency, the N-path

filter has high impedance (16) and for frequencies far away fromthe switching frequency, it renders small impedance (17). Later,in Section IV-F, we will apply derivations in (15)–(17) to derivea simple RLCmodel for the N-path filter. In Section V, (16) alsowill be applied to define the required conditions for input powermatching.

E. The Effect of the Duty Cycle of the Clock

When the duty cycle of the multiphase clock is smallerthan , all switches are off periodically for some time and theoutput signal of the N-path filter simply tracks the (unloaded)input signal. Applying (12) for a 4-path architecture, the filtershape for a duty cycle is illustrated in Fig. 11(a).Comparing to the ideal case , notice from (17)that reducing the duty cycle from results in higher inputimpedance for the frequencies far away from the switching fre-quency and its odd harmonics, which translates to less rejection.On the other hand the reduced duty cycle decreases pass-bandinsertion loss, as predicted by (12) and also (15) [see Fig. 11(b)].Note that the degradation of the maximum rejection is muchmore than the reduction in the pass-band loss.As mentioned in Section III, our analysis does not include the

case for which two switches can be on at the sametime, resulting in undesired charge sharing between capacitors.Fig. 11(a) also shows simulation results for two overlappingclock cases: 1) and , resulting in com-plete destruction of the filter shape; 2) , ,where the switch resistance still limits the charge sharing be-tween capacitors and some filtering remains, but with large in-sertion loss.

F. RLC Model, Bandwidth and Quality Factor

Around , the filter transfer function as shown inFig. 6 resembles that of a high-Q tank circuit. Now we wantto quantify this similarity and find an equivalent RLC modelthat predicts the quality factor and bandwidth for the N-pathfilter. Although (11) encompasses a repetitive pattern of polesand zeros, we are mostly interested in poles which occur closeto the switching frequency. Equating the denominator ofin (12) to zero tofind the poles, we find ,

Fig. 12. Equivalent RLC circuit model for the N-path filter.

, indeed odd harmonics of . In order to makea narrowband approximation, we just consider the poles closeto the switching frequency, which areand set these poles equal to the poles of the transfer function ofFig. 12, which is shown in (18):

(18)

As a result, and in the RLC model can be found as

(19a)

(19b)

The value of in the RLC model is already derived in (16)for a 4-path system with for the switching frequency.Note that and are independent of , in contrast to .However, the term in the denominator of (19b) can benon-negligible compared with . Thus, the maximum in thetransfer function can be slightly shifted to higher frequencies,which also fits with the N-path filter response. For thisshift is negligible. To verify the validity of the RLCmodel, con-sider a 4-path filter with and pF. Employing(16) and (19), we find pF, nH, and

. The comparison between the RLC model and theexact transfer function in Fig. 13 shows a nearly perfect matcharound the switching frequency. Applying the RLC model, wecan find the bandwidth as .Intuitively this can be understood considering that in Fig. 5 theresistor value charging the capacitor is and the capacitorsees this resistor value for a fraction of the period, i.e., the“effective resistor” is . Therefore, the 3 dB bandwidthbecomes times the low-pass filter bandwidth defined by .Finally, for a 4-path system and

. Thus, we see that the bandwidth not only depends on the


Fig. 13. Comparison of the transfer of the RLCmodel with the full N-path filtermodel (11).

RC value for each path, but also on the duty cycle of the clock.Comparing a 4-path and an 8-path filterusing identical capacitors in each path, the 8-path filter has halfthe bandwidth of the 4-path filter. If we keep the total amountof capacitance equal, then the bandwidth will not differ by in-creasing the number of paths [see Fig. 10(a)]. In this paper, weexploit a 1:2 transformer to increase the source resistance, asseen by the filter, and hence reduce the bandwidth and increasethe Q of the filter. A further increase in capacitor area can pro-vide even lower bandwidth and higher Q.Notice that as we discussed intuitively in Section II, the RC

in each path of an N-path filter is performing integration on theinput signal, when the corresponding switch is on. In contrastto a sampling system, there is no need for the voltage to settleduring one on-time of the switch. Thus, the choice of the capac-itor size is independent of the switching frequency and can besolely determined based on the desired bandwidth.

G. Imbalance Multiphase Clocking and Mismatch in the Paths

Next, consider what happens if there is mismatch betweenpaths or if clocking signals deviate from the ideal situation.With mismatch, we can expect that even-order terms are nolonger perfectly cancelled and extra frequency componentsshow up. As an example, , which was 0 for an idealN-path system, can be non-zero around the desired band.According to (11), this renders an image response (e.g., con-version from to ) and alsofolding back from signals around to . Aswe use large valued integrated capacitors (10 s of pF), goodmatching is possible and therefore we focus on quantifyingclock phase errors. We model clock pulse width variationsin the multiphase clocks and apply (11), considering unequalpulse widths. Fig. 14 shows the calculated image suppressionand folding back from . According to Fig. 14, one degreeof phase error will result in 42 dB of image rejection and 45 dBsuppression of second harmonic folding.

H. Noise

Most output noise power is due to the thermal noise of thesource and switch resistances, where noise folding from aroundharmonics of should be incorporated. As the switches donot carry DC current, the flicker noise of the switches can beneglected. At any moment two switches are in the on-state (seeFig. 3) and since noise contributions of the switches are not

Fig. 14. Image and second harmonic rejection with phase error in the drivingclock phases.

Fig. 15. The model for noise calculation. (a) Source noise. (b) Switch resis-tance noise.

correlated, we can use the model in Fig. 15, similar to Fig. 8. Asthe input impedance around according to (16) is significantlylarger than , the noise voltage source has a much highertransfer to than has, which is beneficial for thenoise figure.Relation (13) between the input and output spectrum of

an LPTV system can also be applied to random signals. ForFig. 15(a), we can find , the thermal noise due to :

(20)

The first term accounts for the noise power, which appearsat the output without any frequency translation, and the secondpart accounts for noise folding, where is thefrequency-shifted version of the noise power generated by .Note that in (20) can be calculated by applying

in (11).To calculate the output noise power due to switch resis-

tance, we consider Fig. 15(b). Similar to the previous case,the frequency transfer from to can be calculatedfrom (11) with . Then, by applyingthe procedure described in Section IV-B, the transfer functionfrom to can be derived. Finally, for the circuit inFig. 15(b), we find

(21)


Fig. 16. Micrograph of the 65 nm CMOS chip.

Again, the first part inside the second parenthesis in (21)corresponds to the noise power without frequency translation.Since is close to 1 around the switching frequency foran N-path filter (e.g., 0.81 for a 4-path architecture), the con-tribution of the first part is very small. The second part in (21)is the noise folding term and turns out to be almost negligible.For example, in a 4-path architecture with and

, the noise at the output due to switch resistance isapproximately 2% of the total noise at the output. Finally, thenoise factor can be calculated as . For a4-path differential filter with , , the calcu-lated noise figure from (20) and (21) is 0.92 dB, which is mainlycaused by the noise folding of noise coming from the source re-sistance .

V. IMPLEMENTATION OF A 4-PATH DIFFERENTIAL FILTER

A 4-path differential single-port filter is realized in 65 nmstandard CMOS technology (see Fig. 16). The block diagramof the filter is illustrated in Fig. 17. Capacitors of 66 pF arerealized with NMOS transistors, at 720 mV gate bias, to achievelarge capacitance density with good linearity. NMOS switchesof are driven by a 25% duty cycle 4-phaseclock. The clock phases are capacitively coupled to the gates ofthe switches, which are biased at 950 mVDC voltage to providefull 1.2 V swing on the gate-source nodes of the switches. Thisswing insures the maximum achievable linearity for switcheswith fixed sizes. Increasing switch size will improve linearityand decrease the switch resistance. However, larger switch sizealso means larger parasitic capacitors, affecting the frequencyrange and clock leakage and also requiring more clock power todrive the switches.An off-chip wideband (50–1000 MHz, Mini-Circuits JTX-4-

10T) RF transformer serves as a balun for single-to-differentialconversion. Moreover, it increases the impedance level seen bythe switched-capacitor circuit, increasing filter Q without a sig-nificant degradation in its noise. The architecture in Fig. 17 alsohas an extra resistor to provide input power matching to50 . To find the required conditions for power matching, wewill use (16). Neglecting switch resistance, “lookinginto the IC” can be written as , where

is the driving impedance seen by the IC (see Fig. 17). Thenthe required value for to provide matching can be found as

. For the value forbecomes 322 . In practice, the insertion loss of the transformeris non-negligible and in our case it was actually sufficient to im-plement . In the general case, an equivalent total resistance

according to the derived value is needed for good .

Fig. 17. Filter architecture including a balun and buffer amplifier formeasurements.

Fig. 18. Multiphase clock generator.

The simplified block diagram of the quadrature clock gener-ator with low phase error [17] is shown in Fig. 18. A masterclock (CLK) at 4 times the switching frequency is applied fromoff-chip. A flip-flop based divider divides the input clock byfour, while an AND gate between node A and B generates a 25%clock. Finally, a shift register implemented with transmissiongate flip-flops produces 4-phase clocks to drive the switches.These clocks are then capacitively coupled to the gates of theswitches after buffering.

VI. MEASUREMENT RESULTS AND COMPARISON

An external differential high input impedance buffer ampli-fier is added in the circuit of Fig. 17 to be able to measure with50 equipment without loading the output of the filter. Weutilized Agilent ATF-54143 HEMT transistors to make an am-plifier with high linearity and low noise in order to have min-imum influence on the measurement results. Measurement re-sults show that the tunable filter in Fig. 17 works from 100MHzup to at least 1 GHz. Fig. 19 shows measurement results andcompares them to a simulation employing an ideal transformerand for MHz, while also includinga bond-wire inductance estimate. The buffer amplifier gain isde-embedded in all experiments, but the transformer effects areincluded. Considering the fact that in Fig. 17 is 123 ,


Fig. 19. Frequency transfer and at MHz.

, and NMOS capacitors have the value of approxi-mately 66 pF (simulated value), then according to Section IV-Ethe bandwidth is calculated as 36 MHz. The measured value forthe bandwidth is 35 MHz, which renders a Q ranging from 3 to29 for ranging between 0.1 and 1 GHz.As derived in Section IV-F the bandwidth of an N-path filter

for a given is a function of the RC-time of the filter. Anyvariation of and will hence result in filter bandwidth de-viations from the designed value. While changes of are dueto PVT variations, the effective resistance seen by the filterfor radio receiver application depends on the effective antennaimpedance, which may show significant deviations. As a result,a capacitor tuning scheme might be needed to keep the band-width fixed over RC variations. The extra switches needed toadd or remove capacitors can have larger size than the mainclocked switches, since the capacitive switch parasitics can beabsorbed in the wanted capacitance. Moreover, these switcheswill be static (that is, they do not consume dynamic power).Thus, themaximum rejection of the filter will hardly be affected,nor its noise or linearity.Close to the input is matched to 50 for a narrow band,

simplifying the design of a preceding band-pass or low-passfilter to mitigate the harmonic folding problem. The maximumfilter rejection is limited by non-zero switch resistance andimpedance . Applying (17) and considering a 4-patharchitecture and for frequencies far awayfrom the switching frequency, input impedance can beapproximated as two times the switch resistance . Themaximum rejection, , can then be estimated as

(22)

Thus, increasing by applying the transformer not onlyresults in less bandwidth and hence an increased Q, but alsolarger maximum achievable filter rejection. More attenuationcan also be achieved using wider switches at the cost of clockdriver power. In the implemented architecture, ,

, resulting in dB. Measurement re-sults render 16 dB (Fig. 19). The difference is likely due tothe effect of the non-zero rise and fall times of the clock, re-ducing in an effective duty cycle below 25%. According to (17),

Fig. 20. Folding back from harmonics at MHz (measured and cal-culated with (11); even harmonics ideally are fully cancelled).

Fig. 21. Measured in-band image rejection for –1 GHz.

this results in larger input impedance and hence a smaller max-imum rejection. Fig. 19 also illustrates the frequency selectivityaround odd harmonics of the switching frequency. A rejection of10 dB is found around . Other harmonic responses are lowerthan the maximum attenuation (16 dB) posed by the switch re-sistance and parasitics of the board, and are not observable inthe measurement results.Fig. 20 compares the calculated and measured values for

folding back from all of the harmonics of up to 15th. In thismeasurement the switching frequency is taken to be 100 MHzand we have removed the transformer and applied a microwavehybrid with wider frequency band in order to remove the band-width limitation from the transformer. For odd harmonics, thedeviation between measurement and calculated results is dueto band limitation imposed by the parasitics of the input of thechip. Even-order harmonics are rejected ideally, but mismatchand clock errors limit the rejection. Fig. 20 shows that spectralaliasing from even harmonics is better than 60 dB. Measure-ment results of the in-band image rejection are presented inFig. 21 and prove to be better than 50 dB.The differential architecture also reduces the power leakage

from the switching clock to the RF input. In Fig. 17, the risingand falling edges of the clock mainly produce a common-modesignal, which is suppressed by the common-mode rejection ofthe transformer. At the RF input, a clock leakage power or LOradiation of 62 dBm was measured over the whole band.This is lower than the 57 dBm spurious domain emission limitfor frequencies below 1 GHz, as specified by FCC part 15 [18].Moreover, if a pre-filter is deployed before the N-path filter,the leaked power at harmonics of the switching clock will besuppressed. Note also that in a cognitive radio application, the


Fig. 22. Frequency transfer and at between 0.1 and 1 GHz.

Fig. 23. Measured minimum IIP3 for –1 GHz.

fundamental LO leakage constitutes self-interference. MonteCarlo simulation of process and mismatch variations predict78 dBm clock leakage in the worst case (100 runs), which

suggests that other factors like coupling between wires and sub-strate may dominate the LO leakage. Better layout may provideless leakage due to coupling.The flexible tuning capability of the filter is illustrated in

Fig. 22 for swept from 100 MHz up to 1 GHz. In-bandproves to be better than 10 dB and the voltage transfer char-acteristic exhibits a maximum of 2 dB pass-band attenuationover the entire tuning range. Due to parasitics of the transformerand PCB, some peaking occurs at 100 and 200 MHz center fre-quencies. The main frequency limitations of the current designare related to the clocking circuit and transformer. Wider fre-quency ranges are possible by improving the clocking circuitand removing the transformer for on-chip applications. The im-plemented 4-phase clock generator consumes between 2 mWand 16 mW ( –1 GHz, –4 GHz). The restof the circuit is free of dissipation from the supply.Around the switching frequency, the N-path filter has high

input impedance ( in a 4-path filter). Thus, not muchcurrent flows through the filter and one might intuitively ex-pect good linearity, certainly for large switch-overdrive voltages( 800 mV). Fig. 23 shows IIP3 measurement results where theworst value within the 3 dB bandwidth is reported. It is alwaysbetter than 14 dBm.As derived in Section IV-H, the noise figure of a 4-path filter

without transformer and matching resistance is 0.9 dB, whichfits to SpecreRF transistor-level simulation results in Fig. 24,case 1. For the architecture in Fig. 17 that we have applied for

Fig. 24. Measured and simulated noise figure: case 1–simulation of the un-matched 4-path filter without the transformer and matching resistor; case 2–sim-ulation with ideal transformer and matching resistor included; case 3–measure-ment of the setup in Fig. 17; case 4–the effect of the stray inductance of thetransformer is included in the simulation of case 2.

TABLE ICOMPARISON WITH OTHER DESIGNS

the measurement, assuming an ideal 1:2 transformer, the valueof in (20) and (21) becomes equal to (seeFig. 17). Considering unity voltage gain for thematched input and calculating the noise power from (20) and(21), a noise figure of 3 dB is calculated, again equal to simula-tion (Fig. 24, case 2). In Fig. 24, measurement results (the bufferamplifier noise figure is de-embedded) are shown as case 3,which shows an increasing trend of noise figure at high frequen-cies. Simulations show that stray inductance in the transformerand PCB lines lead to an increment of noise figure at high fre-quencies. Modeling the stray inductance in the secondary of thetransformer, in Fig. 17 should be replaced by an impedancewhich increases with frequency. In this case, the noise generatedby the switch resistances at the output node can no longer be ne-glected, resulting in a noise power increasing with frequency.In Fig. 24, case 4, the simulation of an ideal transformer withmatching resistance and 8 nH stray inductance inseries with the secondary winding of the transformer is shown.Fitting a coupled inductor model with finite coupling factor to a50 MHz–1 GHz bandwidth transformer indicates that such in-ductance values are in the realistic range.


In Table I, the design is compared with two other on-chipfilters, one using Q-enhancement [4] and the other an 8-pathfilter [9], clearly illustrating benefits in tuning range, linearity,and noise. In [9], the achieved Q is increased significantly byincreasing source resistance and also increasing the total ca-pacitance value without providing matching. Inserting a resistordeteriorates the noise figure significantly. Reactive impedancetransformation as employed in this paper ensures a low noisefigure.

VII. CONCLUSION

In this paper, an integrated tunable band-pass filter basedon N-path periodically time-variant networks is analyzed,implemented, and measured. The proposed differential 4-patharchitecture provides a high-Q inductorless filter with a decadetuning range (0.1–1 GHz). The availability of high-qualityswitches in CMOS technology offers high linearity ( 14 dBm)and compression point (2 dBm). According to theory andmeasurement, the architecture can have low noise as well(theoretically close to 1 dB for the unmatched case, 3 dBfor the matched case). A drawback of N-path filtering is theharmonic folding associated with their time-variant nature. Tosuppress folding products, a low-pass pre-filter can be used,which however does not need to be tunable. In the proposeddifferential N-path filter, second harmonic folding is cancelled,which relaxes the pre-filter transition band. Further transitionband extension is possible using higher . As N-path filtersoutperform most receivers in terms of compression point andIIP3, they are one of the few options compatible with CMOSintegration to protect receivers against strong blockers. Webelieve that their extreme tunability by a digital clock and theirhigh linearity and compression point are attractive assets forsoftware-defined or cognitive radio applications.

ACKNOWLEDGMENT

The authors would like to thank G. Wienk and H. de Vriesfor their helpful assistance and Z. Ru and M. Oude Alink forvaluable discussions. The authors also thank NXP for chipfabrication.

REFERENCES

[1] M.Nekovee, “Cognitive radio access to TVwhite spaces: Spectrum op-portunities, commercial applications and remaining technology chal-lenges,” in Proc. IEEE Symp. New Frontiers in Dynamic Spectrum,Apr. 2010, pp. 1–10.

[2] W. B. Kuhn, A. Nobbe, D. Kelly, and A. W. Orsborn, “Dynamic rangeperformance of on-chip RF bandpass filters,” IEEE Trans. CircuitsSyst. II, vol. 50, no. 10, pp. 685–694, Oct. 2003.

[3] X. He and W. B. Kuhn, “A 2.5-GHz low-power, high dynamic range,self-tuned Q-enhanced LC filter in SOI,” IEEE J. Solid-State Circuits,vol. 40, no. 8, pp. 1618–1628, Aug. 2005.

[4] B. Georgescu, I. G. Finvers, and F. Ghannouchi, “2 GHz Q-enhancedactive filter with low-passband distortion and high dynamic range,”IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2029–2039, Sep. 2006.

[5] L. E. Franks and I. W. Sandberg, “An alternative approach to the re-alization of network transfer functions: The N-path filters,” Bell Sys.Tech. J., vol. 39, pp. 1321–1350, Sep. 1960.

[6] L. E. Franks and F. J.Witt, “Solid-state sampled data band-pass filters,”presented at the 1960 IEEE Solid-State Circuits Conf., Philadelphia,PA, Feb. 1960.

[7] Y. Sun and I. T. Frisch, “A general theory of commutated networks,”IEEE Trans. Circuit Theory, vol. CT-16, no. 4, pp. 502–508, Nov.1969.

[8] M. B. Ghaderi, J. A. Nossek, and G. C. Temes, “Narrow-bandswitched-capacitor bandpass filters,” IEEE Trans. Circuits Syst., vol.CAS-29, no. 8, pp. 557–572, Aug. 1982.

[9] A. El Qualkadi, M. El Kaamouchi J. M., Paillot , D. V. Janvier, and D.Flandre, “Fully integrated high-Q switched capacitor bandpass filterwith center frequency and bandwidth tuning,” in IEEE RFIC Symp.Dig., 2007, pp. 681–684.

[10] A. Ghaffari, E. A. M. Klumperink, and B. Nauta, “A differential 4-pathhighly linear widely tunable on-chip band-pass filter,” in IEEE RFICSymp. Dig., 2010, pp. 299–302.

[11] A. Mirzaei, A. Yazdi, Z. Zhou, E. Chang, P. Suri, and H. Darabi, “A65 nm CMOS quad-band SAW-less receiver for GSM/GPRS/EDGE,”in IEEE VLSI Symp. Dig., 2010, pp. 179–180.

[12] B. W. Cook, A. Berny, and A. Molnar, “Low-power 2.4-GHz trans-ceiver with passive RX front-end and 400-mV supply,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2757–2766, Dec. 2006.

[13] M. C. M. Soer, E. A. M. Klumperink, Z. Ru, F. E van Vliet, and B.Nauta, “A 0.2-to-2.0 GHzCMOS receiver without LNA achieving 11dBm IIP3 and 6.5 dB NF,” in IEEE ISSCC Dig. Tech. Papers, 2009,pp. 222–223.

[14] T. Ström and S. Signell, “Analysis of periodically switched linear cir-cuits,” IEEE Trans. Circuits Syst., vol. CAS-24, no. 10, pp. 531–541,Oct. 1977.

[15] M. C. M. Soer, E. A. M. Klumperink, P. T. de Boer, F. E. van Vliet, andB. Nauta, “Unified frequency domain analysis of switched-series-RCpassive mixers and samplers,” IEEE Trans. Circuits Syst. I, Reg. Pa-pers, vol. 57, no. 10, pp. 2618–2631, Oct. 2010.

[16] B. Leung, VLSI for Wireless Communication. Englewood Cliffs, NJ:Prentice-Hall, 2002.

[17] Z. Ru, N. A. Moseley, E. A. M. Klumperink, and B. Nauta, “Digitallyenhanced software-defined radio receiver robust to out-of-band inter-ference,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3359–3375,Dec. 2009.

[18] FCC 47 CFR Part 15, Oct. 1, 2009.

Amir Ghaffari (S’10) was born in Oroumieh, Iran,in 1980. He received the B.S. degree (cum laude) inelectrical engineering from University of Oroumiehin 2002, and the M.S. degree from Iran University ofScience and Technology, Tehran, Iran, in 2006. Heis currently pursuing the Ph.D. degree at the IC de-sign group of the University of Twente, Enschede,The Netherlands.His research focuses on the analog CMOS front-

ends for cognitive radio applications.

Eric A. M. Klumperink (SM’06) was born on April4, 1960, in Lichtenvoorde, The Netherlands. Hereceived the B.Sc. degree from HTS, Enschede, TheNetherlands, in 1982. After a short period in industry,he joined the Faculty of Electrical Engineering of theUniversity of Twente, Enschede, The Netherlands, in1984, participating in analog CMOS circuit designand research. This resulted in several publicationsand a Ph.D. thesis, in 1997 (“TransconductanceBased CMOS Circuits”).In 1998, he started as an Assistant Professor at the

IC Design Laboratory and participated in the MESA+ Research Institute. Hisresearch focus changed to RF CMOS circuits, especially for wireless and wire-line communication. During April–August 2001, he extended his RF expertiseduring a sabbatical at the Ruhr Universitaet Bochum, Germany, in the groupof Prof. U. Langmann and Prof. H. M. Rein. Since 2006, he has been an As-sociate Professor, teaching analog and RF IC electronics courses. He partici-pates in the CTIT Research Institute, guiding Ph.D. and M.Sc. projects relatedto RF CMOS circuit design with focus on cognitive radio, software-definedradio, and beamforming. In 2006 and 2007, he served as a Associate Editorfor IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, in 2008 and 2009 forIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, and since 2011 for IEEEJOURNAL OF SOLID-STATE CIRCUITS. He holds several patents and has authoredand co-authored more than 120 international refereed journal and conferencepapers.Dr. Klumperink was a co-recipient of the ISSCC 2002 and the ISSCC 2009

Van Vessem Outstanding Paper Award.


Michiel C. M. Soer (S’09) was born inSchoonhoven, The Netherlands, in 1984. Hereceived the M.Sc. degree (cum laude) in electricalengineering from the University of Twente,Enschede, The Netherlands, in 2007. He is currentlyworking towards the Ph.D. degree at the IntegratedCircuit Design group at the same university.His research interests include mixers, discrete time

systems, and phased arrays in CMOS.

Bram Nauta (F’08) was born in Hengelo, TheNetherlands, in 1964. In 1987, he received the M.Scdegree (cum laude) in electrical engineering from theUniversity of Twente, Enschede, The Netherlands.In 1991, he received the Ph.D. degree from the sameuniversity on the subject of analog CMOS filters forvery high frequencies.In 1991, he joined the Mixed-Signal Circuits

and Systems Department of Philips Research,Eindhoven, The Netherlands, where he worked onhigh-speed AD converters and analog key modules.

In 1998, he returned to the University of Twente, as a full Professor headingthe IC Design group, which is part of the CTIT Research Institute. His currentresearch interest is high-speed analog CMOS circuits. He is also a part-timeconsultant in industry, and in 2001 he co-founded Chip Design Works. HisPh.D. thesis was published as a book: Analog CMOS Filters for Very HighFrequencies (Springer, 1993).Prof. Nauta received the Shell Study Tour Award for his Ph.D. work. From

1997 until 1999 he served as Associate Editor of IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS II, ANALOG AND DIGITAL SIGNAL PROCESSING. Afterthis, he served as Guest Editor, Associate Editor (2001–2006), and from 2007to 2010 as Editor-in-Chief for the IEEE JOURNAL OF SOLID-STATE CIRCUITS.He is a member of the technical program committees of the IEEE InternationalSolid State Circuits Conference (ISSCC) where he has the role of EuropeanChair, the European Solid State Circuits Conference (ESSCIRC), and theSymposium on VLSI Circuits. He is a co-recipient of the ISSCC 2002 and2009 Van Vessem Outstanding Paper Award. He has served as a DistinguishedLecturer of the IEEE and an elected member of IEEE SSCS AdCom. He is anIEEE fellow.

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Multi-path filter design