Multi-DSP/Micro-Processor Architecture (MDPA)

T. Helfers; E. Lembke; P. Rastetter; O. Ried

Astrium GmbH

Microelectronics Presentation Days 201030 March 2010, ESA/ESTEC, Noordwijk

26.03.2010

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ContentMotivationMDPA ASIC FeaturesBlockdiagramPhysical LayoutASIC statusApplication: Payload Controller using MDPA ASICApplication: Mass Memory Controller using MDPA ASICAvailable Software ToolsOutlook

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MotivationImplementation of a System-on-Chip (SOC) based on LEON2FT to serve upcoming Telecom and EO MissionsGeneral Requirements

High Control Processing PerformanceScalable to multiprocessor system via SpaceWire with routing capabilitySpacecraft interface via Milbus or SpaceWirePayload interface via MilBus, SpaceWire or CAN bus

Specific Telecom RequirementsDVB-S regeneration function for high speed TM/TC interface with Network Control Center (600Kbps each direction)Radiation hardened to operate 15 years in GEO orbit without uncorrectable error

MDPA (MultiDSP/microProcessor Architecture)

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MultiDSP/µProcessor Architecture (MDPA) ASICLEON2FT based System-on-Chip (SOC) operating at up to 80MHz; factor 5 of ERC32 performance (Hartstone benchmark)First SOC with SpaceWire router (path addressing) on-chip with 8 SpaceWire links operating at up to 200MbpsFurther on-Chip features:

IEEE- 754 Floating Point Unit (Meiko)2 MilBus 1553 Controllers (Astrium SAS IP)1 CAN bus 2.0 Controller (ESA IP)2 UARTsModem based on DVB-S standard protocol (Astrium Ltd IP)RMAP client compatible SpaceWire linkDebug Support Unit and Service interfaceWatchdog, Timing functions

Technology: Atmel ATC18RHAPackage: CQFP352 Testing according to QML-Q and QML-V

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MDPA SoC Blockdiagram

AHB

Legend:HP/LP CIC: High Priority/Low Priorirty Communication Int. Contr.PIC: Primary Int. Contr.

SRAMPROM

IO

D-CacheI-CacheAHB

Debug comm.

link

AHB AHB

Tracebuffer

DebugSupportUnit

SpaceWire Module 1

AHB | DMA

MemCtrl

A H B

1553 RT, BCDSP Block

(DVBS-Modem)

SpaceWire I/F

FIFO I/F

writeprotect

AHBArbiter/Decoder

Status

AHB

AHB

APB

APB 2

AHBAPB

UARTHP/LP CIC

PIC

TIMERsWatchdog

APB 1

SIF

CAN

Embedded Test IP

AHB | DMA

SpaceWire Module 2

AHB | DMA

GPIO2

UARTs

GPIO

WDOG

OBTF/SCET

Meiko FPU

LEON2FTIU

Redundant 1553 Interface

Leon Config

DSP register and memory

space

SpaceWire

UART

1553 BC

AHB | DMA

Redundant 1553 Interface

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MDPA SoC ElementsBasic Elements of MDPA SoC

LEON2-FT ProcessorHardwired DVB-S algorithmsGeneral Purpose ClockUARTs with FIFOSpaceWire I/Fs (with limited RMAP support)Service Interface (SIF)Two MIL-STD-1553B Interfaces (RT and BC)CANbusTime distribution services

Real Time Clock (RTC)Spacecraft Elapsed Time (SCET)Cycle Time (CT)

Additional Processing FeaturesFloating Point Unit (FPU)WatchdogNon maskable interrupt (NMI)Reset detection registerSoftware resetGPIO extensionSRAM bank swapSRAM Chip SelectsDebug Support via SpW and UART interface

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MDPA SoC Physical Layout

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ASIC statusValidation Prototypes available since July 2009Industrial Prototypes available since September 2009Industrial Prototypes have been tested by Atmel over military temperature range at speed (80MHz)Industrial Prototypes have been implemented on controllermodule board and have been fully functional tested up to 80MHzQML-V parts have been packaged and are currently undertest at AtmelAvailability of QML-V Flight parts: end of April

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AlphaSAT Payload Controller with MDPAMDPA receives mobile communication requests and configures on-board switch subsystem accordinglyNetwork Control Channel is regenerated by on-chip modemOn-Board Switch connected via 8 SpaceWire links usingRMAP protocolSpacecraft I/F: MilBus 1553 RT16 Mbyte SRAM workingmemory, 2x 4Mbyte EEPROM, 64KByte PROM capacity15 years GEO orbit operation

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AlphaSAT Payload Controller Blockdiagram

TRX TRX

TRF TRF

MIL-BUS A

MIL-BUS B

BUFFER

DSU UART

LVDS

SIF

40MHz

Power-On-Reset

clk

TRX/RS-485

CAN A

AHB arbiter /decoder

write protectstatus

Memory controller SpaceWireOBT

SCET Watchdog

GPIO UARTs

DVB-S modem MIL-STD-1553B CAN-B Boundary Scan embedded test

Interrupt controllerWarm_start register

Configuration registers

DSUAHB

/APB

SIFAHB APB

LEON2-FTFPU

clk

LVDS

SpaceWire1 ..16

Processing core

MDPA Controller

CACHE

LVDS

DSU SpW CAN B

LVDS

TM/TC

SRAM16Mbyte

PROM128Kbyte

EEPROM 8Mbyte

BUFFERBUFFER

BUF

JTAG

Serial Flash

RS-422

PPSSYNC

...

UART

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AlphaSAT Payload Controller EQM Unit

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Next Generation Mass Memory Supervisor using MDPAMDPA based controller and file system manager for nextgeneration flash, SDRAM or DDR-RAM based mass memoriesSupports MilBus, CAN, UART or SpaceWire externalinterfacesInternal 16bit wide parallel memory module interfaceMain advantages over ERC32:

Higher performance by factor 5Highly integrated , lower power (3.5W for board @40MHz)More sophisticated test interface (direct register/memory access via DSU; watchpoints, Breakpoints, single stepetc)

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Available Software ToolsBoot strapLow level Software routines according to ECSS-E40Debug Support Unit Monitor (e.g. from Aeroflex Gaisler)Service Interface box (USB interface) with host tools for software download, monitoring, task level debugging and task timing toolMDPA simulator

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Conclusion and OutlookFirst implementation of LEON2FT with SpaceWire and routing functionalityMDPA ASIC full operational with 80MHz of processingspeedVersatile payload equipment controller can be realiseddue to

High number of interfaces and functions on chipHigh CPU performance at low power due to high integratedsemiconductor technology (0.18micron)Robustness of the design due to various error protection methodsState-of-the-art assembly methods (Quad flat pack)

The MDPA chip can be made available to interested parties on case by case basis