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CURRICULUM VITAE
SHIVARUDRAIAH. B
S/O Basavarajaiah. B. S
Byandahalli,
Kadabagere Post,Bangalore North Thaluk E-mail:
[email protected]: 562130 Mobile: +91-9482138388
To work on innovative solutions by applying and developing my
technical skills
as a software professional with gifted colleagues in an
environment that builds and
rewards creative thinking and teamwork.
CourseName of the Name Name of the Institution University Year
of
passing
Aggregate
percentage
M. Tech
[VLSI Design
& EmbeddedSystems]
Dr. Ambedkar
Institute of
Technology,Bangalore
Visveswaraiah
Technological
University,Belgaum
2010 76.88%
B. E
[Electronics andCommunication]
East West
Institute ofTechnology,
Bangalore
Visveswaraiah
TechnologicalUniversity,
Belgaum
2008
69.96%
Pre-University
course
K.L.E'S
Independent Pre-University College,
Bangalore
Karnataka Pre-
University Board
2004 80.83%
SSLC
St. Chistys High
School , Bangalore
K.S.E.E. Board 2002 84.16%
EDUCATIONAL QUALIFICATION
CARRIER OBJECTIVE
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Hardware Programming Verilog HDL, Microprocessor 8085, 8086
Microcontroller 8051.
Software Programming Basics of C, C++.
Basic Electronics, Logic Design, Analog & Digital
Communication, Embedded
system design, Synthesis & Optimization of digital circuits,
CMOS VLSI design, and
CMOS RF circuit design.
Front end Verilog and front end design Verification
Project Name: Implementation of a Multi-channel UART Controller
Based on FIFOTechnique and FPGA
Description: To meet modern complex control systems
communication demands, we
need to go for designing a multi-channel UART controller based
on FIFO(First In First
Out) technique and FPGA(Field Programmable Gate Array). It
includes the design of
asynchronous FIFO and structure of the controller. This
controller is designed with FIFO
circuit block and UART (Universal Asynchronous Receiver
Transmitter) circuit block
within FPGA to implement communication in modern complex control
systems quickly
and effectively. Form the communication sequence diagrams; it is
easily to know that this
controller can be used to implement communication when master
equipment and slaver
equipment are set at different Baud Rate. It also can be used to
reduce synchronization
error between sub-systems in a system with several sub-systems.
The controller isreconfigurable and scalable. Keywords: FIFO, FPGA,
UART.
Project Name: Advanced ATM Monitoring System
Description: This is an automation system for the ATM which also
enhances the security
functions at ATM center. This automation system will have
installation feature which
TECHNICAL SKILLS
MAJOR SUBJECTS STUDIED
WORKSHOP ATTENDED
PROJECTS
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will remove the human intervention in switching ON/OFF the
lights both inside and
outside of ATM center which would result in power saving.
Software: Embedded C,
Keil.
Date of Birth : 28-08-1987
Sex : Male
Nationality : Indian
Languages Known : English, Kannada, and Hindi
Strengths :Team player, Integrity, Good communication skills
Hobbies : Following all kinds of sports, participating in extra
curricular
activities like quiz competition, listening to music etc
I here by declare that all the above details are true according
to the best of my
knowledge and belief.
Place:
Date: [Shivarudraiah. B]
PERSONAL PROFILE
DECLARATION
