P.E.S.I.T Bangalore South CampusDept of Electronics and Communication Engg.

TIME – TABLE for the Academic year 2015-16M.Tech – VLSI Design and Embedded System (14LVS)

Semester: 1st

Day 8.15 – 9.15 9.15 – 10.15 Break 10.45 – 11.45 11.45 – 12.45 Lunch 1.30 – 2.30 2.30 – 3.30

MondayDSDV DSDV ESD VPT

Tuesday DVD DVD VLSI &ES LAB1 AMAT AMAT

WednesdayVPT VPT AMAT AMAT

ThursdayDSDV DSDV ESD ESD

FridayESD VPT DVD DVD

Saturday

Course Code

Subject Code

Name of subject Staff In charge

14LVS11 Advanced Mathematics -1 Dr.Bharat14LVS11 VLSI Deisgn Raghavendra14LVS11 Advanced Embedded System

(AES )Anand M

14LVS11 VLSI Process Technology Kala14LVS11 Digital System Design Using Verilog Cheerajeevi.G.N

TTO (W.E.F 16-01-2012) HOD

(DSDV)

P.E.S.I.T Bangalore South CampusDept of Electronics and Communication Engg.

TIME – TABLE for the Academic year 2015-16M.Tech – Signal Processing (14LSP)

Semester: 1st

Day 8.15 – 9.15 9.15 – 10.15 Break 10.45 – 11.45 11.45 – 12.45 Lunch 1.30 – 2.30 2.30 – 3.30

MondayADSP ADSP SSP SSP

Tuesday ASP ASP SAP SAP AMAT AMAT

WednesdayADSP ADSP AMAT AMAT PAL

ThursdayASP ASP SAP SAP PAL PAL

FridaySPLAB1 SPLAB1 SSP SSP SAP

Saturday

TTO (W.E.F 16-01-2012) HOD

Course Code

Subject Code

Name of subject Staff In charge

14ELD11 Advanced Mathematics -1 (AMAT) Dr.Bharat14ESP13 Advanced Digital Signal Processing (ADSP) S.Pal14ESP14 Adaptive Signal Processing (ASP) S.Pal14ESP12 Statistical Signal Processing (SSP) Ajey SNR14ESP153 Speech and Audio Processing (SAP) Dr.Ramsubramanya

14ESP16 Signal Processing lab 14ESP17 Seminar on Advanced topics from refereed journals

TTO (W.E.F 16-01-2012) HOD