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TCL L42M61S2 SERVICE MANUAL
MT02
1 Caution 2 2 Specification of Chassis 6 3 Theory of circuits 7 4 Alignment Procedure 16 5 Block Diagram 28 6 Schematic Diagram 30 7 Trouble shooting 49 8 53 9 BOM list
This manual is the latest at the time of printing, and does not include the modification which may be made after the printing, by the constant improvement of product
WARNING: TO REDUCE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT
EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE.
CAUTION: TO REDUCE THE RISK OFELECTRICAL SHOCK, DO NOT REMOVECOVER (OR BACK). NO USER SERVICEABLEPARTS INSIDE. REFER SER VICING TOQUALIFIED SERVICE PERSONNEL.
The lighting flash with arrowhead symbol, with an equilateral triangle is intended toalert the user to the presence of uninsulated voltage within the productsenclosure that may be of sufficient magnitude to constitute a risk of electric shock tothe person.
The exclamation point within an equilateral triangle is intended to alert the user to thepresence of important operating and maintenance (servicing) instructions in theliterature accompanying the appliance.
CAUTION:
Use of controls, adjustments or procedures other than those specified herein may result inhazardous radiation exposure.
CAUTIONRISKRISK OF ELECTRIC
SHOCK DO NOT OPEN.OPEN.
FOR YOUR PERSONAL SAFETY1. When the power cord or plug is damaged or frayed, unplug this television set from the wall outlet and refer servicing to
qualified service personnel.
2. Do not overload wall outlets and extension cords as this can result in fire or electric shock.
3. Do not allow anything to rest on or roll over the power cord, and do not place the TV where power cord is subject totraffic or abuse. This may result in a shock or fire hazard.
4. Do not attempt to service this television set yourself as opening or removing covers may expose you to dangerousvoltage or other hazards. Refer all servicing to qualified service personnel.
5. Never push objects of any kind into this television set through cabinet slots as they may touch dangerous voltagepoints or short out parts that could result in a fire or electric shock. Never spill liquid of any kind on the television set.
6. If the television set has been dropped or the cabinet has been damaged, unplug this television set from the wall outletand refer servicing to qualified service personnel.
7. If liquid has been spilled into the television set, unplug this television set from the wall outlet and refer servicing toqualified service personnel.
8. Do not subject your television set to impact of any kind. Be particularly careful not to damage the picture tube surface.
9. Unplug this television set from the wall outlet before cleaning. Do not use liquid cleaners or aerosol cleaners. Use adamp cloth for cleaning.
10.1. Do not place this television set on an unstable cart, stand, or table. The television set may fall, causing serious injuryto a child or an adult, and serious damage to the appliance. Use only with a cart or stand recommended by themanufacturer, or sold with the television set. Wall or shelf mounting should follow the manufacturer s instructions, andshould use a mounting kit approved by the manufacturer.
10.2. An appliance and cart combination should be moved with care. Quick stops, excessive force, and uneven surfacesmay cause the appliance and cart combination to overturn.
CAUTION:
Read all of these instructions. Save these instructions for later use. Follow all Warnings and
Instructions marked on the audio equipment.
1. Read Instructions- All the safety and operating instructions should be read before the product is operated.
2. Retain Instructions- The safety and operating instructions should be retained for future reference.
3. Heed Warnings- All warnings on the product and in the operating instructions should be adhered to.
4. Follow Instructions- All operating and use instructions should be followed.
IMPORTANT SAFETY INSTRUCTIONS
PROTECTION AND LOCATION OF YOUR SET
11. Do not use this television set near water ... for example, near a bathtub, washbowl, kitchen sink, or laundry tub, in awet basement, or near a swimming pool, etc.Never expose the set to rain or water. If the set has been exposed to rain or water, unplug the set from the walloutlet and refer servicing to qualified service personnel.
12. Choose a place where light (artificial or sunlight) does not shine directly on the screen.
13. Avoid dusty places, since piling up of dust inside TV chassis may cause failure of the set when high humidity persists.
14. The set has slots, or openings in the cabinet for ventilation purposes, to provide reliable operation of the receiver, toprotect it from overheating. These openings must not be blocked or covered.
Never cover the slots or openings with cloth or other material.Never block the bottom ventilation slots of the set by placing it on a bed, sofa, rug, etc.Never place the set near or over a radiator or heat register.Never place the set in enclosure, unless proper ventilation is provided.
PROTECTION AND LOCATION OF YOUR SET
15.1. If an outside antenna is connected to the television set, be sure the antenna system is grounded so as to provide someprotection against voltage surges and built up static charges, Section 810 of the National Electrical Code, NFPA No.70-1975, provides information with respect to proper grounding of the mast and supporting structure, grounding of thelead-in wire to an antenna discharge unit, size of grounding conductors, location of antenna discharge unit, connectionto grounding electrode, and requirements for the grounding electrode.
15.2. Note to CATV system installer : (Only for the television set with CATV reception)
This reminder is provided to call the CATV system attention to Article 820-40 of the NEC that providesguidelines for proper grounding and, in particular, specifies that the cable ground shall be connected to the groundingsystem of the building, as close to the point of cable entry as practical.
16. An outside antenna system should not be located in the vicinity of overhead power lines or other electric lights or powercircuits, or where it can fall into such power lines or circuits. When installing an outside antenna system, extreme careshould be taken to keep from touching such power lines or circuits as contact with them might be fatal.
17. For added protection for this television set during a lightning storm, or when it is left unattended and unused for longperiods of time, unplug it from the wall outlet and disconnect the antenna. This will prevent damage due to lightningand power-line surges.
ANTENNALEAD- IN WIRE
ANTENNA DISCHARGE
UNIT (NEC SECTION
810-20)
GROUNDING
CONDUCTORS
(NEC SECTION810-21)
GROUND CLAMPS
POWER SERVICE GROUNDING
ELECTRODE SYSTEM
(NEC ART 250. PART H)
ELECTRIC SERVICEEQUIPMENT
GROUND CLAMP
NEC-NATIONAL ELECTRICAL CODE
EXAMPLE OF ANTENNA GROUNDING AS PER
NATIONAL ELECTRICAL CODE
EXAMPLE OF ANTENNA GROUNDING AS PER NATIONAL ELECTRICAL CODE INSTRUCTIONS
a built-in
installer s
OPERATION OF YOUR SET
18. This television set should be operated only from the type of power source indicated on the marking label.If you are notsure of the type of power supply at your home, consult your television dealer or local power company. For televisionsets designed to operate from battery power, refer to the operating instructions.
19. If the television set does not operate normally by following the operating instructions, unplug this television set from thewall outlet and refer servicing to qualified service personnel. Adjust only those controls that are covered in the operatinginstructions as improper adjustment of other controls may result in damage and will often require extensive work by aqualified technician to restore the television set to normal operation.
20. When going on a holiday : If your television set is to remain unused for a period of time, for instance, when you go ona holiday, turn the television set and unplug the television set from the wall outlet.
IF THE SET DOES NOT OPERATE PROPERLY
21. If you are unable to restorenormal operation by following the detailedprocedure in your operating instructions,do not attempt any further adjustment. Unplug the set and call your dealer or service technician.
22. Whenever the television set is damaged or fails, or a distinct change in performance indicates a need forservice, unplug the set and have it checked by a professional service technician.
23. It is normal for some TV sets to make occasional snapping or popping sounds, particularly when beingturned on or off. If the snapping or popping is continuous or frequent, unplug the set and consult yourdealer or service technician.
FOR SERVICE AND MODIFICATION
24. Do not use attachments not recommended by the television set manufacturer as they may cause hazards.
25. When replacement parts are required, be sure the service technician has used replacement parts specifiedby the manufacturer that have the same characteristics as the original part. Unauthorized substitutionsmay result in fire, electric shock, or other hazards.
26. Upon completion of any service or repairs to the television set, ask the service technician to performroutine safety checks to determine that the television is in safe operating condition.f
EM BUSINESS CENTER FTV PRODUCT PLANNING DEPT.
SPECIFICATION RELEASE Version: V1.0 Issued Date: 2007.06.25
PICTURE
Panel Size (inch) 42
Category LCDTV
Aspect Ratio 16:9 Color Temperature Adjustable(Cold,Warm,Standard) SIGNAL FORMAT CAPABILITYBacklight Adjustable Yes Component Video Format Y,Pb/Cb,Pr/Cr: up to 720p,1080i@50Hz/60HzScaler Mode 16:9,16:9 subtitles,4:3,Cinema DVI Video Format -Picture Effect 4 (Bright,Standard,Soft,Personal) HDMI Video Format (720p,1080i)@50Hz/60HzFilm Mode (3:2 pull down) Yes PC Compatibility VGA/HDMI: Up to SXGA (1280*1024 @75Hz)Picture Enhancement TERMINALS Comb Filter 3D Audio/CVBS Input (Composite) 3 Video + 3 R/L :AV1 and AV2 rear,AV3(side) Gamma Correction Yes S-Video Input 1
3D+ Engine (Advanced flesh tone and color processing) Audio Input for S-Video Share with AV2MDDi Engine (2nd generation proprietary de-interlacing technology) YPbPr Input 1
Blue Stretch - Audio Input for YPbPr 1 R/L Black Stretch Yes YCbCr Input Share with "YPbPr"
Automatic Luma/Chroma Gain Control Yes Audio Input for YCbCr Share with Audio Input for "YPbPr" DLTI Yes VGA Input(RGB) 1 (D-Sub,15-Pin) DCTI Yes Audio Input for RGB 1 ( 3.5mm) Dynamic Skin Correction Yes DVI - DNR Yes (Motion-adaptive 3D Noise Reduction) Audio Input for DVI -Panel Specification HDMI 1 Panel supplier LPL Audio/CVBS Output (Composite) 1 (R/L+CVBS) (RCA) Viewing Technology SIPS Woofer Output 1 Display Resolution WXGA (1366*768) Headphone Output 1 ( 3.5mm ) Brightness (cd/m2) 500 RF Input(Antenna) 1 (F Type) Contrast Ratio 1000:1 USB - Response Time 5ms (G to G) BASIC INFO. Viewing Angle (H/V) 178°/178° TV System NTSC M,PAL M/N Life Time 50,000hrs (min) AV System NTSC/PAL Color 16.7M Channels 125(CATV)+68(Antenna) free program presets
SOUND Chassis MT02Speakers 2 Integrated (bottom side) Certification CBAudio Power Output 8W*2 Power Supply AC 110V-240V 50/60HzSound Processing MTS Stereo(BTSC-SAP) Power Consumption-TV on 220WDVSS(Dolby Virtual Surround) - Power Consumption-Standby Less than 3WAVC(Auto Volume Control) Yes Default Color of Front Cabinet BlackBBE - Keyboard Position TopSRS - Base Stand Detachable Yes
Unpackaged Dimension for Main Body (L*H*D) (mm) With Base Stand (mm) 1058*765*270
Sound Control Volume,Balance,Sound Effects etc.. Without Base Stand (mm) 1058*711*116FUNCTION Packaged Dimension (L*H*D)
V-Chip Yes Main Body (mm) 1211*889*364CCD(Closed Caption) Yes Speaker Box (mm) --Teletext - Base Stand (mm) Packaged with Main BodyPIP/POP - Net Weight (Kg) 27.5 (Main Body and Base Stand)Macro Vision Yes Gross Weight (Kg) 33 (main body and base stand)Calendar - Container Loading Clock/Timers 24h Timer turn ON/OFF;Sleep timer 20 feet 56 With base standLock Yes (parental lock) 40 feet 118 With base standOSD language English/Spanish/Portuguese/French 40 feet high 177 With base standOSD Features - ACCESSORIESCard Reader - Operation Manual English(Default)DVD Combo - Remote Control For TV control (with two 5# batteries)USB Connection - Base Stand YesGame - Speaker Box IntegratedScreen Saver - Wall Mount Optional (WMB400)Demo Function - Others AC Power cordFavourite Channels Yes (6)
Design and specifications are subject to change without notice! Page 1 of 1
Approved by:
Drafted by:
Model: L42M61S2
Sound Effects (Stereo,Music,News,Movie,Personal),AVL,Treble,Bass,WooferSound Features
Core Technology
Theory of circuitsChassis MT02 adopt MT8202 of MTK Company. MT8202 is configured with video decoder, audio
decoder, CPU, decoder, and picture quality processor. Power supply unit is JSK4338. This chassis is
high picture performance and fully integrated IC, matching circuit and alignment is very simple.
Refer to LCD42K73/MT02 as representative, the power consumption is 240W Max. , the standby
consumption is less than 1W. The Sound speaker’s power is 2x8W.The PSU(power supply unit) has 3
part voltage output: 5v for standby, 24v for inverter, 12v for signal process.
This chassis compose of 7 boards, they are main board, tuner board ,AV board, side AV board, keypad
board, USB board, power board.
The unit supports 1x RF in, 2XAV,1x S-video and common AV audio input. 2xUSB input , one way has
print function, the another way connect with high definition signal source ,it supports SDTV, HDTV, The
highest signal format reaches 1920 1080@60I 1xVGA input, supports the signal format have VGA,
SVGA XGA SXGA 1xheadphone output ,1x AV output. 1xHDMI input , supports most of HDMI format
of video and audio input.
Chapter I Signal Flowing Introduction
There are 7 boards for signal process: main board, tuner board, AV board, side AV board, keypad board,
USB board, power board. Section I Tuner board signal flowing introduction
Turner board mostly assemble are turner and I2C bus control TDA9886 and audio .video SAW filter circuit.
TV signal flow: 75OMH antenna received high frequency TV signal input to tuner U601A disposal. U601A is a common tuner .through tuner inside circuit disposal: high frequency amplifier, mixing, filtering, IF amplifier, detection, pre-video amplifier, AGC, AFT, PLL etc. From U601A output IF signal through Z610,Z611 disposal, PIF and AIF signal send to Pin1,Pin2,Pin23,Pin24 of IC601, after TDA9886 IF amplifier disposal, from pin17 output color full TV signal into audio disposal circuit process .
TDA9886 is multi system video and audio IF signal PLL demodulator without adjustment, using for positive and negative modulator and AM/FM processor. Characters as follow:
1. Power supply voltage of 5V 2. Gain controlling broad band PIF amplifier AC coupling 3. Multi standard synchronization demodulation, linearity demodulation 4. Multi system PIF 5. Audio IF disposal IC
This manual just used for experienced technician, not for any public people. There is not any caution and mention in this manual for one whom unqualified technician attempt to service this product. This product should be serviced by special technician, only other persons attempt to service it might have heavy hurt even have life hazard.
6. Audio apart circuit 7. Reducing the picture interference from audio 8. Full integrated VCC 9. 4M norm frequency input 10. Accurate fully digital AFC detector, 4 bit ADC, through IIC BUS exchange AFC data. 11. Through IIC adjusts receive point 12. SIF-AGC, gain control SIF amplifier single norm QSS 13. AM demodulation without outside reference circuit 14. Choose FM-PLL demodulation without adjustment ,high linearity and low noise
Pin function OSD NO FUNCTION VIF1 1 VIF difference input
1VIF2 2 VIF difference input
2NC Empty pin OP1 3 Output port 1 FMPLL 4 Loop filter FM-PLL DEEM 5 Get rid of aggravate
output AFD 6 AF demodulation
coupled DGND 7 Figure grounding NC Empty pin AUD 8 Audio input TOP 9 Tuner received point SDA 10 IIC data input and
output SCL 11 IIC clock input SIOMAD 12 Inside carrier
frequency audio output MAD option
NC Empty NC 13 Empty NC Empty TAGC 14 Tuner AGC output REF 15 4M crystal or norm
signal output VAGC 16 VIF_AGC NC Empty pin CVBS 17 Complex video
signal output NC Empty pin AGND 18 Analog grounding VPLL 19 Loop filter FM-PLL VP 20 Power supply AFC 21 AFC output OP2 22 Output port 2 NC Empty pin SIF1 23 SIF difference input
1SIF2 24 SIF difference input
2NC Empty NC Empty
Section II Digital board signal flowing introduction
LCD42K73/MT02 digital board chassis adopted ICs are U27-DC change DC disposal circuit, makes the 12v changed to 5v, U21 U23 U24 U37-AZ1117 are three-terminal voltage regulator, it makes 3.3v changed to 1.8v; U3-MT8202 IC include CPU, audio/video decoder, picture tone disposal etc functions; U4 U5-M13S128168 8M picture ,audio memory, U7-29LV160 saves CPU programs; U36-CM2021 HDMI socket prevent static regulator; U8-MT8293 HDMI decode regulator; U11-EEPROM 24C02; U12-CS5340 audio A/D change input ; U13-HEF4052 audio change switch U14-P15V330 video change switch.; Signal input:
Signal input include:one way RF signal,three ways AV signal, VGA,HDMI,YUV. 1 RF input From high frequency board sends CVBS connected to digital board through JP6. Video signal: from pin5 of the JP6 sends CVBS signal, through R354 limiting current, coupled by CE197 signal
sent to Q3 and video signal amplify , from emitter of Q3 sent video signal to D25pin of 8202 IC, process TV video signal decode disposal.
Audio signal: audio signal from pin7 of JP6 sent out and separate two paths TUMPX1 TUMPX2 signal. They are through filter which compose of R212 C48 C139 and R215 C143 R216 C144, the audio signal after filter input to C26pin B26pin of U3 process audio signal decode.
2 AV signal input From CN2 CN5 CN7 input AV1 AV2 AV3 signal, each through D11 D12 D13 prevent static protection
IC process disposal. Video signal: Video signal AV1_ V/AV2_ V/AV3_ V A1/A2/C1 sent to U3 process picture signal disposal.
AV1 AV2 AV3 video signal: From JP603 JP604 JP605 sent AV1 AV2 AV3 video signal through D11 D12 D13 prevent static
protection IC process disposal. Video signal after filtering by filter which compose of C11 R118 C13 R119C7 C8 R96 R101, then input U3’s PinD26, PinE26, PinE25 and disposal video signal.
Audio signal: Audio signal of AV1 AV2 AV3 from JP603 JP604 JP605 output L/R audio signal, through filter circuitry
which compose of CE15 R26 CE18 R34 CE17 R28 CE20 R36 and input audio switch IC U2, through U2 to change the audio signal for corresponding signal channel and output L/R audio signal from Pin13 and Pin3, then send to digital audio disposal IC U3. The digital audio signal from U3’s P1~P4 pin output, through U15 digital/simulative change ,output L/R simulative audio signal send to audio power amplifier U17A.
3 S-video signal input video channels: S-video signal from JP607 input, the Y C signal separate two ways to process. First channel signal :pin1 of JP607 output Y signal through R46 limiting current and coupled by C14 get
AVSY0 signal connected to Pin F25 of U3 to process video disposal. Second channel signal; pin2 of JP607 output Y signal through R44 reduced voltage, FB10 C16 C17 restrain
noise signal interference and filter , coupled by C17 and get AVSC0 input PinF26 of U3 to process video disposal. Audio channel: share with the channel of AV3.
4 YUV HDTV input From CN1 input Y U V signal, through L53 L54 L55 filtering , CN2 connected audio signal. Video channel: Y U V signal separate through R199/R55 R203/R206 R207/R210 limiting current, coupled
by C112/C115 C119/C122 C129/C133. The signal of YO+/YO- PBO+/PBO- PRO+/PRO- connected to U3’s PinP25 P26 N25 N26 I25 I26 process video disposal.
Audio signal: Pin4 and pin2 of the CN2 output YUV_AUDIO_L YUV_AUDIO__R audio signals separate through CE192 CE193
coupled, then filter by R350/R351 R352/R353. Direct input PinA25/A26 of U3 to proceed audio decode disposal. 5 VGA signal input From P2 input VGA’s R G B horizontal and vertical signal. Video channel: From P2 output VGA’s R G B signal through R131/R137/R145 limiting current, coupled by
C88/C92/C97 and get RED+/RED- GREEN+/GREEN- BLUE+/BLUE- signal separate connected with U3’s
PinR26/R25 PinT26/T25 PinU26/U25, pin14 and pin13 of P2 output H/V signals separate through R332 R333C100 C102 coupled to PinV25 and PinV26 of U3 to proceed video signal disposal.
6 HDMI signal input P1 input HDMI signal, dispart as one couple of clock signals and three couples of data signal. Pin12 and pin10
of P1 output R1XC- R1XC+ clock signal through IC U36 disposal then connected to pin50 and pin51 of U8(MT8293),pin9/pin7/pin6/pin4/pin3/pin1 output DATA0-/DATA0+ DATA1-/DATA1+ DATA2-/DATA2+dates through U36 disposal then connect to pin54 /pin55/pin58/pin59/pin62/pin63 of U8,after U8 disposal then dispart as two paths output.
Video channel: pin95 –pin92/pin99-pin105/pin108-pin111, pin114- pin117/pin121-pin124/pin110-pin113 of U8, output 24 bits date signal VI[0 23],through RN26~RN32 connected to U3’s AF20 AE20 AD20 AD21 AC21AF22 AE22 AD22 AF23 AD23 AF24 AE24 AD24 AF25 AF26 AE25 AE26 AD25 AD26AC25 AC26 pin1 and pin128 of U8 output HDMI-HS H/V synchronization signals; process video processing... Pin71-pin74 of U8 output four paths digital audio signal separate connected to pin AA23~AA26 of U3 to process digital audio decode processing..
Video signal processing: Through first channel input U3’s CVBS signal, AV signal, S-VIDEO signal, YUV signal, through inside
option switch control output analog signals, after analog to digital conversion module makes the analog signal change to digital signal.
Under U3’s memory controller controlling, the built-in video decoder, format converter and external flash U4,U5(M13S128168 8M), the signal through 3D comb filtering, color decoder, synchronization signal disposal, VBI amplitude limitation, diagonal angle disposal, noise reducer, progressive converter, format zoom converter, picture quality enhance and so on disposal, and generate main picture’s display matrix.
Through second channel input U3 digital signal, under the MCU controlling, to improve picture quality of sub-picture, and generate display matrix of sub-picture. the two pictures’ signal will be processed picture cover disposal, r correction, LCD speedup drive. OSD display cover disposal, then process output format conversion , changed to LVDS format. Under LVDS transport controller controlling and output display signal to LCD screen interface.Audio signal processing
There were two kinds of signal input to U3: Sound IF signals, chose by switch inside IC, after gain enlarge, after analog to digital converter change to
digital signal. Then send to NICAM decoder, and demodulated audio signal; L/F channels of audio signal chose by switch inside IC after analog to digital converter change to digital
signal. The audio signal which chose by sound switch output from one disposal channel.
Speaker channel: After sound effect disposal, through ADC modulus changed to analog signal. It out from PinA18/A17 of U3, separate input sound disposal circuit, then output to speaker to restore the sound.
Signal output: AV channel output: Video signal: Pin B25 of U3 output simulation complex video signal, after coupled by R181 CE67 and sent to
base of Q7, output from emitter of Q7, then through capacitor CE68 coupling output complex video signal.
LCD display signal output: From pin C12 D12 C11 D11 C10 D10 C9 D9 C8 D8 A12 B12 A11 B11 A10 B10
A9 B9 A8 B8 of U3 output R G B LVDS signal separate connected to pin1~6\10~13\15~16\18~19/22~23 of JP11;P25 pin R26 pin of U3 output DHS H DVS V synchronization signals connected to pin9 and pin8 of JP11,from U3 output CLK+/CLK-display synchronization clock signals connected to pin21 and pin20 of JP11;From U3 output controlling signal connected to pin28 and pin29,pin30 of JP11,then from the cable output to display circuit of LCD, LCD display the picture.
From pinAC18 of U3 output controlling signal PPWR connected to R156 and base of Q31,mixed with +5V,output to pin26 and pin27 of JP11,supply the working power to screen of LCD.
OCM signal controlling: EPROM controlling: U3 through fllowing connection to control the U7: From pinA5 of U3 output signal to control EPROM operation, pinB5 of U3 output signal to control EPROM of
read operation, pinJ2 of U3 output signal to control EPROM of writing operation.
U3 and U7 through following connection to exchange the date. Pin and U7’s
pin10\9\1617\48\1\2\3\4\5\6\7\8\18\19\20\21\22\23\24\25 connected was address line and pin44\42\40\38\35\33\31\29 of U7 connected were data lines
Turn on/off controllingTurn off: through standby turn off,makes the ON/OFF signal output low level ,power board detected ON/OFF
signal output low leve and makes the 12v and 24v shut down, so that into standby state, follow two ways enter standby situation:
when OCM received standby signal, remove control receiver connected to pin7 of JP9, MCU identified the standby order and makes ON/OFF output low level.
real time clock setting controlling, when the timing off is out , then MCU makes ON/OFF output low level. Turn on: ON/OFF signal makes MCU output high level that can turn on the TV, power board detected ON/OFF
signal output high level and the 12v and 24v output. Follow three ways can turn on the TV: When the remove control send out turn on order.
detected PRG+/PRG- button on local control board be pressed. Real time setting control, the turn on time is outing.
Mute circuit controlling: Turn on/off mute
Turn on: when the power booting, at first point, +12v voltage through R59 Q14 charges to C283.makes Q14 turnon, thus output high level pulse, then through Q21 reverse phase output low level pulse ,makes sound power amplifier U16 in standby model, thus it was mute when turn it on.
Turn off :after cut off the power supply, as the 12v voltage was disappear ,but C283 still has voltage,Q15 turn on, makes C283 discharge from Q15,thus output high level pulse , then through Q21 reverse phase output low level pulse ,makes power amplifier U16 in standby model, thus it is muting when turn it off.
MCU controlling mute Controller U3’s Pinw4 send high level pulse signal, it through R336 Q21 makes the sound power amplifier
U16 in standby state ,so that can control turn off in mute state.
Section III Power board signal flow introduction
Input characteristics:
Surge current :100A max when input 220vac
Output characteristics:
Output protection characteristics:
Protect controlling:
Short circuit protection, while there is short circuit in output path, the power supply unit entered short circuit protect,
it is can start up again while short circuit is removed.
Over voltage protection: while voltage output is over voltage, the circuit entered protection situation, it means no voltage output. Over temperature protection, while the temperature rise to abnormal, the circuit entered protection situation, when
the temperature decrease to normal, the power supply unit restore normal.
1 choose project
A Main IC
Using regulated power supply controlling IC L6563 and L6599 of SANTE company.
Basic characteristics:
Two levels over current protection
B Standby IC
Using VIPER22 power supply standby controlling IC of SANTE company, input voltage range:180v-264v,max
rising temperature 40ºC
Basic characteristics:
2 power supply specification:
OUTPUT
VOLTAGE TOLERANCE
CROSS
REGULATION OUTPUT CURRENT
(ACCURACY) 10%~90% LOAD MIN MAX
+24Vdc
5.0% 5.0% 0.5A 14A
(ACCURACY) 10%~90% LOAD MIN MAX
+18Vdc
-10.0%~5.0% 5.0% 0.0A 2.0A
(ACCURACY) 10%~90% LOAD MIN MAX
+12Vdc
5.0% 5.0% 0.5A 7.0A
(ACCURACY) 10%~90% LOAD MIN MAX
+5VSTB
5.0% 5.0% 0.0A 2.0A
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and
pin
9 of
ICS1
C.
Und
er re
gula
r wor
king
con
ditio
ns, d
ue to
the
volta
ge o
f Pin
7 o
f IC
S1B
, Pin
5 o
f IC
S1B
,Pin
9 of
ICS1
C h
ighe
r tha
n Pi
n6 o
f IC
S1B
, Pin
4 of
ICS1
A a
nd P
in8
of
ICS1
C c
orre
spon
ding
, so
the
outp
ut te
rmin
al o
f vol
tage
com
para
tor w
hich
who
se P
in1
of IC
S1B
, pin
2 of
ICS1
A, p
in14
of I
CS1
C o
utpu
t low
leve
l.
Each
low
leve
l thr
ough
DS1
4,D
S8,D
S7 c
onne
cted
to e
mitt
er o
f QS4
, QS4
, QS1
and
QS2
all
cut-o
ff ,th
e vo
ltage
of 1
C d
idn’
t cha
nge,
the
pow
er s
uppl
y ci
rcui
t
was
wor
king
in re
gula
r.
whi
le o
utpu
t circ
uit i
n ov
er c
urre
nt, d
ue to
vol
tage
com
para
tor’s
pin
7 of
ICS1
B, p
in5
of IC
S1A
,pin
9 of
ICS1
C o
utpu
t vol
tage
less
than
vol
tage
com
para
tor’s
pin6
of I
CS1
B, p
in4
of IC
S1A
, pin
8 of
ICS1
C, s
o pi
n1 o
f vol
tage
com
para
tor’s
ICS1
B, p
in2
of IC
S1A
, pin
14 o
f IC
S1C
out
put h
igh
leve
l.
Each
leve
l thr
ough
DS1
4,D
S8,D
S7 c
onne
cted
to e
mitt
er o
f QS4
,als
o th
roug
h R
S40
conn
ecte
d to
Gat
e po
le o
f QS5
,it m
akes
QS5
del
ay tu
rn o
n, th
en Q
S4 tu
rn
on, a
fter t
hat t
he h
igh
leve
l sen
d to
bas
e of
QS2
,so th
at Q
S2 tu
rn o
n, c
olle
ctor
of Q
S2 c
onne
cted
to b
ase
of Q
S1,m
akes
the
QS1
turn
on,
in c
ause
of t
he v
olta
ge o
f
IC3
redu
ctio
n. A
fter t
hat ,
it e
qual
redu
ced
the
+5v
volta
ge o
f IC
3 ,IC
3 st
oppe
d w
orki
ng, t
he se
cond
ary
of IC
3 w
as h
igh
resi
stan
ce ,m
akes
the
Q3
of V
CC
cut
-off,
Q2
cut-o
ff, V
CC
stop
ped
supp
ly p
ower
, it m
eans
no
pow
er to
L65
99,th
e m
ain
pow
er sh
ut d
own.
2 +24V
+18V
+12V
out
put l
oop
sepa
rate
con
nect
ed to
ZS1
ZS2
ZS3,
thro
ugh
DS9
.DS1
0D
S11
conn
ecte
d to
RS1
8,
Alig
nmen
t Pro
cedu
re
Ente
r the
Fie
ld S
ervi
ce m
ode(
can
use
the
IR a
nd p
ress
the
rem
ote
key
“vol
-”to
“0’
, pre
ss m
ute
rem
ote
key
then
pre
ss 9
,7,3
,5 r
emot
e ke
y. P
ress
rig
ht k
ey to
ent
er th
e su
b-m
enu
and
pres
s M
ENU
key
to re
turn
the
mai
n-m
enu)
)
(R
emem
ber:
Kee
p th
e la
tely
Pow
er o
n st
ate;
OFF
: Sta
ndby
afte
r Pow
er o
n)
””
it is
use
d fo
r goi
ng b
ack
the
defa
ult
(it is
the
sour
ce o
f whi
te b
alan
ce a
djus
t tha
t are
TV,
VG
A,C
MP)
it is
use
d fo
r the
adj
ust o
f whi
te b
alan
ce
it is
use
d fo
r the
adj
ust o
f gra
y ba
lanc
e
it is
use
d fo
r the
softw
are
adju
st in
VG
A m
ode
it is
use
d fo
r the
pos
ition
of t
he h
oriz
onta
l and
ver
tical
.H
/V
it is
use
d fo
r the
size
of t
he h
oriz
onta
l and
ver
tical
.
adju
st th
e le
vel o
f vol
ume
adju
st th
e le
vel o
f vol
ume
it is
use
d fo
r the
adj
ust t
he V
olum
e cu
rve
TV/A
V
it is
use
d fo
r the
adj
ust t
he le
vel o
f vol
ume
it is
onl
y us
ed fo
r des
ign
(It i
s the
info
rmat
ion
of th
e pr
oduc
t mod
el, t
he so
ftwar
e ve
rsio
n an
d th
e da
te)
fact
ory
alig
nmen
t pro
cess
It is
the
sour
ce o
f AD
C c
hann
el a
djus
t (ne
ed to
adj
ust Y
pb,p
r and
VG
A st
ate)
The
SW c
an b
e up
date
d on
boa
rd a
nd a
lso
upda
te th
roug
h th
e V
GA
por
tdo
not
nee
d to
ope
n th
e
cabi
net
(pl
ease
inst
all t
he M
T820
2 dr
iver
and
Par
alle
l driv
er f
irst.
Nee
d to
pre
pare
a s
peci
al
cabl
e an
d R
&D
will
supp
ly a
cab
le sa
mpl
e an
d th
e so
ftwar
e dr
iver
s. )
(Firs
t tim
e do
wnl
oad
on b
oard
)
(con
nect
by
cabl
e [th
e to
ol a
nd th
e ca
ble]
bet
wee
n th
e PC
and
th
e X
PA5
on th
e bo
ard
)
(op
en th
e M
T820
2 dr
iver
as b
elow
)
(then
sele
ct “
Bro
wse
” op
en th
e at
tach
ed fi
le (M
T02.
bin)
in th
e lo
catio
n. In
ord
er to
ens
ure
it
can
be b
ette
r upd
ated
you
can
set t
he “
baud
rate
” be
“11
5200
”.)
sele
ct “
Upg
rade
”, if
the
rate
of p
rogr
ess g
et to
100
%,th
e up
date
is fi
nish
ed.
afte
r fin
ishe
d up
date
,pow
er o
ff th
e TV
,then
pow
er o
nat
the
first
tim
e th
at y
ou p
ower
on
the
TV se
t ,th
e di
spla
y w
ill b
e la
ter t
han
norm
al.
upda
te th
roug
h th
e V
GA
por
t
(con
nect
by
cabl
e [th
e to
ol a
nd th
e ca
ble]
bet
wee
n th
e PC
and
the
VG
A p
ort )
(pow
er o
n th
e se
t, pr
ess t
he k
ey o
f the
fact
ory
rem
ote
cont
rolle
r
Afte
r th
at r
epea
t the
pro
cess
3,4
,5,6
, abo
ve ,p
leas
e no
te w
hen
doin
g th
e
proc
ess
6, m
ust e
rase
flas
h fir
st: P
ress
“ER
AS
E F
LAS
H”)
(The
DD
C d
ata
shou
ld b
e pr
ogra
m b
efor
e SM
T, a
nd it
als
o ca
n be
upd
ate
thr
ough
P2
VG
Aw
hen
finis
hed
SMT
. )
(A
fter d
ownl
oad
the
SW, i
t nee
d ab
out 3
0 se
c to
initi
aliz
e th
e EE
prom
, so
mus
t writ
e th
e da
ta
to U
2 be
fore
SM
T )
Blo
ck D
iagr
am
Pow
er b
oard
sign
al fl
ow
EMC
Filte
rci
rcui
t
Brid
gere
ctifi
er
PFC
co
ntro
l ci
rcui
t
PWM
circ
uit
isol
atin
g tra
nsfo
rmer
com
mut
ate
filte
r of
out
put
volta
ge
AC
IN
Mai
n po
wer
supp
ly
+24V
/+12
V
Con
trol
IC L
6563
L659
9
Stan
dby
circ
uit C
ontro
l IC
V
IPER
22
isol
ati
ng trans
form
er
insu
late
d by
ph
oto-
coup
ler
VC
C c
ontro
l cel
l
com
mut
ate
filte
r of
ou
tput
Ove
r cu
rren
t an
d ov
er
volta
ge
prot
ectio
nst
andb
y co
ntro
l circ
uit
PS-O
N
Stan
dby
volta
ge
+5V
SB
Digital board block diagram
Audio
signal MT8202
LCD Panel LVDS
KEY IR
U7 29AL016M90TFI02(FLASH)
POWER
MODEL
12V/AMP12VGND(JP12)
VG
A
U11(D
DC
) AT24C
02
HD
MI
U10(D
DC
)M
24C08
TITMD
S 341A
U8(R
eceiver) M
T8293E U
9(HD
CP)
AT24C08
Y cb cr input.
U2(SCART)4052Audio switch
TCL TUNER /SLG 3
SCART1 Audio input
SCART1\2(AV1\AV2) AV3 Video input
SIF
CV
BS
U2 M24C32 (user data)
SDA\SCL
SCART2 Audio input
AV3 Audio input
U13(4052)Audio switch
HD\VGA Audio input
U12 (A/D) CS5340
U001
YD
A142
8
Audio
U7
(SDR
AM
)
Q1 2N3904
SCART1 PIN20 Video output
TU_CVBS0
indicator light JP9 PIN4U14PI5V330
SCART1 RGB input
YUV/RGB
DTV D200 Q7 2N3904
TESTP2 SCART2 PIN20 Video output
AV_CVBS
Headphone R/L
DDC
SDA
\SCL
YPbPr U18RC4558
AR/ALSCART2Audio output
AVR/L_OUT
Q2\252N3904
SCART1 Audio
output
TU_MONO
Standby control SB-5V(JP12A)
24V/(PANNEL) GND
HV+RGB
RGB
CVBS
DDC
U27(DC-DC) 9583 +5V
KEY
REM
OTE
LED
L\R
A A
B B
C C
D D
E E
44
33
22
11
MT8
202M
1V2 MT8202E (PBGA388) CRT/LCDTV DEMO/VERFICATION BOARD 4 LAYERS
AUIO
IN/O
UT G
NDDI
GIT
AL G
ND
"GN
D N
eed
Very
Str
ong"
4.38
V Th
resh
old
Opt
ion
RES
ET#
CIR
CU
IT
V2
R1=Rds(on)max*Ilimite/200uA = 0.023 * 2A *1.25 /200uA = 184
MOS
fET
and
T1 i
n th
e sa
me side
R1=Rds(on)max*Ilimite/200uA = 0.023 * 4A *1.25/200uA = 368
SC11
02 B
OMR1
184
(2A)
/368
(5A)
*1
D1 M
BRA1
30
*1
D2 M
BR05
20
*1
D3 M
BRD1
035
*1
Q1A,
Q2B
STP4
0NE
*2
C1 1
0uF/
16V
*1
C2,3
,4 2
70uF
/16V
*3
C5 0
.1uF
*1
C7,8
1uF
*2
C10,
11,1
2,13
,14
180u
F/6V *5
T1 4
uH
*1
R2 1
0 08
05
*1
R3,5
1K
0603
*2
R4 2
K 06
03
*1
R6 4
75 0
603
*1
R7 1
27 0
603
*1
R9 3
.9 0
603
*1
R10
2.2
0603
*1
U1 S
C110
2
*1
SC11
04 B
OMD1
LL4
148
*1
D2 M
BRA1
30L
*1
Q1A,
Q2B
STP4
0NE
*2
C1 1
0uF/
16V
*1
C2,3
,4 2
70uF
/16V
*3
C6 ?
*1
C8 1
uF
*1
C9 ?
*1
C15
?
*1
C16
?
*1
C10,
11,1
2,13
,14
180u
F/6V *5
T1 4
uH
*1
R6 5
08 0
603
*1
R7 1
27 0
603
*1
R8 ?
*1
R9 2
.2 0
603
*1
R10
2.2
0603
*1
R11
?
*1
R12
?
*1
R13
?
*1
U2 S
C110
4
*1
Remark:
The components which did not marked the value in
the circuit are all using in SC1104 solution.
Vin-R1*200uA=Vin-Rds(on)*Ilimite
1/2
Iout
Sens
itiv
e
>=15
mil
>=15
mil
2. L
DO
13. L
VDS
/ CRT
/ TT
L O
UT14
. BAC
K LI
GHT
/ KE
YPAD
5. M
T820
2 DI
GIT
AL D
ECO
UPLI
NG
12. C
S433
4 / W
M87
66(8
768)
ADA
C11
. AUD
IO /
VIDE
O IN
CIR
CUIT
4. M
T820
2 AN
ALO
G D
ECO
UPLI
NG
1. I
NDEX
/ PO
WER
/ RE
SET
10. C
S534
0 AD
C &
AV B
OAR
D I/F
15. C
ARD
I/F &
DEB
UG P
ORT
& G
PIO
LIS
T
7. H
DMI I
NPUT
-SiI9
011
/ MT8
293
6. D
DR M
EMO
RY &
FLA
SH
9. V
GA
IN &
PC
AUDI
O IN
8. C
CIR6
56 /
MT5
351
INTE
RFAC
E
3. M
T820
2E P
BGA3
88
Rev
Date
P#
History
Mod
ified
2005
/09/
30TC
L_V1
.0TC
L_V1
.4M
odifi
ed20
06/0
5/25
TTE
SHEN
ZHEN
R&D
CEN
TER
TCL_
V1.5
Mod
ified
2006
/08/
17
2006
-5-2
6YW
X
MT8
202
C
114
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
GN
DG
ND
A
UR
ST#
GN
D
AMP_
GN
D
AMP_
+12V
+12V
GN
DPO
N/O
FF
GN
DP
UR
ST#
+5V
GN
DP
ON
/OFF
SB+5
V
GN
DA
8202
UP3
_0
+12V
+5V
UR
ST#
[1,3
,6,9
]
GN
DA
[3,4
,8,9
,11,
12,1
4]
8202
UP3
_0
+12V
[1,2
,9,1
0,11
,12,
14]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
+12V
5VSB
+12V
GN
DP
GN
DP
GN
DP
GN
DP
GN
DP
SB+5
V
GN
DP
AM
P_G
ND
AMP_
+12V
+12V
GN
DP
GN
DP
AM
P_G
ND
+5V
GN
DP
SB+5
V
H2
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
H1
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
+C
E44.
7uF/
10v/
NC
R51
4N
C
C23
0O
PEN
L59
FB
L68
FB
R50
46.
5K
L67
FB
L66
FB
L65
FB
C22
61.
0uF/
16V
L64
FB
Q19
2N39
04SO
T23/
SMD
/NC
1
32
R50
927
0
R10
4.7K
/NC
C20
7N
C
H3
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
D32
STPS
2L40
U
CB1
960.
1U
R51
3
2.2
D1
1N41
48/S
MD
/NC
L62
FB
Q24 2N
3904
SOT2
3/SM
D
1
32
R50
72.
2K
U1 LM
809M
3-4.
38V
SOT-
23/S
MD
1
23 GND
RESETVCC
D30
LL41
48
CE1
9447
0uF/
25V
JP12
2 3 41
2 3 41
R8
47k/
NC
U27
SC26
02
1 2 3 4 6 7891011121314
5
VCC
PWR
GD
OVP
OC
SET
DR
VH
PGN
DD
RVL
BSTL
BSTH
SEN
SE
VREF
SS/S
HU
T
GN
D
PHAS
E
C19
647
0uF/
16V
CB2
01
0.1u
F
R51
92.
2K
JP7
DIP
12/W
H/P
2.0/
R
1 2
H8
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
1=32=4
SW1
SW4P
/DIP
/FLA
T/N
C
1234
C12
0.1u
FC
0402
/SM
D
R50
81K
L58
FB
CB2
02
0.1U
U29
PHKD
13N
03LT
(N-M
OS)
1 2 3 4
8 7 6 5
S1 G1
S2 G2
D1
D1
D2
D2
R50
510
L60
FB
JP12
A
3x1
W/H
OU
SIN
G R
.A
DIP
12/W
H/P
2.0/
R
1 2 3
CE1
9510
00uF
/10V
R57
10K
CB4
NC
C04
02/S
MD
R50
65.
1K
R52
61K
L63
FB
CB2
060.
1U
H4
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
R9
1k
R51
1O
PEN
R32
410
K/N
C
L69
BCK-
4235
( 10
UH
)
1
2
CB2
050.
1U
C36
0.1u
FC
0402
/SM
D
H5
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
R51
068
0
C84
1uC
0805
/SM
D/N
C
CB2
040.
1UF
H6
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
D31
STPS
2L40
U
C22
5
NC
R51
810
K
R11
100k
CB2
0.1u
F
C70
0.1u
FC
0402
/SM
D
C71 0.1u
FC
0402
/SM
D
L61
FB
CB2
03
0.1
R51
22.
2
CB2
070.
1U
H7
HO
LE/G
ND 2 3 4 5
9 8 7 6
1
2 3 4 5
9 8 7 6
1
A A
B B
C C
D D
E E
44
33
22
11
1.25
x(1+
180/
110)
=3.3
V
STANBY
SB+5
DV33A
DV18A
AV18A
AV33A
Pow
er O
N a
live
sour
ce
1.25
x(1+
150/
270)
=1.9
44V
1.25
x(1+
64.9
/110
)=1.
99V
1.25
x(1+
180/
110)
=3.3
V
1.25
x(1+
150/
270)
=1.9
44V
Modi
fied
by
Bin_
wang
.200
6/01/20
Modi
fied
by
Bin_
wang
.200
6/01/20
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
214
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
ASB3
3A
VFE_
GN
D
VFE_
GN
D
SB18
A
ASB1
8A
VFE_
GN
D
VFE_
GN
D
DAC
VDD
LVD
S_G
ND
LVD
S_G
ND
SB33
A
LVD
S_G
ND
LVD
S_G
ND
AV33
A
DV1
8A
ADC
V33A
SB18
ADC
V18A
VFE_
GN
D
LVD
S_G
ND
ADCV33A
5VSB
VFE_
GN
D1
DV1
8A
+12V
+5VD
V33B
LVD
S_G
ND
[3,4
,14]
VFE_
GN
D[3
,4,1
0,11
]
VFE_
GN
D1
[2,4
,8,9
,10,
12]
+12V
[1,2
,9,1
0,11
,12,
14]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
DV3
3B[7
,8,9
,12,
13,1
4]
SB33
A
DV1
8A
SB18
A
+5V
ASB
18A
+12V
AV1
8AA
DC
V18A
DV3
3B
+5V
AV3
3AA
DC
V33A
SB33
B
DA
CVD
D
ASB
33A
SB33
DV3
3A
SB+5
V
5VSB
U23
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
+C
E17
100U
f/10v
L7FB
L42
FB
U24
AZ1
117/
adj/N
C
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
CB1
970.
1uF
C06
03/S
MD
FBFB
2
R32
527
0 1%
R38
100K
L6FB
+C
E13
100U
f/10v
CB1
80.
1uF
U20
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
+C
E10
4.7u
F / 0
805
R32
615
0 1%
C10
14.
7uF/
10v
C08
05/S
MD
+C
E74.
7uF
/ 080
5
FB18
0
R51
10K
CB7
0.1u
F
+C
E310
0uF/
16v
+C
E11
4.7u
F / 0
805
L5FB
C16
810
0Uf/1
0v
U22
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
CB2
30.
1uF
R88
270
1%
U37
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
U30
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
+C
E108
100U
f/10v
Q6
SI23
07D
SSO
T-23
/SM
D
12
3
GS
D
CB1
30.
1uF
R89
150
1%
CB1
87
0.1u
F
CB1
10.
1uF
C16
710
0Uf/1
0v
CB3
0.1u
FC
0603
/SM
D
U21
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
L4FB
+C
E21
100U
f/10v
U31
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
CB1
70.
1uF
R99
270
1%
CB1
50.
1uF
+C
E14
100u
F/16
v
+C
E110
0uF/
16v
CB9
0.1u
FC
B10
0.1u
F
CB8
0.1u
F
R10
215
0 1%
+C
E109
100U
f/10v
+C
E103
100u
F/16
v
+C
E8
4.7u
F / 0
805
CB2
4
0.1u
F
CE1
54.
7uF/
10v
C08
05/S
MD
+C
E94.
7uF
/ 080
5
L2 FB
+C
E104
100u
F/16
v
FB19
0
L8FB
A A
B B
C C
D D
E E
44
33
22
11
V2
V2
RS-
232
SYST
EM E
EPRO
M
Modi
fied
by
Bin_
wang
.200
6/01/20
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
5YW
X
MT8
202
C
314
Mon
day,
Mar
ch 1
9, 2
007
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
A_C
LK
A_D
QM
[0..1
]A_
BA[0
..1]
A_W
E#
A_C
KEA_
CLK
#
A_D
Q[0
..31]
A_R
A[0.
.11]
A_C
AS#
A_D
QS[
0..3
]
A_C
S#A_
RAS
#
F_A[
8..2
1]
F_O
E#
F_D
[0..7
]
IOW
R#
IOC
E#
AP[0
..7]
AN[0
..7]
CLK
2-
CLK
1-C
LK2+
CLK
1+
AOLR
CK
IOSC
L
AOM
CLK
IOSD
A
ADIN
AOBC
LK
AOSD
ATA1
INT0
#
PWM
0PW
M1
VI[0
..23]
SB33
B
XTAL
I
PR0-
HD
MIS
D0
HD
MIB
CLK
HD
MIL
RC
K
HD
MIM
CLK
HD
MIS
D1
HD
MIS
D2
HD
MIS
D3
LVD
S_G
ND
SB18
A
PLLV
DD
2
AAD
CVD
D
LVD
DA
DAC
VDD
C
DAC
VDD
A
VPLL
VDD
1
AVD
D_V
AD1
PLLV
DD
3
AVD
D_V
AD0
XTAL
VDD
LVD
S_G
ND
ADC
VDD
VPLL
VDD
2
AVD
D_V
FE1
PLLV
DD
1
ADAC
VDD
DAC
VDD
B
AVD
D_V
FE0
AUD
IO_G
ND
UR
ST#
UTX
D
UR
XDR
XD
TXD
GPI
O2
GPI
O3
FCLK
FCM
DFD
ATG
PIO
10
8202
UP3
_1G
PIO
13G
PIO
14G
PIO
15G
PIO
16G
PIO
17G
PIO
18
DV2
5A
SDV2
5A
27M
HZ
HD
MIH
SYN
CH
DM
IVSY
NC
HD
MID
EH
DM
IOD
CK
SDA0
CC
IR_V
[0..7
]
CC
IR_V
CLK
ADC
_IN
2
ADC
_IN
1
ADC
_IN
0
LVD
DC
LVD
DB
TEST
P4TE
STN
4
TEST
P3TE
STN
3
TEST
P2
HD
MIC
EN
VREF
IRDE_
SOG
SCAR
T_FB
RXD
TXD
AVIC
M
PWM
2VR
EF
DAC
FSSC
L0
AAD
CVS
S
REF
PR
EFN
SCL
SYSR
OM
WP
SDA
ICE
VFE_GND1
GN
D
TESTP2
VFE_GND1
VI23
VI11
VI1
DV2
5A
A_C
LK
LVD
S_G
ND
A_DQ2
A_DQ4
GN
D
IOA1
GPIO16
GPIO10
USB_IR_EN
A_R
A9
A_D
Q19
A_R
A4
A_R
A8
AN7
F_A1
7
UWR#
URXD
GND
VFE_GND
TESTN2
REFP
CVBS0
Y0-
BLUE+VFE_GND
CCIR_V4
GN
D
A_C
AS#D
V33A
A_D
QS2
A_D
Q24
A_D
Q28
F_D
5
IOA6
F_A12
TESTP3
AVDD_VAD0
CVBS3
CVBS1
SDA0
CCIR_V1
HDMIMCLK
VI14
A_D
Q13
A_BA
1
F_A1
3
VPLL
VDD
1
A_R
A2
GN
D
A_C
S#
A_W
E#
VPLL
VDD
2
AP0
XTAL
I
F_D
2
IOC
E#
F_A1
4
SB18
A
ADIN
AOMCLK
GND
GN
D
AR
SC0
VFE_GND
VI22
DV1
8A
IOA2
DV25A
A_D
Q27
CLK
1-
AN6
ADC
_IN
0
A_R
A0
A_D
Q20
LVD
DA
AN1
DAC
VDD
A
A_D
QM
1
ADC
_IN
2
8202UP3_4
GNDGND
REFN
PB1+Y1-
Y0+
GND
GND
HDMISD0
VI16
VI2
GPIO18
F_A11
A_DQ3
8202
UP3
_5
A_R
A1
GND
A_DQ11
A_DQ12
SB18
A
LVD
S_G
ND
ADC
_IN
4
GPIO6
A_R
A7
AP6
GN
D
GN
D
GN
D
LVDS_GND
ADACVDD
PR0+
VGAVSYNC#
VI18
VI0
A_R
AS#
GN
D
IOA4
AOSDATA3
GND
DAC
VREF
AP5
GND
VFE_GND
VFE_GND1
AADCVSS
GN
D
Y1+
SCL0
CCIR_V3
HDMISD2
VI12
VI7
DE_
SOG
DAC
FS
A_DQ5
PLLV
DD
3
A_DQ8
PWM
0
LVD
S_G
ND
A_D
Q21
ADC
_IN
1
LVD
DC
AP1
F_D
4
F_A18
IOA5
GND
GPIO15
DV18A
GPIO4
A_R
A5SB
33A
AP2
UTXD
GNDVFE_GND1
GN
D
GN
D
AVICM
MPX1
CVBS2
SOY1
VI20DV33A
VI13
VI5
FDATFCMD
LVD
S_G
ND
PLLV
DD
2
GN
D
A_D
Q22
F_A20
GPIO14IO
A0
XTAL
O
GN
D
AADCVSS
VFE_GND1
SY1
DV18A
VI6
27M
HZ
GPIO12
GND
A_DQ6
GPIO2
A_DQ10
A_DQS1
F_A1
5
GN
D
AOBCK-GPIO8
GND
AP4
F_D
7
GND
ACENT
PR1+
CCIR_V5
SCL1
LVD
S_G
ND
A_BA
0
A_R
A3
A_C
LK#
A_D
Q14
A_D
Q30
A_D
Q23SD
V25A
F_O
E#
INT0#
GN
D
LVD
S_G
ND
DV3
3A
GN
D
AUDIO_GNDAL
AVDD_VFE0
PR1-
PB1-
BLUE-
CCIR_V2
HDMISD3
VI15
HD
MIO
DC
K
A_D
QS3
A_D
Q17
AP3
A_R
A10
GREEN+
A_D
Q26
F_D
0
MPX2
SY0
AVDD_VAD1
SCART_FB
A_DQM0
GN
D
VREF
A_D
Q31
AN5
A_D
Q25 SD
V25A
ADC
_IN
3
IOA7F_A8
F_A1
6
LRCK-GPIO7
AOBCLK
DV2
5A
VFE_GND1
SC1
PR0-
AVDD_VFE1
CCIR_V0
HDMISD1
HDMIBCLK
VI19
GN
D
VI4
HD
MIH
SYN
CH
DM
IVSY
NC
GN
D
DAC
VDD
C
F_A21
LVD
S_G
ND
PWM
1
GND
A_DQ1
A_DQ7
AN0
DAC
VDD
B
CLK
2+
FCLK
IR
A_D
Q16
PB0-
RED-RED+
CCIR_V7
CCIR_VCLK
VI17
DV2
5A
GPIO17
A_DQS0
A_DQ9
TEST
N4
A_DQ0
DV25A
XTAL
O
LVD
S_G
ND
GPIO5
AOSDATA1
IOA3
HSY
NC
LVD
DB
AADCVDD
GN
D
VI9
VI8
HD
MIC
EN
8202
UP3
_1
CLK
1+
A_R
A11
IOWR#
AN2
DV33A
GND
F_D
1
A_R
A6
TESTN3
VI21
VI10
VI3
AOLRCK
A_C
KE
LVD
S_G
ND
CLK
2-
LVD
S_G
ND
DV1
8A
IOSCL
A_D
Q18SD
V25A
IOSDA
F_D
3
GPIO13
AOMCLK-GPIO9
GPIO3
URST#
VFE_
GN
DD
V18A
SDA1
AN4
PLLV
DD
1
PB0+
SOY0
VGASOG
VGAHSYNC#
CCIR_V6
HDMILRCK
HD
MID
E DV1
8A
F_D
6
AN3
A_D
Q15
XTAL
VDD
AP7
A_D
Q29
GREEN-
F_A19
SB33A
F_A9
SY0
RED
-
Y1-
MPX
2
BLU
E-
CVB
S2INT0
#
PB1+
AR GR
EEN
-
Y0+
PB0-
CVB
S3
SOY1
VGAV
SYN
C#
SOY0
ICE
ACEN
T
PR1+
PB1-
VGAH
SYN
C#
PWM
2VR
EF
RED
+
RXD C
VBS0
ADC
VDD
TXD PR
0+
F_A10
LVD
S_G
ND
PR1-
BLU
E+
AL Y0-
Y1+
PB0+
TEST
P4
TESTN1
MPX
1
CVB
S1
SC0
VSYN
C
VGAS
OG
DV18A
TESTP1
GR
EEN
+
GPI
O4
SDA1
GPI
O5
SCL1
IOA[
0..7
]
C6
SDA
SCL
GPI
O6
8202
UP3
_582
02U
P3_4
SB33
A
8202
UP3
_0
8202
UP3
_0
ADC
_IN
3AD
C_I
N4
VFE_
GN
D
VFE_
GN
D1
VFE_
GN
D1
GPIO11
SC1
SY1
USB
_IR
_EN
GPI
O11
GPI
O12
AOM
CLK
-GPI
O9
AOBC
K-G
PIO
8LR
CK-
GPI
O7
AOSD
ATA3
C6
A_C
KE[7
]
A_C
AS#
[7]
A_D
QS[
0..3
][7
]
A_C
LK[7
]
A_W
E#[7
]
A_BA
[0..1
][7
]A_
RA[
0..1
1][7
]
A_C
S#[7
]
A_D
Q[0
..31]
[7]
A_R
AS#
[7]
A_D
QM
[0..1
][7
]
A_C
LK#
[7]
F_D
[0..7
][6
,7]
F_O
E#[7
]
F_A[
8..2
1][6
,7]
IOC
E#[6
]IO
WR
#[6
]
AP[0
..7]
[14]
AN[0
..7]
[14]
CLK
1+[1
4]
CLK
2+[1
4]C
LK2-
[14]
CLK
1-[1
4]
IOSD
A[6
]IO
SCL
[6]
AOBC
LK[1
1,13
]AO
MC
LK[1
1,13
]
ADIN
[11,
16]
AOLR
CK
[11,
13]
AOSD
ATA1
[13]
INT0
#[6
,8]
PWM
0[1
5]PW
M1
[15]
VI[0
..23]
[8,9
]
PR0-
[12]
HD
MIM
CLK
[8,9
]H
DM
IBC
LK[8
,9]
HD
MIL
RC
K[8
,9]
HD
MIS
D0
[8,9
]
LVD
DA
[4]
AVD
D_V
FE0
[4]
ADAC
VDD
[4]
ADC
VDD
[4]
XTAL
VDD
[4]
PLLV
DD
1[4
]
AVD
D_V
AD0
[4]
PLLV
DD
2[4
]
DAC
VDD
A[4
]
VPLL
VDD
1[4
]
VPLL
VDD
2[4
]
PLLV
DD
3[4
]
AVD
D_V
AD1
[4]
AAD
CVD
D[4
]
AVD
D_V
FE1
[4]
DAC
VDD
C[4
]
LVD
S_G
ND
[2,4
,14]
DAC
VDD
B[4
]
AUD
IO_G
ND
[1,4
,10,
11,1
2,13
]
UR
ST#
[1,6
,9,1
5]
GPI
O2
[14]
GPI
O3
[13]
FCLK
[11]
FCM
D[1
1]FD
AT[1
1]G
PIO
10[1
1]
8202
UP3
_1[1
]G
PIO
13G
PIO
14G
PIO
15G
PIO
16G
PIO
17[8
]G
PIO
18[8
]
DV2
5A[7
]
SDV2
5A[7
]
27M
HZ
[8]
HD
MIS
D1
[8,9
]H
DM
ISD
2[8
,9]
HD
MIS
D3
[8,9
]
HD
MIH
SYN
C[8
,9]
HD
MIV
SYN
C[8
,9]
HD
MIO
DC
K[8
,9]
HD
MID
E[8
,9]
SDA0
[9,1
6]
CC
IR_V
[0..7
][9
]
CC
IR_V
CLK
[9]
ADC
_IN
1[1
1]
ADC
_IN
2[1
1,15
]
ADC
_IN
0[1
1]
LVD
DC
[4]
LVD
DB
[4]
TEST
P4[4
]TE
STN
4[4
]
TEST
P3[4
]TE
STN
3[4
]
TEST
P2[1
1]
HD
MIC
EN[8
]
VREF
[7]
IR[3
,10,
13]
DE_
SOG
[8]
SCAR
T_FB
[11]
RXD
[9]
TXD
[9]
AVIC
M[4
]
PWM
2VR
EF[4
]
DAC
FS[4
]
SCL0
[11,
16]
AAD
CVS
S[1
,4,8
,9,1
0,11
,12,
14]
REF
P[4
]R
EFN
[4]
PB1-
[12]
BLU
E-[1
0]
CVB
S3[1
2]
VGAH
SYN
C#
[10]
Y1-
[12]
CVB
S0[1
2]
Y0+
[12]
SOY0
[12]
PR1+
[12]
RED
-[1
0]
PR1-
[12]
RED
+[1
0]
VGAV
SYN
C#
[10]
CVB
S2[1
2]
SY0
[12]
ACEN
T
SOY1
[12]
BLU
E+[1
0]
AR[1
3]
MPX
2[1
2]
VGAS
OG
[10]
PB1+
[12]
CVB
S1[1
2]
PB0-
[12]
Y0-
[12]
SC0
[12]
Y1+
[12]
AL[1
3]
GR
EEN
+[1
0]G
REE
N-
[10]
MPX
1[1
2]
PB0+
[12]
PR0+
[12]
SDA1
[9,1
6]
GPI
O5
SCL1
[9,1
6]
IOA[
0..7
][3
,6]
SDA
[1,6
,11]
SCL
[1,6
,11]
GPI
O6
8202
UP3
_482
02U
P3_5
8202
UP3
_0
ADC
_IN
3[1
2]
ADC
_IN
4[1
2]
VFE_
GN
D[2
,4,8
,9,1
0,11
,12,
14]
VFE_
GN
D1
[2,4
,8,9
,10,
12]
VFE_
GN
D1
[2,4
,8,9
,10,
12]
SC1
[10,
14]
SY1
[10,
14]
USB
_IR
_EN
[3,1
0]
GPI
O11
[3,8
]
GPI
O12
[3,9
]
AOSD
ATA3
[3,1
1]AO
MC
LK-G
PIO
9[3,
11]
LRC
K-G
PIO
7[3
,11]
AOBC
K-G
PIO
8[3
,11]
C6
[3,1
2]
SB33
BSB
18A
DV1
8AD
V33A
SB33
A
SB33
B
SB33
BSB
33B
SB33
B
TP13 TP
99
TP81
TP6
TP16
8
TP10
R39
0
R36
10KR
1320
K
TP7
TP20
0
C1
16pF
C2
16pF
U2
EEPR
OM
24C
32SO
P8/S
MD
1 2 3 45678
NC
NC
NC
GN
DSD
ASC
LW
PVC
C
R40
0
JP1
4x1
W/H
OU
SIN
GD
IP4/
W/H
/P2.
0
1 2 3 4
TP31
TP80
TP92
X1 27M
Hz
TP12
CB5
0.1u
F
TP2
TP79
TP91
TP23
TP83
R26
4.7K
R15
10K/
NC
TP14
MT8202
SOCKET
U3
MT8
202
BGA3
88/S
OC
KET
C9
U4M3M4M1
K1
B6 A6 C6
D6
C3
C2
C4
C10
D12B16
A10
C8
D5
A14
R13
AF10
AC11
AD11
AC12
AE11
AF11
AF12
AE10
AC7
K2
D3
L1L2L3L4
N1N4M11P1P2P3P4N12R1
R4
R2
T1
T4U1U2U3V1
V3V2
V4
W3W4Y1Y2
L12
F3
M12
F2
D2
H2H3
H4G1
K3
G3
C1B5B3 E4
G2H1
A5A4 D1A3A2B2
G4
B4
AA1
D18 A18
D20A21
AE13
C18
T26
C20 B20
A23
C11
AC16
AC15
AD16
AC14
AD15
AF16
T14
AE15
AD14
AE14
J1
A8A9B13
D16
C16A17
C17
C12A13
A15
D9 B9D
13A22
A20
C19
D19
R14
AF14
AF13
AD13
T13
D7K4B8B22
AD17
AC17
AF17
AC13
AE17
AE12
AC1
AC4
AD5AE1AF1
AA2
AE5
AF4
AE4
AF3R12AE3AF2
T25
AD3P12
AC8
AF7
AF6
R11
AF5
AB3AB2AB1
AE8
AD8
AA4
AF9
AF8
AD9
T11
N11
AD7
AC18
C21 B21
A19
D21 B19
B18
B14
B12
B17
A12
D10
D11
D14
D15B15
AC2
F1
L11
C14 B10
B11
D17
C15
F4
B1
J2
AD12
AC9
AE16
AF15
AD10
AE9
AC10
AE2
AD1
AC5
W1
Y3
R3
T2
D4
C7 E3
T12
AB4
A16
A11
AC6
AE7
AE6
M2
B7
E1
N3
AD2
AC3
P11
Y4
T3
AD6
W2
AD4
AD18
AE18
AF18
AF19
AD19
AC19
AF20
AE20
AD20
AD21
AF21
AE19
AE21
AF22
AC21
AC22
AE22
AD22
R15
AF23
T15
AE23
AD23
AF24
AE24
AD24
AF25
AF26AE25AE26AC20AD25AC23AD26AC25AC26AB26AB25AC24AA25AA26AA23AA24
AB24T16W23Y26Y25Y24Y23R16W26W25W24V24V23U23U24V26V25N24U25U26T24
R25R26R23R24P23M24P24P25P26N25N26M25M26L24L25L26K25K26J25J26L23G26G25F26F25H23
G23G24
D25D26
J23E26E25
F24F23E24B26C26D24C25B25C24B24A24A26A25D23C23D22
C22
C13 A7
B23
D8
AB23
P13
N16
N15
N14
N13
M16
P16
P15
P14
A1 C5 J3 J4
E23H24H25H26K23M23N23
AA3
M15
L16
L13
E2
M13
L14L15
M14
J24
K24
T23
N2
A5P
DVDD18RXDTXDAOMCLK
WR#
VSYN
CO
HSY
NC
OG
PIO
GPI
OA1
7IO
A0AD
7
A6P
A7N
VREF
A2P
A4P
DVD
D33
A
LVSS
C
DVS
S25
RA8
RA7
RA6
DQ
16
RA5
RA4
DQ
19
RA9
DVD
D25
_CLK
RD#
IOA3
INT0PRST#UP3_4IR
AOBCKLINDVSS18AOSDATA0/GPIOAOSDATA1/GPIOAOSDATA2/GPIOAOSDATA3/GPIODVSS33GPIO0/AOSDATA4
GPIO3
GPIO1/AOSDATA5
FCICLK/GPIO
GPIO4GPIO5/TXDGPIO6/RXDDVDD18GPIO7
GPIO9GPIO8
GPIO10
GPIO13GPIO14GPIO15GPIO16
DVS
S18
HIGHA1
DVSS18
IOA20
A16
IOA6IOA5
DVDD33AIOA4
DVD
D18
A
IOA18
IOA1
IOO
E#
AD3
HIG
HA6
HIGHA0IOA7
IOC
S#
AD0
HIG
HA7
AD2
AD4
AD5
IOA19
AD1
SDA
ADC
VDD
BADIN
4/G
PIO
XTAL
I
DQ
22
PWM
2VR
EF
GN
ADIN
3/G
PIO
ADIN
2/G
PIO
PLLV
SS3
CK2
PD
Q29
DVD
D25
OPT
DQ
28
DVD
D25
OPT
DVD
D25
OPT
DQ
26D
VSS2
5
DQ
25D
Q24
DQ
M1
IOALE
A0P
A1P
LVD
DC
DAC
VDD
B
DAC
VDD
AG D
ACVS
SB
A7P
VPLL
VDD
2
TP4
A5N
A1N
LVD
DA
XTAL
VDD
XTAL
O
ADIN
1/G
PIO
DAC
VSSA
DVS
S18
DQ
S2D
Q23
DQ
21D
VSS2
5
GPI
OD
VDD
18A
A0N
PLLV
SS2
GPI
O/P
WM
0D
VDD
33I
DQ
30
DQ
20
DQ
31
DQ
18
DQ4
DQ7
DVDD25DQS1DQ8
SCL
RW
E#D
Q15
DQ
14
DQ12DVSS18DQ11DQ10
GP
RVREFDVSS18
DVD
D18
RA1
0
RC
S#
DVS
S25
CAS
#
DQ2DQ1DQ0
RA1
RA0
DVDD33
RC
LKB
RA2
RA3
DVS
S25
DVSS25
BA0
GPI
O/P
WM
1
PLLV
DD
2
PLLV
DD
3
XTAL
VSS
ADC
VSS
ADIN
0/G
PIO
SVM
LVSS
BA3
N
R A3P
A6N
CK2
N
VPLL
VSS
VPLL
VDD
1TN
4
DQ5
IOA21
DVS
S33
LVSS
A
A2N
CK1
N
DAC
VSSC
DAC
VDD
C
HIGHA2
AD6
IOWR#
DQ
17
DVD
D18
DQ
27
DQ
S3
RA1
1
RC
LK
CKE
DQ9
DQS0
DVDD25
GPIO11
GPIO17
GPIO2
FCICMD/GPIO
IOA2
UP3
_5
HIG
HA5
DVS
S18
DQ3
FS CK1
P
DVD
D25
BA1
RAS
#
ICE
UP3
_1
HIGHA3
AOLRCK
DQM0
DQ6
DVSS25
GPIO18
FCIDAT/GPIO
DVD
D25
GPIO12
DQ
13
OU
T_27
MH
Z/G
PIO
DE_
SOG
/GPI
OC
EN_D
VI/G
PIO
VSYN
C_D
VIH
SYN
C_D
VID
E_D
VIVI0
VI1
VI2
VI5
VI3
VCLK
_DVIVI4
VI7
VI6
DVD
D18VI
8VI
9D
VSS3
3IVI
10D
VSS1
8VI
11VI
12VI
13VI
14VI
15VI
16
VI17VI18VI19
DVDD33VI20
DVDD18VI21VI22VI23
HDMIMCLK/GPIOHDMIBCLK/GPIOHDMILRCK/GPIO
HDMISD0/GPIOHDMISD1/GPIOHDMISD2/GPIOHDMISD3/GPIO
SCL1DVSS33
CCIR_VCLK/GPIOCCIR_V0/GPIOCCIR_V1/GPIOCCIR_V2/GPIOCCIR_V3/GPIO
DVSS18CCIR_V4/GPIOCCIR_V5/GPIOCCIR_V6/GPIOCCIR_V7/GPIO
SDA0SCL0
FAST_BLANKHSYNCVSYNC
AVSS_VFE1BPBN
SOG
RPRN
AVDD_VFE1TN1TP1
AVSS_VAD1SOY0
Y0PY0N
PB0PPB0NPR0PPR0NSOY1
Y1PY1N
PB1PPB1NPR1PPR1N
AVDD_VAD1SC1SY1SC0SY0
AVSS_VFE0
AVSS_VAD0REFN
CVBS1CVBS0
AVDD_VFE0CVBS3CVBS2
REFPAVDD_VAD0
AADCVDDSIFAF
AADCVSSTN2TP2
ADACVDDACENT/AOSDAT2
AVICMAR/AOSDAT1AL/AOSDAT0
ADACVSSTP3TN3
PLLV
DD
1
LVD
DB
UP3
_0
PLLVSS1
A4N
SDA1
DG
ND
/BAL
LD
GN
D/B
ALL
DG
ND
/BAL
LD
GN
D/B
ALL
DG
ND
/BAL
LD
GN
D/B
ALL
DG
ND
/BAL
LD
GN
D/B
ALL
DG
ND
/BAL
L
NC
BAL
LN
C B
ALL
NC
BAL
LN
C B
ALL
AADCVSSVFE_GND1VFE_GND1VFE_GND1VFE_GND1
VFE_GNDVFE_GND
NC
BAL
L
DGND/BALL
DGND/BALL
DGND/BALL
HIGHA4
DGND/BALL
DGND/BALLDGND/BALL
DGND/BALL
NC
BAL
LN
C B
ALL
NC
BAL
L
NC
BAL
L
TP3
TP90
Q4
2N39
04SO
T23/
SMD
1
32
R6
1K
TP11
TP94
TP93
TP4
TP95
TP88
TP85
TP89
R14
10K
TP10
0
R35
10K
TP5
TP10
1
TP10
5
R34
100k
TP10
2TP
103
TP10
4
A A
B B
C C
D D
E E
44
33
22
11
NO
RM
AL
VID
EO D
AC
PO
WER
STA
ND
BY
AN
ALO
G P
OW
ER
NO
RM
AL
AU
DIO
AD
C /
DA
C P
OW
ER
NO
RM
AL
VID
EO A
DC
PO
WER
NO
RM
AL
AN
ALO
G P
OW
ER
NO
RM
AL
VID
EO D
AC
PO
WER
V2
V2
CLOS
E TO
820
2 PIN
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
414
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
DAC
FS
TEST
P3TE
STN
3
LVD
DB
PWM
2VR
EF
ADC
VDD
AVIC
M
DAC
FS
DAC
VDD
A
DAC
VDD
B
DAC
VDD
C
ADAC
VDD
AAD
CVD
D
AVD
D_V
FE0
AVD
D_V
AD0
AVD
D_V
FE1
AVD
D_V
AD1
PLLV
DD
1
PLLV
DD
2
PLLV
DD
3
VPLL
VDD
1
VPLL
VDD
2
PWM
2VR
EF
PLLV
DD
1
PLLV
DD
1
VPLL
VDD
1
VPLL
VDD
1
XTAL
VDD
LVD
DA
LVD
DB
LVD
DC
AVD
D_V
FE0
AVD
D_V
AD0
AAD
CVD
D
ADAC
VDD
VPLL
VDD
2
LVD
DA
AVD
D_V
AD1
AVD
D_V
FE1
PLLV
DD
1
PLLV
DD
2
PLLV
DD
3
XTAL
VDD
VPLL
VDD
1
DAC
VDD
A
DAC
VDD
B
DAC
VDD
C
AVIC
M
TEST
N3
TEST
P4
TEST
N4
LVD
DC
TEST
P4TE
STN
4
AUD
IO_G
ND
VFE_
GN
D
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
AAD
CVS
S
AUD
IO_G
ND
LVD
S_G
ND
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D
VFE_
GN
D
LVD
S_G
ND
AUD
IO_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
TEST
P3
AAD
CVS
S
VFE_
GN
D1
AAD
CVS
SG
ND
A
LVD
S_G
ND
AAD
CVS
S
AUD
IO_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
LVD
S_G
ND
VFE_
GN
D
VFE_
GN
D1
REF
PR
EFN
REF
N
VFE_
GN
D1
VFE_
GN
D1
REF
P
VFE_
GN
D
VFE_
GN
D
VFE_
GN
D1
VFE_
GN
D1
LVD
S_G
ND
LVD
S_G
ND
GN
DA
VFE_
GN
D1
VFE_
GN
D
AAD
CVS
S
AUD
IO_G
ND
VFE_
GN
D
ADC
VDD
AAD
CVS
SVF
E_G
ND
+5V
TEST
P3[3
]TE
STN
3[3
]
LVD
DB
[3]
PWM
2VR
EF[3
]
ADC
VDD
[3]
AVIC
M[3
]
DAC
FS[3
]
AVD
D_V
FE0
[3]
AVD
D_V
AD0
[3]
AAD
CVD
D[3
]
ADAC
VDD
[3]
VPLL
VDD
2[3
]
LVD
DA
[3]
AVD
D_V
AD1
[3]
AVD
D_V
FE1
[3]
PLLV
DD
1[3
]
PLLV
DD
2[3
]
PLLV
DD
3[3
]
XTAL
VDD
[3]
VPLL
VDD
1[3
]
DAC
VDD
A[3
]
DAC
VDD
B[3
]
DAC
VDD
C[3
]
LVD
DC
[3]
TEST
P4[3
]TE
STN
4[3
]
VFE_
GN
D[2
,3,1
0,11
]
LVD
S_G
ND
[2,3
,14]
AUD
IO_G
ND
[1,3
,10,
11,1
2,13
]
AAD
CVS
S[1
,3,1
0,11
,12,
13]
VFE_
GN
D1
[2,3
,11,
12]
REF
P[3
]R
EFN
[3]
GN
DA
[1,3
,10,
11,1
2,13
]
AAD
CVS
S[1
,3,8
,9,1
0,11
,12,
14]
VFE_
GN
D[2
,3,8
,9,1
0,11
,12,
14]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]A
SB18
A
ASB
33A
AD
CV3
3A
AD
CV3
3A
ASB
18A
AV1
8A
AV3
3A
AD
CV1
8A
AV3
3A
AD
CV3
3A
DA
CVD
D
+5V
L15
150u
HL/
IND
/DIP
/P10
.0
TP15
C26
4.7u
F
FB11
FB
CB3
81u
F
R42
820
C50
4.7u
F/10
vC
0805
/SM
D
C25
4.7u
F
C13
4.7u
F
CB2
50.
1uF
CB2
70.
1uF
C04
02/S
MD
CB2
90.
1uF
C04
02/S
MD
C14
1uF
C18
4.7u
F
TP17
+C
E28
4.7u
F/10
V
L13
FB
FB13
FBC
234.
7uF
CB4
31u
F
C51
4.7u
F/10
vC
0805
/SM
D
+C
E12
10uF
/25v
CB3
11u
F
FB6
FBBE
AD/S
MD
/060
3
CB4
70.
1uF
C04
02/S
MD
FB4
FB
+C
E24
4.7u
F/10
V
C16
4.7u
F
+C
E31
4.7u
F/10
V
CB3
90.
1uF
C04
02/S
MD
R45
49.9
1%
CB3
60.
1uF
C04
02/S
MD
+C
E35
4.7u
F/10
V
C17
30.
1uF
C04
02/S
MD
C21
4.7u
F
C24
4.7u
F
C9
4.7u
F
C17
4.7u
F
CB4
40.
1uF
C04
02/S
MD
CB2
60.
1uF
C04
02/S
MD
+C
E23
4.7u
F/10
V
C15
4.7u
F
TP24
TP27
C20
1uF
CB3
70.
1uF
C04
02/S
MD
+C
E25
4.7u
F/16
V
+C
E29
4.7u
F/10
V
C7
4.7u
F
+C
E36
220u
F/16
V
CB3
20.
1uF
C04
02/S
MD
R43
49.9
1%
C6
1uF
C17
40.
01uF
C04
02/S
MD
C11
4.7u
F
L12
FB
C19
4.7u
F
R46
49.9
1%
C27
1uF
+C
E16
4.7u
F/16
v
CB4
00.
1uF
C04
02/S
MD
CB3
51u
F
L14
150u
HL/
IND
/DIP
/P10
.0
FB8
FBBE
AD/S
MD
/060
3
CB4
80.
1uF
C04
02/S
MD
CB3
40.
1uF
C04
02/S
MD
C8
0.1u
FC
0402
/SM
D
C5
4.7u
F
FB7
FB
CB3
00.
1uF
C04
02/S
MD
FB15
FB
C3
10uF
/10v
C08
05/S
MD
TP8
C28
1uF
CB4
20.
1uF
C04
02/S
MD
FB5
FBBE
AD/S
MD
/060
3
C4
1uF
TP18
FB10
FBBE
AD/S
MD
/060
3
CB4
10.
1uF
C04
02/S
MD
+C
E34
220u
F/16
V
CB3
30.
1uF
C04
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4.7u
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E30
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TP9
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C04
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1%
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E27
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A A
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44
33
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MT8
202
DIG
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2005
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Title
Size
Doc
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t Num
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Rev
Dat
e:Sh
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of
SB18
A
SB33
ASB
18A
5VSB
DV1
8A
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50.
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02/S
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E38
4.7u
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A A
B B
C C
D D
E E
44
33
22
11
TSOP 48 pin
VREF
DEC
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PLIN
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CLOS
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820
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V2
Tan
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<Doc
>YW
X
2006
-5-2
6
C
614
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
A_R
A[0.
.11]
A_BA
[0..1
]
A_C
LK
A_C
KE
A_R
AS#
A_C
S#
A_W
E#A_
CAS
#
A_D
QM
[0..1
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DQ
[0..3
1]
F_D
[0..7
]
F_O
E#
A_D
QS[
0..3
]
A_C
LK#
VREF
F_D
3
F_A1
4
F_A2
0
F_A1
7
IOA2
IOA3
F_A9
IOA7
F_A2
1
F_D
4
F_A8
IOA0
IOA5
F_D
6
F_D
1
F_A1
3
IOA4
F_A1
0
IOA6
F_A1
8
IOA1
F_D
2
F_D
5
F_A1
6F_
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F_A1
9
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F_O
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F_D
0
F_D
7
F_A[
8..2
1]
FLAS
HVC
C
D1V
25
D1V
25
D1V
25
D1V
25
D1V
25
VREF
VREF
A_D
Q19
A_C
LK
A_D
Q17
D_C
LK
D_D
Q14
D_R
A6
D_D
Q23
A_D
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D_D
Q20
D_D
QS1
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1
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D_D
Q17
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A3
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1
D_D
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D_C
KE
D_D
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D_D
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A_R
A2
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0
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0
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A_R
A3
D_R
A2
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A3
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D_D
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A_BA
1
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A_D
Q21
D_C
LK#
D_C
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D_D
Q14
D_D
QM
1
D_D
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Q22
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A_R
A8
D_D
Q22
A_D
Q24
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D_D
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A_D
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A_D
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D_D
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A_D
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D_C
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D_D
QS2
D_D
Q24
D_D
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A_R
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A_R
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0
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1
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A_D
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D_D
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A_R
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0
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A_R
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DV2
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VREF
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3B
A_R
A[0.
.11]
[3]
A_BA
[0..1
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]
A_C
LK[3
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A_C
KE[3
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A_R
AS#
[3]
A_C
S#[3
]
A_W
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A_D
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[0..3
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F_D
[0..7
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,6]
F_O
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A_D
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A_C
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[1,2
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11,1
2,13
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SB33
B
SB33
B
SB33
B
DV2
5B
SB33
B
D1V
25
VREF
DV2
5B
VREF
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5B
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78
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78
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25 24 23 22 21 20 19 18 8 9 28
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6-5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VDD
DQ
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8Mx1
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VDD
DQ
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DQ
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NC
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VREF
VSS
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M CK
CK
CKE N
CA1
2A1
1 A9 A8 A7 A6 A5 A4VS
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CB8
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CB1
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C47 3300
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7
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CB8
10.
1uF
CB1
050.
1uF
A A
B B
C C
D D
E E
44
33
22
11
NC i
f AV
CC18
fro
m re
gulator
SPDI
F OU
TOUT
V2
V2
V2
V2
V2
CM2021
Modi
fied
by
Bin_
wang
.200
6/01/20
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6<R
evC
ode>
MT8
202
C
714
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
CLO
CK+
GPI
O17
HD
MIH
SYN
CH
DM
IVSY
NC
HD
MID
E
SCL
SDA
GPI
O18
PLU
GPW
R
9993
_SD
A
9993
_SC
L
INT0
#
DE_
SOG
VI[0
..23]
DAT
A2+
DAT
A0+ D
ATA0
-
HD
MIO
DC
K
DAT
A2-
DAT
A1+
DAT
A1-
HD
MI_
DD
C_S
DA
AVC
C18
AVC
C18
XTLI
VCC
18
27M
HZ
27M
HZ
HD
MIS
D0
HD
MIB
CLK
HD
MIL
RC
K
HD
MIM
CLK
HD
MIS
D1
HD
MIS
D2
HD
MIS
D3
CO
AXO
UT
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VI8
VI9
VI10
VI11
VI12
VI13
VI14
VI15
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
HD
MIC
EN
IOVC
C
GPI
O18
9993
_SD
A99
93_S
CL
SCL
SDA
INT0
#
HD
CP_
SDA
HD
CP_
SCL
KWP
AVC
C
HD
MI_
DD
C_S
CL
CLO
CK-
CO
AXO
UT
XTLO
IOVCC
AVC
C
IOVC
C
PLU
GPW
R
SPDIF
CLO
CK-
HDCP_SCL
HDMISD1
VCC
18VCC18
VCC
18
PVC
C
HDMISD2
DAT
A1+
HDMIMCLK
AVC
C
IOVC
C
VCC
18
HDMILRCK
DAT
A1-
CLO
CK+
DAT
A2+
XTLI
REGVCC
XTLO
IOVCC
HDMISD0
HDMICEN
HDMIBCLK
AVC
C
VCC18
KWP
SPD
IF
IOVCC
AVC
C
OSC_IN
IOVC
C
VCC18
HDCP_SDA
DAT
A2-
HDMIRST#
VCC18
DAT
A0-
IOVC
C
HDMISD3
IOVCC
GPIO17IOVCC
DAT
A0+
CI2
CA
PVC
C
DAT
A2+
DAT
A2-
DAT
A1+
DAT
A0-
DAT
A0+
DAT
A1-
CLO
CK-
CLO
CK+
HD
MIC
AB_O
UT
HD
MI_
DD
C_S
CL
CLO
CK-
HD
MI_
DD
C_S
DA
DAT
A0-
DAT
A0+
CLO
CK+
DAT
A1-
DAT
A1+
DAT
A2-
DAT
A2+
HD
MIC
AB_I
N
DD
C_S
DA
DD
C_S
CL
DD
C_S
DA
HD
MIC
AB_I
N
HD
MIC
AB_O
UT
DV3
3BR
EGVC
C
AVC
C
HD
MI_
PLU
GPW
R
HD
MI_
DD
C_S
CL
HD
MI_
DD
C_S
DA
AVC
C
DD
C_S
CL
VCC
18
CI2
CA
IOVC
C
DE_
SOG
HD
MIR
ST#
VCC
18
AVC
C18
HD
MIO
DC
KH
DM
IVSY
NC
HD
MIH
SYN
CH
DM
IDE
PLU
GPW
R
GPI
O17
[3]
HD
MIH
SYN
C[3
]H
DM
IVSY
NC
[3]
HD
MIO
DC
K[3
]H
DM
IDE
[3]
SCL
[1,6
,11]
SDA
[1,6
,11]
GPI
O18
[3]
INT0
#[3
,6]
DE_
SOG
[3]
VI[0
..23]
[3]
27M
HZ
[3]
HD
MIM
CLK
[3]
HD
MIB
CLK
[3]
HD
MIL
RC
K[3
]
HD
MIS
D0
[3]
HD
MIS
D1
[3]
HD
MIS
D2
[3]
HD
MIS
D3
[3]
HD
MIC
EN[3
]
DV3
3B[7
,8,9
,12,
13,1
4]
HD
MI_
PLU
GPW
R
HD
MI_
PLU
GPW
R
DV3
3B
AVC
C
AVC
C
DV3
3B
AVC
C
DV3
3B
HD
MI_
PLU
GPW
R
DV3
3B
DV3
3B
C67
1000
PF
R10
90
R10
70
R94
1K
TP44
X3
27M
Hz/
NC
CR
YS/4
9US/
P4.8
8
TP53
CB1
40
0.1u
F
CB1
57
0.1u
F
R10
60
+C
E54
4.7u
F/16
v
C99
10uF
/10v
C08
05/S
MD
TP41
TP54
C85 18pF
/NC
CB1
320.
1uF
C59
1000
pF
C65
1000
PF
L25
FB
+C
E52
4.7u
F/16
v
CB1
39
0.1u
F
R11
5
1M/N
C
R15
2N
C
R93
0
R96
4.7k
C78
1000
PF
+C
E53
4.7u
F/16
v
R11
947
k
R95
0
U10
EEPR
OM
24C
02/C
OD
E
1 2 3 45678
NC
NC
NC
GN
DSD
ASC
LW
PVC
C
R10
80
L20
FB
U36
CM
2021
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19202138 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
5V_S
UPP
LY
LV_S
UPP
LY
GN
D
TMD
S_D
2+
TMD
S_G
ND
TMD
S_D
2-
TMD
S_D
1+
TMD
S_G
ND
TMD
S_D
1-
TMD
S_D
0+
TMD
S_G
ND
TMD
S_D
0-
TMD
S_C
K+
TMD
S_G
ND
TMD
S_C
K-
CE_
REM
OTE
_IN
DD
C_C
LK_I
N
DD
C_D
AT_I
N
HO
TPLU
G_D
ET_I
NH
OTP
LUG
_DET
_OU
T
DD
C_D
AT_O
UT
NC
NC
GN
D
TMD
S_D
2+
TMD
S_G
ND
TMD
S_D
2-
TMD
S_D
1+
TMD
S_G
ND
TMD
S_D
1-
TMD
S_D
0+
TMD
S_G
ND
TMD
S_D
0-
TMD
S_C
K+
TMD
S_G
ND
TMD
S_C
K-
CE_
REM
OTE
_OU
T
DD
C_C
LK_O
UT
TP55
CB1
44
0.1u
F
CB1
52
0.1u
F
CB1
50
0.1u
F
C72
1000
PF
L27
FB
CB1
43
0.1u
F
CB1
36
0.1u
F
C75
1000
PF
+C
E51
4.7u
F/16
v
C64
1000
PF
CB1
56
0.1u
F
RN
3133
x4
12
34
56
78
C10
90.
1uF
C04
02/S
MD
C12
50.
1uF
C04
02/S
MD
R90
R/N
C
TP48
C81
0.1u
F
TP62
CB1
37
0.1u
F
TP1
CB1
46
0.1u
F
C63
1000
PF
R11
847
k
RN
3033
x4
12
34
56
78
CB1
45
0.1u
F
L22
FB
C57
1000
pF
R12
047
k
CB1
49
0.1u
F
TP45
C61
1000
PF
RN
3233
x4
12
34
56
78
CB1
53
0.1u
F
C76
1000
PF
L70
FB
TP61
TP42
RN
2933
x4
12
34
56
78
TP51
C60
1000
PF
R11
3
100
CB1
51
0.1u
F
QF1
MO
SFET
N 2
N70
02/N
CSO
T23/
SMD
1
32
L26
FB
R11
747
kC
B155
0.1u
F
R11
633
+C
E49
4.7u
F/16
v
TP56
RN
2833
x4
12
34
56
78
+C
E50
33uF
/16v
R52
NC
C58
1000
pF
R10
5 4.7K
TP52
C83
0.01
uF
L21
FB
R11
4
100
C77
1000
PF
R92
0
CB1
34
0.1u
F
RN
2733
x4
12
34
56
78
QF2
MO
SFET
N 2
N70
02/N
CSO
T23/
SMD
1
32
CB1
35
0.1u
F
P1 HD
MI/S
MD
/CO
N/A
HD
MI T
YPE-
A1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
22 212023
C79
1000
PF
L23
FB
RN
2633
x4
12
34
56
78
U9
EEPR
OM
24C
08/C
OD
E
1 2 3 45678
NC
NC
NC
GN
DSD
ASC
LW
PVC
C
CB1
42
0.1u
F
CB1
41
0.1u
F
TP47
R25
30
L24
FB
C80
0.1u
F
C86
18pF
/NC
C82
33pF
Q20
2N39
04SO
T23/
SMD
1
32
C74
1000
PF
TP49
CB1
31
0.1u
F
R11
00
R10
0
4.7K
/NC
C66
1000
PF
MT8293
U8
MT8
293
LQFP
128/
SMD
/829
3
6665
126
63
30
112
6261 6457 6056555452515049
108
73
70
78
109
79
38
118
8687
68
117
67
4845
69
107
97121
120
113
106
114
115
111
116
123
58 59
110
7576
128
1
127
2345
76
8910
13
119
12
16
11
15
17
202122
1918
23
26272829
32
2425
373633 34 35
91
8988
90
122
7172
98
46 47
14
31
5339 40 41 42 43 44
74
77
808182838485
9293949596
99100
101
102
103
104
105
124
125
G1
CVCC18CGND18
CG
ND
18
RX2
+
IOGND33
CVC
C18
RX2
-AV
CC
AGN
D
AVC
C
AGN
D
AGN
DR
X0+
RX0
-
AGN
DR
XC+
RXC
-AV
CC
QE1
1
SD1
SPDIF
IOGND33
QE1
0
MCLK
CI2
CA
IOG
ND
33
XTALVCCREGVCC
IOVCC33
QE4
MUTE
EXT_
RES
CVC
C18
IOGND33
IOVC
C33
IOG
ND
33
QE3
IOVC
C33
CG
ND
18
IOG
ND
33
QE7
QE6
QE8
QE5
QE1
RX1
-R
X1+
QE9
WSSCK
HSY
NC
VSYNC
DE
CENSOG_INOSC_IN
NC
IOVCC33IOGND33
NCKWP
KSDA
CGND18
OD
CK
CVCC18
GPIO13
KSCL
GPIO14
GPIO12
GPIO11GPIO10
GPIO9
IOVCC33IOGND33
GPIO8
GPIO7GPIO6GPIO5GPIO4
GPIO3
CVCC18CGND18
CG
ND
18C
VCC
18
GPI
O2
GPI
O1
GPI
O0
INT
RESET#TEST
SCDT
QE2
SD3SD2
IOVC
C33
PGN
DPV
CC
GPIO15
IOVCC33
AVC
C
CSD
AC
SCL
DSD
AD
SCL
CEC
PWR
5V
SD0
IOVCC33
CGND18CVCC18AUDPVCC18AUDPGNDXTALOUTXTALIN
QE23QE22QE21QE20QE19
QE1
8Q
E17
QE1
6Q
E15
QE1
4Q
E13
QE1
2
QE0
CVC
C18
ePad
/GN
D
TP43
CB1
38
0.1u
F
R91
0
C68
1000
PF
TP50
CB1
33
0.1u
F
CB1
54
0.1u
F
C62
1000
PF
R98
0TP
46
JP13
S/PD
IF O
UT/
NC
1 2 3
1 2 3
R97
4.7K
C69
1000
PF
U26
AZ1
117/
adj
SOT2
23/S
MD
1
23
ADJ/GND
OU
TIN
C73
1000
PF
R11
2N
C
A A
B B
C C
D D
E E
44
33
22
11
NEA
RLY
ICN
EAR
LY V
GA
CO
N
V2
V2
V2
V2
VGA
IN
L : W
P DI
SABL
EH
: WP
ENAB
LEN
EAR
LY IC
NEAR CONNECTOR
N-M
OSF
ETN
-MO
SFET
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
814
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
RED
RED
+
VGAS
OG
BLU
E-
RED
-
GR
EEN
-
GR
EEN
+
BLU
E+
GR
EEN
+G
REE
N-
BLU
E+BL
UE-
RED
+
VGAS
OG
RED
-
VGAH
SYN
C#
VGAV
SYN
C#
GN
DA
GR
EEN
VGAS
DA_
IN
BLU
_GN
D
RED
VGAS
CL_
IN
HSY
NC
#
GR
N_G
ND
RED
_GN
DBL
UE
VSYN
C#
GR
N_G
ND
BLU
_GN
D
PIN
9
BLU
E
VGAH
SYN
C#
HSY
NC
#
VGAV
SYN
C#
GR
EEN
VGAS
DA
VGAR
OM
WP
GN
DA
VFE_
GN
D
VGAS
CL
SOY0
PB0+
Y0-
Y0+
PR0+
PB0-
PR0-
GN
DA
GN
DA
A-YU
V-R
A-YU
V-L
Y-R
Y-L
PR_G
ND
PB0_
IN
Y_G
ND
PB_G
ND
PR0_
IN
AVPB
0P
AVPR
0P
AVPB
0P
Y0_I
N
AVPR
0P
RED
BLU
E
GR
EEN
VGA_
PLU
GPW
R
VGAS
CL_
INVG
ASD
A_IN
HSY
NC
#
Y-L
Y-R
1
PB0_
IN
PR0_
IN
Y0_I
N
VSYN
C#
VGAS
DA_
INVG
ASD
A
VGAS
CL_
IN
VGA_
PLU
GPW
R
VGAS
CL
TXD
RXD
VGAS
DA_
IN
Y-R
1
RED
_GN
D
A-YU
V-L
Y_G
ND
PB_G
ND
PR_G
ND
PB0_
INAV
PB0N
PR0_
IN
AVPR
0N
AVY0
N
AVY0
N
Y0_I
N
AVPR
0N
AVPB
0N
AVY0
P
AVY0
P
VFE_
GN
D
DV3
3B
+5V
A-YU
V-R
VGAS
CL_
IN
GPI
O11 GPI
O11
Y-LY-
R
RED
-[3
]
BLU
E+[3
]
GR
EEN
+[3
]
BLU
E-[3
]
RED
+[3
]
VGAS
OG
[3]
GR
EEN
-[3
]
VGAH
SYN
C#
[3]
VGAV
SYN
C#
[3]
GN
DA
[1,3
,4,1
1,12
,13]
A-YU
V-R
[10]
A-YU
V-L
[10]
TXD
RXD
SOY0
Y0+
Y0-
PB0+
PB0-
PR0+
PR0-
VFE_
GN
D[2
,3,4
,9,1
0,11
,12,
14]
DV3
3B[7
,8,9
,12,
13,1
4]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
GPI
O11
[3,8
]
+5V
VGA_
PLU
GPW
R
VGA_
PLU
GPW
R
VGA_
PLU
GPW
R
+5V
+5V
+5V
+5V
SB33
B
R28
NC
R13
268
R49
582
R35
0
47K
D13
1N41
48
QF6
2N70
02
13
2
C89
10nF
L56
FB
C12
910
0nF
R33
251
0
R13
982
R14
50
R12
60
C94
10nF
U34
PESD
3V3L
4UG
1 2 345
A GN
DB
CD
Q29
PDTC
143Z
TSO
T23/
SMD
1
32
R29
NC
R13
00
R20
210
0
C10
05p
F
C13
015
pF
+
CE1
9222
uF/3
5V
R15
4
2K
R14
13.
3K
R13
410
0
FB27
0
R19
968
R15
510
K/N
C
R13
868
R17
24.
7K
R49
782
L57
FB
C98
10nF
R33
351
0
C11
510
0nF
R55
0
FB29
0
FB21
0
R14
010
0
C88
5pF
L53
FB
CN
1 CO
MPO
NEN
T 657
8
910
SIG
3G
ND
3
GN
D4
SIG
4
GN
D5
SIG
5
R37
1K
R35
347
K
C12
210
0nF
R4
15K
R21
010
0
R13
5N
C
L29
2.2u
H
R14
7
82
R20
610
0
R14
23.
3K
C92
5pF
R49
1K
R13
70
U33
PESD
3V3L
4UG
1 2 345
A GN
DB
CD
C87
10nF
R13
60
C11
615
pF
+
CE1
9322
uF/3
5V
C10
25p
F
L54
FB
C96
0.1u
F/N
C
C13
310
0nF
R14
668
R12
80
D14
1N41
48
R14
310
0
C91
10nF
CN
2C
OM
PON
ENT_
AUD
IO
12
34
GN
D4
SIG
4
GN
D5
SIG
5
C12
315
pF
P2 D-S
UB1
5 FE
MAL
ED
SUB1
5/D
IP/F
16 17
1 2 3 4 56 7 8 9 10
11 12 13 14 15
FB20
0
R14
410
0
R52
84.
7K
R49
682
R35
2
47K
R20
368
CB1
620.
1uF
C90
4.7n
F
R7
15K
L30
2.2u
H
U35
PESD
3V3L
4UG
1 2 345
A GN
DB
CD
R15
120
K
R14
810
0
R13
382 R
150
2K
L55
FBR
86N
CR
0603
/SM
D
U32
PESD
3V3L
4UG
1 2 345
A GN
DB
CD
FB28
0
C12
610
0nF
C11
910
0nF
C93
10nF
R13
10
FB17
0
C11
24.
7nF
R35
147
K
C95
0.1u
F/N
C
R87
NC
R06
03/S
MDQ
F5
2N70
02
1
32
R20
768
U11
EEPR
OM
24C
02
1 2 3 45678
NC
NC
NC
GN
DSD
ASC
LW
PVC
C
C97
5pF
A A
B B
C C
D D
E E
44
33
22
11
AU
DIO
AD
C
PULL
DOW
N FO
R LJ
N-M
OSF
ET
N-M
OSF
ET
AU
DIO
AD
C
BYP
ASS
VID
EO O
UTP
UT
V2
V2
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
914
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
TEST
P2
SDA
SCL
ADIN
AOM
CLK
AOBC
LKAO
LRC
K
AOM
CLK
AOBC
LKAO
LRC
K
ADC
VL
SCL
SDA_
V50
SCL_
V50
SDA
+5V
AOLR
CK
AOM
CLK
ADIN
AOBC
LK
DV3
3B
ADC
VA
ADC
VD
ADC
VD
ADC
M1
ADC
M1
ADC
M0
A_IN
_L
A_IN
_R
ADC
VL
ADC
M0
GN
DA
ADC
RST
#
TEST
P2
ADC
VA
GN
DA
SW1
SW2
FCLK
FCM
D
SW2
SW1
SDA_
V50
SCL_
V50
VFE_
GN
D
VFE_
GN
D1
+5V
CVB
S_O
UT
DV3
3B
VFE_
GN
D
+12V
A_IN
_LA_
IN_R
GPI
O12
ADC
RST
#
GPI
O12
TEST
P2[3
]
SDA
[1,6
,8,9
]SC
L[1
,6,8
,9]
AOBC
LK[3
,13]
AOM
CLK
[3,1
3
ADIN
[3]
AOLR
CK
[3,1
3]
GN
DA
[1,3
,4,1
0,12
,13]
FCLK
FCM
D
A-YU
V-L
A-D
TV-L
AU_I
N_L
A-D
TV-R
A-YU
V-R
AU_I
N_R
CVB
S_O
UT
SDA_
V50
[1,6
,8,9
]SC
L_V5
0[1
,6,8
,9]
VFE_
GN
D[2
,3,4
,8,1
0,11
,12,
14]
VFE_
GN
D1
[2,3
,4,8
,10,
12]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
CVB
S_O
UT
[9,1
4]
DV3
3B[7
,8,9
,12,
13,1
4]
+12V
[1,2
,9,1
0,11
,12,
14]
GPI
O12
[3,9
]
ADC
VLAD
CVL
ADC
VL
ADC
VLAD
CVD
ADC
VAAD
CVA
+5V
ADC
VA
ADC
VLAD
CVL
DV3
3B
+5V +5
V
DV3
3B
DV3
3B DV3
3B+5
V
+5V
+5V
+5V
+12V
+12V
+5V
+5V
ADC
VL
C10
41u
F
CB1
73
0.1u
F
+C
E60
4.7u
F/25
V
R16
110
K
C17
90.
01uF
R16
710
K/N
C
CB1
670.
1uF
QF3
2N70
02
1
32
FB32
NC
R17
633
FB35
1uF/
10v
CB1
650.
1uF
Q7
2SD
2653
K1
32
U13
HEF
4052
TSSO
P16/
SMD
1 2 3 4 5 6 7 8910111213141516
Y0B
Y2B
ZB Y3B
Y1B
/E VEE
VSS
A1A0Y3A
Y0AZAY1A
Y2A
VDD
R17
733
C18
00.
01uF
C16
6
10uF
/10v
C10
64.
7uF/
16V
R58
NC
+
CE6
8N
C
Q30
PDTC
143Z
TSO
T23/
SMD
1
32
U12
CS5
340
ADC
TSSO
P16/
SMD
1 2 3 4 5 6 7 8910111213141516
M0
MC
LKVL SD
OU
TG
ND
VD SCLK
LRC
KR
ST#
AIN
LVQ
AIN
RVAR
EF_G
ND
FILT
+M
1
R15
610
K
CB1
630.
1uF
R16
610
K/N
C
FB30
NC
CB1
640.
1uF
C10
70.
1uF
C06
03/S
MD
FB33
FB
CB1
680.
1uF
R12
20
FB24
FB
C16
5
10uF
/10v
R16
410
K/N
C
R18
875
C10
31u
F
+
CE6
7
33uF
/10v
C10
51u
F
R19
133
0 1%
Q23
2N39
04SO
T23/
SMD
1
32
R15
810
K
+C
E61
4.7u
F/25
V
R16
810
K/N
C
FB23
FB
CB1
700.
1uF
R18
10
R16
010
K
R10
4N
C
R49
827
K
QF4
2N70
02
1
32
+C
E59
4.7u
F/25
V
R18
724
K
R15
75.
1
R16
510
K/N
C
FB34
1uF/
10v
Q26
2N39
04SO
T23/
SMD
1
32
R17
833
R12
3N
C
FB31
FB
R12
50
R50
0
10K
+C
E64
47uF
/16V
R15
910
K
R17
910
K
R19
047
K
R17
433
R12
4N
C
R50
1
10K
CB1
710.
1uF
R49
927
K
+C
E24.
7uF/
16v
A A
B B
C C
D D
E E
44
33
22
11
TO MT8202
FROM AV BOARD
THIS
PA
GE
NEA
RLY
IC
FOR EXTERNAL TVD
2006
-1-4
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
1014
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SY0
SC0
CVB
S0C
VBS1
CVB
S2C
VBS3
CVB
S3AV
CVB
S3
SY0
SC0
AVSY
0
AVSC
0
B/AV
PR1P
R/A
VY1P
Y1+
Y1-
PB1+
PB1-
PR1+
PR1-
SOY1
CVB
S0AV
CVB
S0
CVB
S1AV
CVB
S1
CVB
S2AV
CVB
S2
AVC
VBS3
AVC
VBS0
AVC
VBS1
AVC
VBS2
AVSY
0AV
SC0
PR1+
SOY1
Y1+
PB1+
PR1-
Y1-
PB1-
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D1
VFE_
GN
D1
AVC
VBS1
Y1P
GPR
1PB
R
G/A
VPB1
P
B/AV
PR1P
G/A
VPB1
P
SCL_
V50
GN
DSD
A_V5
0
GN
D
TVD
PWR
CC
IR_V
2SD
A0
TVD
PWR
CC
IR_V
7
TVD
PWR
CC
IR_V
[0..7
]
CC
IR_V
CLK
CC
IR_V
6C
CIR
_V5
SDA
SCL
CC
IR_V
3
SCL
CC
IR_V
4
SDA
CC
IR_V
1C
CIR
_V0
TVD
_CE
CC
IR_V
CLK
R G B
SCL0
SDA_
V50
SCL_
V50
AVPB
1NAV
Y1N
AVPR
1N
AAD
CVS
S
VFE_
GN
D
VFE_
GN
D1
AVSY
1SY
1
AVSC
1SC
1
VFE_
GN
D1
VFE_
GN
D1
R/A
VY1P
PB1P
AVC
VBS3
AVSY
0
SY1
AVSC
1
SC1
AVSY
1
+12V +5
V
USB
_IR
_EN
SCL0
SDA0
USB
_IR
_EN
IR
AVPR
1N
AVPB
1N
PR1P
GN
D
Y1P
Y1N
AVY1
N
USB
_MP_
ON
PR1N
AVPR
1NPB
1NAV
PB1N
IRG
ND
USB
_REV
USB
_RST
AVY1
N
PB1P
SY0
[3]
SC0
[3]
CVB
S0[3
]C
VBS1
[3]
CVB
S2[3
]C
VBS3
[3]
AVC
VBS0
[11]
AVC
VBS1
[11]
AVC
VBS2
[11]
AVC
VBS3
[11]
AVSY
0[1
1]AV
SC0
[11]
SOY1
[3]
Y1+
[3]
PB1-
[3]
PR1+
[3]
PB1+
[3]
Y1-
[3]
PR1-
[3]
VFE_
GN
D1
[2,3
,4,1
1]
CC
IR_V
CLK
[3]
SDA0
[3,1
0]
SDA
[1,6
,8,1
1]SC
L[1
,6,8
,11]
CC
IR_V
[0..7
][3
]
GPI
O3
GPI
O16
R[2
,3,4
,11]
G[2
,3,4
,11]
B[2
,3,4
,11]
SCL0
[3,1
0]
SDA_
V50
[1,6
,8,9
]SC
L_V5
0[1
,6,8
,9]
SDA1
GPI
O13
AVPB
1NAV
Y1N
AVPR
1N
AAD
CVS
S[1
,3,8
,9,1
0,11
,12,
14]
VFE_
GN
D[2
,3,4
,8,1
0,11
,12,
14]
VFE_
GN
D1
[2,3
,4,8
,9,1
2]
AVC
VBS3
[10,
14]
AVSY
0[1
0,14
]
AVSC
1[1
0,14
]
SC1
[10,
14]
AVSY
1[1
0,14
]
SY1
[10,
14]
+12V
[1,2
,9,1
0,11
,12,
14]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
IR[3
,10,
13]
USB
_IR
_EN
[3,1
0]
A-D
TV-L
A-D
TV-R
+5V
+5V
+5V
R22
6N
C
R54
0
R22
7N
C
C11
147
nF
R37
5N
C
C15
022
pF
C14
110
0nF
C14
715
pF
R21
910
0
C13
64.
7nF
C12
733
0pF R
349
33
R53
0
R37
6N
C
JP5
16x2
DIP
10X2
/W/H
/P2.
0/45
04/N
C
1 3 5 7 9 11
2 4 6 8 10 1213
1415
16
R21
168
L28
FB
R20
10
C13
147
nF R37
7N
C
C14
510
0nF
TP70
R19
70
JP2
10x2
DIP
10X2
/W/H
/P2.
0/45
04/N
C
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
C12
447
nF
JP8-
PD
6x1/
NC
1 3 52 4 6
R56
NC
R20
00
C12
133
0pF
C13
710
0nF
C11
333
0pF
TP72
R21
710
0C
164
47nF
C04
02/S
MD
C12
033
0pF
R20
80
CB1
580.
1uF
C13
815
pF
C14
010
0nF
C11
047
nF
R32
10
R34
710
K
C11
847
nF
R21
868
U14
PI5V
330
15 14 13 12 11 10 971 52 3 64
16
8
EN SD1
SD2
DD
SC1
SC2
DC
DB
IN SB1
SA1
SA2
SB2
DA
VCC
GN
D
C12
833
0pF
C04
02/S
MD
C13
433
0pF
R19
80
+C
E58
4.7u
F/16
v
C11
747
nF
C14
922
pF
R21
310
0
C14
610
0nF
R41
0
C15
622
pF
R22
0N
C
C14
215
pF
CE1
904.
7uF/
16V
C13
2
47nF
C04
02/S
MD
TP71
C11
433
0pF
CB1
610.
01uF
R21
468
C23
10.
1uF
C04
02/S
MD
CB1
980.
1uF
C06
03/S
MD
C14
810
0nF
C13
533
0pF
C04
02/S
MD
R20
40
A A
B B
C C
D D
E E
44
33
22
11
CS4
334
AU
DIO
DA
C S
PEA
KER
/HEA
DPH
ON
E O
UT
SPEA
KER
/HEA
DPH
ON
E O
UTP
UT
AV2
BYP
ASS
AU
DIO
OU
TPU
T
MU
TE_C
IRC
UIT
HEADPHONE CONNECTOR
IC
TTE
SHEN
ZHEN
R&D
CEN
TER
B
C
E
3906
AV1
BYP
ASS
AU
DIO
OU
TPU
T
2006
-5-2
6YW
X
MT8
202
C
1114
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
AOSD
ATA1
DAC
VA
AUSP
R
AUSP
L
AOLR
CK
AOBC
LKAO
SDAT
A1
AOM
CLK
OPV
REF
OPV
REF
AUSP
R
A_M
UTE
AUSP
L
OPV
REF
A_M
UTE
OP1
VREF
AR AL
OP1
VREF
AVL_
OU
T
AVR
_OU
T
AOLR
CK
AOM
CLK
AOBC
LK
ARAL GN
DA
HP_
DET
ECT
HEA
DPH
ON
E_L
GPI
O14
OU
TR+
OU
TR-
OU
TL+
OU
TL-
8202
UP3
_5
SPO
UTR
SPO
UTL
DAC
VA
OU
TL+
SPO
UTR
HEA
DPH
ON
E_L
AMP_
GN
DH
EAD
PHO
NE_
RAM
P_G
ND
+5V
OP1
VREF
AVR
_OU
TAV
L_O
UT +5
V
OU
TL-
OU
TR-
OU
TR+
+12V
8202
UP3
_5
HEA
DPH
ON
E_R
SPO
UTL
GPI
O15
HP_
DET
ECT
GPI
O15
AMP_
GN
D82
02U
P3_5
A_M
UTE
A_M
UTE
AMP_
+12V
AMP_
+12V
A_M
UTE
TU_A
UR
OO
P1VR
EF
OP1
VREF
AV1O
UPU
T_R
AV1O
UPU
T_L
TU_A
ULO
LRC
K-G
PIO
7
AOM
CLK
-GPI
O9
GPI
O11
AOBC
K-G
PIO
8
AOSD
ATA3
TU_A
UR
OTU
_AU
LO
AOSD
ATA3
AOBC
K-G
PIO
8
LRC
K-G
PIO
7AO
MC
LK-G
PIO
9AV
1OU
PUT_
R
AV1O
UPU
T_L
AOSD
ATA1
[3]
AOBC
LK[3
,11]
AOM
CLK
[3,1
1]
AOLR
CK
[3,1
1]
AR[3
]AL
[3]
GN
DA
[1,3
,4,1
0,11
,12]
GPI
O14
8202
UP3
_5
AVR
_OU
T[1
1,14
]AV
L_O
UT
[11,
14]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
+12V
[1,2
,9,1
0,11
,12,
14]
8202
UP3
_5
GPI
O15
A_M
UTE
[10,
14]
GPI
O11
[3,8
]
LRC
K-G
PIO
7[3
,11]
AOBC
K-G
PIO
8[3
,11]
AOM
CLK
-GPI
O9[
3,11
]AO
SDAT
A3[3
,11]
TU_A
ULO
[11,
12,1
4]TU
_AU
RO
[11,
12,1
4]
+5V
OPV
REF
OPA
V120
OPA
V120
OPV
REF
OPA
V120
OPV
REF
OPA
V120
OPA
V120
OP1
VREF
OP1
VREF
AMP_
+12V
AMP_
+12V
AMP_
+12V AM
P_+1
2VAM
P_+1
2V
+5V
+5V
AM
P_G
ND
AM
P_G
ND
AM
P_G
ND
AM
P_G
ND
AM
P_G
ND
AM
P_G
ND
+12V
5VSB
OP1
VREF
OPA
V120
OP1
VREF
OPA
V120
+5V
+5V
+5V
R28
8
20K
R27
712
K
R22
833
R22
147
K
+-
U17
A
NJM
4558
OPA
321
84
C15
210
00pF
R12
147
K
+
CE8
510
uF/1
0V
C19
1
10uF
/10v
C08
05/S
MD
Q21
2N39
04SO
T23/
SMD
1
32
Q22
2N39
04SO
T23/
SMD
1
32
R33
5
10K
L76
BCK-
4235
( 22
UH
)
1
2
CE1
1122
0uF/
25v
C18
582
0pF
R28
95.
1K
R27
5
20K
C23
20.
1uF
C04
02/S
MD
R23
70
C19
310
uF/1
0vC
0805
+-
U18
A
NJM
4558
OPA
321
84
R28
2
4.7k
R23
410
K
C15
34.
7uF
CB1
93
0.1u
F
C06
03/S
MD
R27
951
CB1
910.
1uF
C06
03/S
MD
R27
3
0
L77
BCK-
4235
( 22
UH
)
1
2
+-
U18
B
NJM
4558
OPA
567
84
CE5
10U
/16U
R29
0
51
R28
05.
1K
R25
410
K
U38
CS4
334
2-C
H A
UD
IO D
ACSO
P8/S
MD
1 2 3 45678
SDAT
AD
EM#/
SCLK
LRC
KM
CLK
AOU
TRAG
NDVA
AOU
TL
C19
2
10uF
/10v
C08
05/S
MD
R24
910
K
R26
75.
1K
L74
BCK-
4235
( 22
UH
)
1
2
+
CE7
410
uF/1
0V
C18
615
0pF
FB26
FB
C15
10.
1uF
C19
40.
1uuF
C04
02
L75 BC
K-42
35 (
22U
H )
1
2
R59
0
+C
E92
220u
F/16
v
+
CE8
810
uF/1
0V
R28
4
51
R16
20
+
CE9
110
uF/1
0V
+C
E78
22uF
/16V
R24
010
K
C17
60.
1uF
0402
/SM
D
R28
1
4.7k
+C
E102
22uF
/16v
R33
7N
C
R26
139
K
R33
410
K
R12
9N
C
R31
NC
R28
50
Q11
2SD
2653
K1
32
RN
38
33x4
12
34
56
78
FB25
FB
CB1
800.
1uF
D24
1N41
48
R25
151
C18
782
0pF
C23
5
0.01
uF
R12
7N
C
C23
6
0.01
uF
C15
915
0pF
C16
215
0pF
+C
E93
470u
F/25
vC
330U
F25V
/D8H
14
R23
951
C15
422
00pF C
177
4.7u
F06
03/S
MD
CB1
884.
7uF/
10v
C08
05/S
MD
R30
100
C16
382
0pF
Q15
2N39
061
3 2
C15
822
00pF
R28
7
10K
U15
CS4
334
2-C
H A
UD
IO D
ACSO
P8/S
MD
1 2 3 45678
SDAT
AD
EM#/
SCLK
LRC
KM
CLK
AOU
TRAG
NDVA
AOU
TL
R26
50
R52
710
K
P4
12x1
W/H
OU
SIN
G R
.A
DIP
12/W
H/P
2.0/
R
1 2 3 4 5 6 7 8
R23
033
CE1
1322
0uF/
25V R
338
NC
CB1
9210
uF/1
0vC
0805
/SM
D
+
CE8
610
uF/1
0V
CB1
944.
7uF/
10v
C08
05/S
MD
R27
4
10K
C18
815
0pF
C23
40.
01uF
R33
610
K
R32
20K
C16
90.
33uF
/50v
C08
05/S
MD
+
CE8
710
uF/1
0V
FB3
FB
R27
85.
1K
CB1
904.
7uF/
10v
C08
05/S
MD
R28
61k
C23
30.
01uF
+-
U17
B NJM
4558
OPA
567
84
+
CE9
010
uF/1
0V
R22
433
C18
9
10uF
/10v
C08
05/S
MD
Q14
2N39
06
1
32
+C
E73
4.7u
F
Q9
2SD
2653
K1
32
Q27
2N39
04SO
T23/
SMD
/NC
132
CB1
750.
1uF
U16
YDA1
38
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
HPO
R
AVSS
VSSB
GR
VREF
R
INR
MU
TEN
PVD
DPR
OU
TPR
PVSS
R
PVSS
R
PVSS
R
PVSS
R
PVSS
R
OU
TMR
PVD
DM
R
PRO
TN
SLEE
PN
DVS
S
CKI
O
XO XI
HPO
L
REF
A
PVD
DR
EG
VREF
L
INL
HP
PVD
DPL
OU
TPL
PVSS
L
PVSS
L
PVSS
L
PVSS
L
PVSS
L
OU
TML
PVD
DM
L
VOL1
VOL0
MO
DE2
MO
DE1
MO
DE0
DVD
D
R27
60
C17
00.
33uF
/50v
C08
05/S
MD
JP4
12x1
W/H
OU
SIN
G R
.A
DIP
12/W
H/P
2.5/
R
1 2 3 4
C15
710
00pF
R24
820
K
R27
239
K
C23
70.
01uF
R33
90
+-
U40
A
NJM
4558
OPA
321
84
R23
55.
1K
+C
E76
4.7u
F/25
V
CB1
950.
1uF
C06
03/S
MD
R26
851
R22
533
+-
U40
B
NJM
4558
OPA
567
84
C23
94.
7uF/
10v
C08
05/S
MD
+
CE7
510
uF/1
0V
R23
147
K
C19
0
10uF
/10v
C08
05/S
MD
R26
612
K
C23
8 0.01
uF
C16
082
0pF
R28
3
100
R40
447
K
R34
00
C24
04.
7uF/
10v
C08
05/S
MD
R25
05.
1K
CB2
0810
uF/1
0vC
0805
/SM
D
R14
9N
C
R23
320
K
A A
B B
C C
D D
E E
44
33
22
11
LVD
S O
UT
LO =
> L
VDS
PO
WER
OFF
HI =
> L
VDS
PO
WER
ON
Tuner CVBS Direct Output
Tuner CVBS Switching Output
0418
To: 8202
To: SCART1
FRO
M T
uner
V2
LG P
ANEL
TTE
SHEN
ZHEN
R&D
CEN
TER
Tuner Interface 2006
-1-4
2006
-5-2
6YW
X
MT8
202
C
1214
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
CLK
1+C
LK1-
CLK
2-C
LK2+
AP[0
..7]
AN[0
..7]
GPI
O2
Pane
l_Po
wer
LVD
S_G
ND
LVD
S_G
ND
GN
D
LVD
S_G
ND
TU_C
VBS0
TU_C
BO_G
ND
AAD
CVS
S
MPX
1
TUM
PX2
MPX
2
TUM
PX1
ADC
_IN
3
PWM
_PAN
EL
TUN
ER+5
V
LVD
S_G
ND
SCL_
V50
SDA_
V50
ADC
_IN
3AD
C_I
N4
GN
DA
AAD
CVS
S
VFE_
GN
D1
AAD
CVS
S
TU_C
VBS1
AAD
CVS
S
ADC
_IN
4DV3
3B
TU_C
VBS_
SW
TU_C
VBS0
TU_A
UR
O
DV3
3B
+5V
AN2
AP2
CLK
1-C
LK1+
AP3
AN4
AP4
AN3
AN5
AP5
AN6
AP6
CLK
2-C
LK2+
AN7
AP7
AP1
AP0
AN0
AN1
PWM
1G
PIO
5
LVD
S_G
ND
TU_A
ULO
+12V
VFE_
GN
D1
TU_C
VBS1
SDA_
V50
Tune
r_R
eset
VFE_
GN
D1
TU1_
MO
NO
TUM
PX2
SIF1
TUM
PX1
TUN
ER+5
V
SCL_
V50
VFE_
GN
D1
Tune
r_R
eset
C6
C6
AP[0
..7]
[3]
AN[0
..7]
[3]
CLK
1+[3
]C
LK1-
[3]
CLK
2+[3
]C
LK2-
[3]
LVD
S_G
ND
[2]
SCL_
V50
SDA_
V50
MPX
1
MPX
2
TU_C
VBS0
AVC
VBS0
GPI
O2
PWM
_PAN
EL
ADC
_IN
4[3
]AD
C_I
N3
[3]
GN
DA
[1,3
,4,8
,9,1
1,14
]
AAD
CVS
S[1
,3,8
,9,1
0,11
,12,
14]
VFE_
GN
D1
[2,3
,4,8
,9,1
0]
DV3
3B[7
,8,9
,12,
13,1
4]
TU_C
VBS0
[12,
14]
TU_A
UR
O[1
1,12
,14]
DV3
3B[7
,8,9
,12,
13,1
4]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
GPI
O5
PWM
1
TU_A
ULO
[11,
12,1
4]+1
2V[1
,2,9
,10,
11,1
2,14
]
C6
[3,1
2]
+5V
+12V
TUN
ER+5
V
TUN
ER+5
VTU
NER
+5V
+5V
+12V
Pane
l_Po
wer
TUN
ER+5
V
L1FB
C14
315
pF
R19
330
RN
3333
x4
12
34
56
78
R35
4N
CR
0603
/SM
D
Q32
PDTC
143Z
TSO
T23/
SMD
1
32
R29
30
CB1
810.
1uF
L44
FB BEAD
/SM
D/0
805
C14
415
pF
RN
3733
x4
12
34
56
78
F15A
/32v
FUSE
/SM
D 0
603
TP59
R60
0
R5
47
R52
151
L9FB
BEAD
/SM
D/0
805
R21
639
K
+C
E95
220u
F/16
v
C38
0.1u
FC
0402
/SM
D
RN
3533
x4
12
34
56
78
TP60
C39
0.1u
FC
0402
/SM
D
R2
100
R1
100
JP11 FI
-SE3
0P-H
FLV
DS/
30P/
P1.2
5/S
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+
CE1
97
22uF
/10v
C13
910
nF
R20
75
C53
4.7u
F/10
vC
0805
/SM
D
R18
75/1
8
Q1
2N39
041
32
C48
1.8p
F
C52
0.1u
FC
0402
/SM
D
+
CE7
047
uF/1
6V
R29
6
2k
L11
NC
BEAD
/SM
D/0
805
RN
3633
x4
12
34
56
78
C17
50.
1uF
C06
03/S
MD
R29
422
k
R52
375
/NC
R3
3K
R29
1
10k
JP6
10x2
DIP
10X2
/W/H
/P2.
0/45
04
1 3 5 7 92 4 6 8 10
R21
20
R16
47
Q33
PDTC
143Z
TSO
T23/
SMD
1
32
R52
233
0
U19
SI49
43
1 2 3 4
8 7 6 5
S1 G1
S2 G2
D1
D1
D2
D2
R52
020
K
R16
310
K
RN
3433
x4
12
34
56
78
Q16
2N39
04SO
T23/
SMD
1
32
R29
2
10k
Q31
PDTC
143Z
TSO
T23/
SMD
1
32
R21
539
K
Q3
2N39
041
32
L45
NC
BEAD
/SM
D/0
805
A A
B B
C C
D D
E E
44
33
22
11
FOR
CHI-M
EI IN
VERT
ERCO
NNEC
TOR
SELE
CT
Low
For
Inte
rnal
SELE
CT
Hi
For E
xter
nal
Bac
k Li
ght c
ircui
t
AD
C K
EYPA
D 8
KEY
Inital pull up
V2
V2
9.26
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
1314
Frid
ay, M
arch
30,
200
7
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
ADC
_IN
2
PWM
0
PWM
1
PWM
0
BL_O
N/O
FF
IR
ADC
_IN
2
GPI
O6
IR
ADC
KEY
LED
BRIG
HTN
ESS
GN
D
8202
UP3
_1
SELE
CT
PWM
_PAN
EL
PWM
_PAN
EL
DV3
3B
+5V
ADC
_IN
2[3
,11]
PWM
0[3
]
PWM
1[3
]
IR[3
,10,
13]
GPI
O6
8202
UP3
_1
PWM
_PAN
EL
DV3
3B[7
,8,9
,12,
13,1
4]
+5V
[1,2
,4,6
,8,9
,10,
11,1
2,13
,14]
+5V
+5V
+5V
DV3
3B
5VSB
+5V
R33
NC
R30
51k
R30
6
10k
L3FB
C17
80.
01uF
C04
02/S
MD
C17
10.
1uF
R30
30/
NC
L40
FB BEAD
/SM
D/1
206
L46
FB
FB12
FB
R31
10
Q17
2N39
04SO
T23/
SMD
1
32
R31
6
4.7k
CB1
851u
F
CB2
000.
1uF
C06
03/S
MD
R31
510
k
C35
0.00
1uF
C04
02/S
MD
L39
FB BEAD
/SM
D/1
206
L47
FB
CB1
840.
1uF
R31
70
J7
12x1
W/H
OU
SIN
G R
.A
DIP
12/W
H/P
2.0/
R
1 2 3 4 5
Q18
2N39
04SO
T23/
SMD
1
32
R30
40
L48
FB
C24
11u
F/10
vC
0603
/SM
D
TP78
JP9
7x1W
/HO
USI
NG
DIP
7/W
/H/P
2.0
1 2 3 4 5 6 7
C37
0.1u
FC
0603
/SM
D
R30
8
4.7k
R11
110
K
R30
90/
NC
A A
B B
C C
D D
E E
44
33
22
11
ERO
0/U
P3_0
: M
AIN
PO
WER
SW
ITC
H
GPI
O D
ECR
IPTI
ON
GPI
O5/
TXD
:TO
PA
NEL
EN
AB
LEG
PIO
4 : E
EPR
OM
WR
ITE
PRO
TEC
T
GPI
O2
: LVD
S PO
WER
SW
ERO
2/U
P3_5
: SD
A
UP3
_4 :
SCL
ERO
1/U
P3_1
: LE
D1
GPI
O7
: SW
ITC
H H
EF40
52
GPI
O9
: SW
ITC
H A
V B
OA
RD
HEF
4052
GPI
O8
: SW
ITC
H H
EF40
52
GPI
O6/
RXD
: B
AC
K L
IGH
T O
N/O
FF
GPI
O3
: DTV
_CE
GPI
O14
: A
UD
IO A
MP
SLEE
PG
PIO
13 :
FOR
PD
P C
ON
TRO
LG
PIO
12 :
NO
NE
USE
GPI
O10
:SW
ITC
H A
V B
OA
RD
HEF
4052
GPI
O11
: +1
2V P
OW
ER C
ON
TRO
L
GPI
O16
: R
GB
/YU
V SW
ITC
HG
PIO
15 :
AU
DIO
AM
P M
UTE
GPI
O17
: H
DM
I SC
DT
SCL
: SC
L (T
TL M
OD
E)SD
A :
SDA
(TTL
MO
DE)
GPI
O18
: H
DM
I CA
BLE
DET
ECT
CEN
_DVI
/GPI
O :
HD
MI_
CEN
DE_
SOG
/GPI
O :
HD
MI R
ESET
OU
T_27
Mhz
/GPI
O :
27M
hz T
O M
T829
3
GPI
O/P
WM
0 : D
IMM
ING
GPI
O/P
WM
1 :T
O P
AN
EL E
XTER
NA
L PW
M
SDA
1 : T
VB_C
E
SDA
0 : E
XTER
NA
L D
TV T
XD
ERO
3/G
PIO
: LV
DS
GPI
O
AO
SDA
TA5/
GPI
O1
: AU
DIO
AM
PLIF
IER
CO
NTR
OL
SCL0
: EX
TER
NA
L D
TV R
XD
SCL1
: SC
AR
TSEL
AD
CIN
0 : S
CA
RT
AD
CIN
1 : S
CA
RT
AD
CIN
2 : A
DC
KEY
AD
CIN
3 : T
UN
ER1
AD
CIN
4 : T
UN
ER2
DE/
GPI
O :
LVD
S G
PIO
VCLK
/GPI
O :
LVD
S G
PIO
P1: N
O U
SEP3
: NO
USE
P4: N
O U
SER
1: N
O U
SER
2: F
OR
USB
VC
C N
eed
3V ~
3.3
V
2006
-1-4
TTE
SHEN
ZHEN
R&D
CEN
TER
2006
-5-2
6YW
X
MT8
202
C
1414
Wed
nesd
ay, D
ecem
ber 2
7, 2
006
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SCL
IOSD
ASD
AIO
SCL
8202
UP3
_5
SCAR
T1_F
B
SCAR
T1_F
B
SCAR
TFB
SCAR
TFB
GN
DAAC
ENT
GPI
O10
SCL1
SCL SC
ART_
FB
AUSW
0S0
SDA
AUSW
0S1
SCAR
TSEL
SUBW
OO
FER
SCAR
TFB
FDAT
R/A
VSC
1AV
CVB
S1/A
VSY1
AVC
VBS1
AVSY
1
AVC
VBS3
AVSC
0
AVSY
0
ADC
_IN
0
GN
DA
GN
DV
GN
DA
GN
DA
GN
DA
GN
DV
AVC
VBS2
+5V
AVC
VBS1
/AVS
Y1G
ND
V
SCAR
TSEL
R/A
VSC
1
SUBW
OO
FER
CVB
S_O
UT
TU_A
UR
O
AVPB
1N
B
AVPR
1NG AU
_IN
_R
AVR
_OU
TAV
L_O
UT
GN
DV
GN
DA
AUSW
0S0
TU_C
VBS0
AU_I
N_L
AUSW
0S1
TU_A
ULO
+12V
GN
DV
SCAR
T1_F
B
GN
DV
ADC
_IN
1
GN
DA
AVY1
N
AVSC
1
R
8202
UP3
_4
G B
RAVC
VBS2
AVC
VBS3
AVSY
0
AVPR
1N
AVPB
1N
AVY1
N
SC1
SY1
AVSC
1
AVSY
1
DV3
3B
+5V
A_M
UTE
A_M
UTE
+5V AU
_IN
_R
AU_I
N_L
TU_A
ULO
ADC
_IN
1
TU_C
VBS0
ADC
_IN
0
CVB
S_O
UT
AVR
_OU
T
AVSC
0
AVC
VBS1
AVL_
OU
T
TU_A
UR
O
+12V
IOSD
AIO
SCL
8202
UP3
_582
02U
P3_4
GN
DA
[1,3
,4,8
,9,1
1,12
]
FDAT
SCL
[1,6
,11]
SCAR
T_FB
SDA
[1,6
,11]
ACEN
T
SCL1
GPI
O10
B[1
0,14
]
G[1
0,14
]
R[1
0,14
]
AVC
VBS2
[10,
14]
AVC
VBS3
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MT8202CGPreliminary specifications are subject to change without notice HDTV-Ready Flat Panel TV Controller
Page 1
The MT8202CG is a highly integrated chip with a cost-effective and high performance HDTV-ready solution for the flat panel TV manufacturers. It supports flat panel TV video/audio input and output formats and HDTV as well. The MT8202CG includes a 3D comb filter of the TV decoder retrieving the best video from composite signals and embedded HDTV/VGA decoders perfectly reproducing the high bandwidth input signals. A 24/16/8 bit digital port can accept a variety of external digital video inputs.
2nd generation motion-adaptive deinterlacer converts interlace to progressive video. In addition, a 2D graphic processor can overlay on-screen displays (OSD) on the progressive video. Advanced full function color processing with a full 10-bit path provides high-quality video contents. Two independent flexible scalers can simultaneously process two different video sources and provide the wide adoption for various flat panels.
An on-chip audio processor with a lip sync control decodes analog signals received from the tuner, delivering high-quality post-processed sound effect to customers. An on-chip microprocessor reduces the system BOM and shortens the schedule of UI design by high level C program.
FEATURES
Video Input Fully programmable eight composite/S-Video input pins Two component inputs with SDTV format and HDTV 480p/720p/1080i formats One VGA input including SOG signals up to SXGA (1280x1024x75Hz) DVI 24-bit RGB digital input CCIR-656/601 digital input
TV decoder Full 10-bit data path to enhance the video resolution and reduce digital truncation errors
PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43 and SECAM Automatic Luma/Chroma gain control Automatic TV standard detection 2nd generation NTSC/PAL motion-adaptive 3D comb filter with huge improvements Motion-adaptive 3D noise reduction Macrovision detection Adjustable horizontal delay for combination of SCART composite/RGB input
Video Processor Full 10-bit processing to enhance the video quality Advanced flesh tone and color processing Gamma/anti-Gamma correction Advanced Color Transient Improvement (CTI) 2D Peaking Advanced horizontal/vertical sharpness Saturation/hue adjustment Brightness and contrast adjustment Black level extender White peak level limiter Adaptive Luma/Chroma management Automatic film or video source detection 3:2/2:2 pull down source detection 2nd generation advanced motion-adaptive de-interlacing Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X Advanced linear and non-linear panoramic scaling Programmable zoom viewer Progressive scan output Picture-in-Picture (PIP) Picture-Outside-Picture (POP) Advanced dithering processing for flat panel display with 6/8/10-bit output Frame rate conversion; 50Hz to 75Hz
Audio DSP Supports BTSC/EIAJ/A2/NICAM decoders Stereo and SAP demodulations Noise reduction Mode selections (Main/SAP/Stereo)
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y programmable eiprogrammablns
Two component inTwo compo480p/720p/1080480p/720pOne VGA ne VG(1280x10(128DVI 2C
ive 3D noise reductie 3D noise ron detection
able horizontal delaorizmposite/RGB input posite/RGB inp
ideo Processor deo ProFull 10-bit prFull 10-bAdvancedAdvaGammGAd
MT8202CG PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Page 2
Pink noise and white noise generator EqualizerSub-woofer/Bass enhancement Noise automatic mute 3D surround processing with virtual surround Audio and video lip synchronization Supports reverberation
Audio Input/Output Decodes audio AF from the tuner Two-channel audio L/R digital line in 7.1-channel slave digital line in Including a full 7.1-channels digital output, two- channel bypass and two-channel headphone output Three embedded internal DAC outputs
DRAM Controller Supports up to 32MB SDR/DDR DRAM Supports 2x16-bit SDR/DDR bus interfaces A built-in programmable DRAM interface clock optimizes DRAM performance Programmable DRAM access cycle and refresh cycle timings Supports 3.3/2.5-V SDR/DDR Interfaces
Video Output TV patterns generator for testing Supports up to 1366 horizontal points 6/8/10-bit single channel or 6/8/10-bit dual channel LVDS output Supports mirror and upside down images
2D-Graphic/OSD processor
Two backend OSD planes at RGB domain and one OSD plane at YUV domain Supports Text/Bitmap decoder Supports line/rectangle/gradient fill Supports bitblt Supports color key function Supports clip mask Supports alpha blending with video output A 256/16/4/2-color bitmap-formatted OSD Automatic vertical scrolling of OSD images Supports OSD mirror and upside down images
Host Micro-controller Turbo 8032 micro-controller A built-in internal 373 and 8-bit programmable lower address port 2048-byte on-chip RAM Up to 4M bytes FLASH-programming interface Supports 5/3.3-Volt. FLASH interface Supports power-down mode Supports additional serial ports IR controls serial inputs Support two RS232 interfaces for external source communication Supports two PWM outputs A programmable GPIO setting for complex external device controls
Outline 388-pin BGA package 3.3/2.5/1.8-V operating voltages 0.18 m process
0-bit dual channel dual cha
own images mages
sor
o output putmatted OSD matted OSD
g of OSD images of OSD imand upside down imagd upside down
er r micro-controller ro-contro
n internal 373 and 8rnal 373 as port
48-byte on-chip RAM8-byte on-chip Up to 4M bytes FLAUp to 4M byteSupports 5/3.3-VSupporSupports powSupportsSupports SupIR coISu
MT8202CG PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Page 3
Functional Block Diagram
Analog Switch
Built-in analog switches connect to seventeen input signals and it is necessary to add external components and analog video multiplexes on the printed circuit board (PCB).
There are nine high-speed differential input pairs for three sets of YPRPB/VGA input signals.
The eight composite/S-Video input pins can be fully programmed to connect to any AV/S-Video inputs.
ADC/ Selected Source
The video ADC converts analog input signals to digital signals. The selected sources multiplex all inputs from digital and analog video ports and route them into data path.
Audio Interface
The audio interface accepts analog audio signals from the tuner, for example, AF. It also includes preprocessing circuit to filter the noise. Audio decoder decodes the BTSC or NICAM, and outputs high-quality sound with enhanced 3D surround post processing.
Embedded 7.1 channel digital audio input (slave) and 2 channels (master) digital audio inputs.
Embedded three high performance audio DACs.
DSP
HDMI Receiver
RGB
LVDS
PIP Select ADC
TVD
TVD
Selected Sources
MDDi Scalar
OSD
2D-G
DD
R/SD
R D
RA
M
AV/SV inputs X 8
YPbPr X2
8032
RG
B2Y
U
Tuner
Analog Sw
itch Color
Gamma
Audio I/F
Flash
LCD Panel Audio DAC
Audio AMP
nect to seventeen inpo seventeed (PCB).
peed differential inpudifferentia
site/S-Video input pite/S-Video inp
elected Source lected Source
video ADC converideo ADC coports and route them nd route th
Audio InterAudio
The audTAud
LVDS
alar
DD
R/SD
R
MP
MT8202CG PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Page 4
DSP
DSP implements audio decoding and intensive computing jobs. The downloadable micro-code enables fast functional convergence forvarious audio standards.
An advanced DSP engine supports full functions of sound effects.
MDDi/Scaler
MDDi is MediaTek’s proprietary de-interlacing technology. 2nd generation MDDi solution provides improved low angle processing and accurate motion detection for all interlaced sources. The techniques successfully reduce jagged edges and broken images. The MDDi engine supports both main and sub channel of SDTV inputs or one channel of 1080i high quality de-interlacing.
Two independent scalers support full functions of PIP/POP and frame rate conversion.
With MDDi and the high quality scalers, MT8202CG guarantees all input formats can be translated with the best video quality for motion and still pictures.
Color/Gamma
MT8202CG includes advanced color management function allowing users to improve video quality with full flexibility. With contrast/hue/saturation/Gamma/anti-Gamma/flesh tone functions, MT8202CG delivers the best video quality with lifelike color.
An advanced dither function supports 6/8/10-bit video output for any kinds of display unit (LCD, PDP, CRT).
8032
An on-chip Turbo8032 provides cost-effective environment for system house. Well-proven F/W can significantly ease the system design.
2D-G/OSD
On-chip graphic engine draws bitmap OSD and stores them into DRAM. OSD accesses data from DRAM and displays on the screen.
With 2D-G and OSD, the computing power requirement of P can be minimized.
This document contains information that is proprietary to MediaTek Inc. Unauthorized reproduction or disclosure of this information in whole or in part is prohibited
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GL850A USB 2.0 Low-Power HUB Controller
2000-2005 Genesys Logic Inc. - All rights reserved. Page 9
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinouts
GL850A
LQFP - 48
AV
DD
1
AG
ND
2
DM
03
DP0
4
DM
15
DP1
6
AV
DD
7
AG
ND
8
DM
29
DP2
10
RR
EF11
AV
DD
12
AM
BER
2/E
E_D
I
GR
EEN
2/EE
_DO
DV
DD
DG
ND
AM
BER
3
GR
EEN
3
NC
TEST
RES
ET#
DV
DD
DG
ND
AM
BER
4
36 35 34 33 32 31 30 29 28 27 26 25
PSELF 37
DGND 38
DVDD 39
PGANG/SUSPND 40
OVCUR1# 41
PWREN1# 42
DGND 43
DVDD 44
GREEN1/EE_SK 45
AMBER1/EE_CS 46
DGND 47
DVDD 48
GREEN4
DP4
DM4
AGND
AVDD
DP3
DM3
AGND
AVDD
X2
X1
AGND
24
23
22
21
20
19
18
17
16
15
14
13
Figure 3.1 GL850A 48 Pin LQFP Pinout Diagram
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3.2 Pin List
Table 3.1 GL850A 48 Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type1 AVDD P 13 AGND P 25 AMBER4 O 37 PSELF I
2 AGND P 14 X1 I 26 DGND P 38 DGND P
3 DM0 B 15 X2 O 27 DVDD P 39 DVDD P
4 DP0 B 16 AVDD P 28 RESET# I 40 PGANG/SUSPND B
5 DM1 B 17 AGND P 29 TEST I 41 OVCUR1# I
6 DP1 B 18 DM3 B 30 NC - 42 PWREN1# O
7 AVDD P 19 DP3 B 31 GREEN3 O 43 DGND P
8 AGND P 20 AVDD P 32 AMBER3 O 44 DVDD P
9 DM2 B 21 AGND P 33 DGND P 45 GREEN1/EE_SK B
10 DP2 B 22 DM4 B 34 DVDD P 46 AMBER1/EE_CS B
11 RREF B 23 DP4 B 35 GREEN2/EE_DO B 47 DGND P
12 AVDD P 24 GREEN4 O 36 AMBER2/EE_DI B 48 AVDD P
Table 3.2 GL850A 64 Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1 AGND P 17 RREF B 33 NC - 49 AMBER2/EE_DI B
2 NC - 18 AVDD P 34 GREEN4 O 50 PSELF I
3 DM0 B 19 AGND P 35 AMBER4 O 51 DGND P
4 DP0 B 20 X1 I 36 DGND P 52 DVDD P
5 NC - 21 X2 O 37 DVDD P 53 PGANG/SUSPND B
6 NC - 22 AVDD P 38 RESET# I 54 OVCUR2# I
7 NC - 23 AGND P 39 TEST I 55 PWREN2# O
8 DM1 B 24 NC - 40 OVCUR4# I 56 OVCUR1# I
9 DP1 B 25 DM3 B 41 PWREN4# O 57 PWREN1# O
10 NC - 26 DP3 B 42 OVCUR3# I 58 DGND P
11 AVDD P 27 NC - 43 PWREN3# O 59 DVDD P
12 AGND P 28 AVDD P 44 GREEN3 O 60 GREEN1/EE_SK B
13 NC - 29 AGND P 45 AMBER3 O 61 AMBER1/EE_CS B
14 DM2 B 30 NC - 46 DGND P 62 DGND P
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15 DP2 B 31 DM4 B 47 DVDD P 63 AVDD P
16 NC - 32 DP4 B 48 GREEN2/EE_DO B 64 AVDD P
3.3 Pin Descriptions
Table 3.3 - Pin Descriptions
USB Interface
GL850APin Name
48Pin# 64 Pin#I/O Type Description
DM0,DP0 3,4 3,4 B USB signals for USPORT
DM1,DP1 5,6 8,9 B USB signals for USPORT1
DM2,DP2 9,10 14,15 B USB signals for USPORT2
DM3,DP3 18,19 25,26 B USB signals for USPORT3
DM4,DP4 22,23 31,32 B USB signals for USPORT4
RREF 11 17 B A 680 resister must be connected between RREF andanalog ground (AGND).
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer toGL850A Design Guideline.
HUB Interface
GL850APin Name
48Pin# 64 Pin#I/O Type Description
OVCUR1#~4 41 56,54,42,40
I(pu)
Active low. Over current indicator for DSPORT1~4OVCUR1# is the only over current flag for GANGmode.
PWREN1#~4 42 57,55,43,41 O
Active low. Power enable output for DSPORT1~4PWREN1# is the only power-enable output for GANGmode.
GREEN1~4 45,35,31,24
60,48,44,34
O(pd)
Green LED indicator for DSPORT1~4*GREEN[1~2] are also used to access the external EEPROMFor detailed information, please refer to Chapter 5.
AMBER1~4 46,36,32,25
61,49,45,35
O(pd)
Amber LED indicator for DSPORT1~4*Amber[1~2] are also used to access the external EEPROM
EE_CS/EE_DI - - I Used to access the external EEPROM.
For detailed information, please refer to Chapter 5.
PSELF 37 50 I 0: GL850A is bus-powered.1: GL850A is self-powered.
PGANG/SUSPND 40 53 B
This pin is default put in input mode after power-onreset. Individual/gang mode is strapped during thisperiod. After the strapping period, this pin will be set to
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2000-2005 Genesys Logic Inc. - All rights reserved. Page 13
output mode, and then output high for normal mode.When GL850A is suspended, this pin will output low.*For detailed explanation, please see Chapter 5Input: 0: individual, 1: gangOutput: 0: suspend, 1: normal
Clock and Reset Interface
GL850APin Name
48Pin# 64Pin#I/O Type Description
X1 14 20 I 12MHz crystal clock input.
X2 15 21 O 12MHz crystal clock output.
RESET# 28 38 IActive low. External reset input, default pull high 10K .When RESET# = low, whole chip is reset to the initialstate.
System Interface
GL850APin Name
48Pin# 64 Pin#I/O Type Description
TEST 29 39 I(pd)
0: Normal operation.1: Chip will be put in test mode.
Power / Ground
GL850APin Name
48Pin# 64 Pin#I/O Type Description
AVDD 1,7,12,16,20
11,18,22,28,64 P 3.3V analog power input for analog circuits.
AGND 2,8,13,17,21
1,12,19,23,29 P Analog ground input for analog circuits.
DVDD 27,34,39,44
37,47,52,59 P 3.3V digital power input for digital circuits
DGND26,33,38,
43,47
36,46,51,58,62 P Digital ground input for digital circuits.
NC 30
2,5~7,10,13,16,24,27,30,33
- No connection
Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the powerrouting and the ground plane. For detailed information, please refer to GL850A Design Guideline.
Notation:Type O Output
I InputB Bi-directionalB/I Bi-directional, default inputB/O Bi-directional, default outputP Power / Ground
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A AnalogSO Automatic output low when suspendpu Internal pull uppd Internal pull downodpu Open drain with internal pull up
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CHAPTER 4 BLOCK DIAGRAM
FRTIMERUSPORT
Transceiver
RAM
CPU
Control/Status
RegisterUTMI
USPORT
LogicSIE
D+ D-
GPIO
REPEATER
REPEATER / TT Routing Logic
DSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 Logic
DSPORT
Transceiver
DSPORT DSPORT DSPORT
12MHz
D+ D- LED/OVCUR/PWRENB
D+ D- LED/OVCUR/PWRENB
D+ D- LED/OVCUR/PWRENB
D+ D- LED/OVCUR/PWRENB
TT (Transaction Translator)
PLL
x40, x10
Transceiver Transceiver Transceiver
ROM
Figure 4.1 GL850A Block Diagram (single TT)
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CHAPTER 5 FUNCTION DESCRIPTION
5.1 General
5.1.1 USPORT TransceiverUSPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speedelectrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver willoperate in full-speed electrical signaling when GL850A is plugged into a 1.1 host/hub. USPORT transceiverwill operate in high-speed electrical signaling when GL850A is plugged into a 2.0 host/hub.
5.1.2 PLL (Phase Lock Loop)GL850A contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks areproven quite accurate that help in generating high speed signal without jitter.
5.1.3 FRTIMERThis module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub s localclock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame(SOF). FRTIMER keeps tracking the host s SOF such that GL850A is always safely synchronized to thehost. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.
5.1.4 CC is the micro-processor unit of GL850A. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM.
It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares thedata to respond to the host. In addition, C can handle GPIO (general purpose I/O) settings and readingcontent of EEPROM to support high flexibility for customers of different configurations of hub. Theseconfigurations include self/bus power mode setting, individual/gang mode setting, downstream port numbersetting, device removable/non-removable setting, and PID/VID setting.
5.1.5 UTMI (USB 2.0 Transceiver Macrocell Interface)UTMI handles the low level USB protocol and signaling. It s designed based on the Intel s UTMIspecification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZIencoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.
5.1.6 USPORT logicUSPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. Itmainly manipulates traffics in the upstream direction. The main functions include the state machines ofReceiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATERand TT.
5.1.7 SIE (Serial Interface Engine)SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with cto play the role of the hub kernel. The main functions of SIE include the state machine of USB protocolflow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing isimplemented in UTMI, not in SIE.
5.1.8 Control/Status registerControl/Status register is the interface register between hardware and firmware. This register contains theinformation necessary to control endpoint0 and endpoint1 pipelines. Through the firmware basedarchitecture, GL850A possesses higher flexibility to control the USB protocol easily and correctly.
5.1.9 REPEATERRepeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specificationRevision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signalingin the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup eventis issued under the situation that hub is globally suspended.
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5.1.10. TT (Transaction Translator)TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TTbasically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS(operating in FS/LS) of hub. GL850A adopts the single TT architecture to provide the most cost effectivesolution. Single TT shares the same buffer control module for each downstream port. GL852 adoptsmultiple TT architecture to provide the most performance effective solution. Multiple TT provides controllogics for each downstream port respectively. Please refer to GL852 datasheet for more detailedinformation.
5.1.11 REPEATER/TT routing logicREPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation thatUSPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the trafficchannel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is inthe full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.
5.1.11.1 Connected to 1.1 Host/HubIf an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passingthrough REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to theREPEATER.
USB1.1 HOST/HUB
REPEATER TT
DSPORT operatingin FS/LS signaling
USPORToperatingin FS signaling
Traffic channelis routed toREPEATER
Figure 5.1 Operating in USB 1.1 scheme
5.1.11.2 Connected to USB 2.0 Host/HubIf an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream portsignaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel willthen be routed to the REPEATER when the device connected to the downstream port is signaling also inhigh speed. On the other hand, the traffic channel will then be routed to TT when the device connected tothe downstream port is signaling in full/low speed.
AML3278 A/V Processor User Guide Version 0.71
12/21/2005 5/40 Amlogic Proprietary
1 Introduction The AML3278 A/V processor is a completely integrated system targeting all types of Audio/Video decoder applications that provide connectivity to hard disk, digital camera, MP3 players and other external digital consumer devices. The target market for AML3278 A/V processor is feature rich DVD players, audio receivers, DVD/receiver combo players, digital media players, integrated TV media players, portable DVD players, and portable media players.
The AML3278 combines full function of MPEG-1, MPEG-2 and MPEG-4 decoding, numerous dedicated and general-purpose peripherals, and a high speed 32-bit host CPU in a single device. The AML3278 has three built-in AMRISCTM RISC processors with special instructions to accommodate audio, video and servo-loop digital signal processing. The AML3278 also provides a high speed interface to external USB 1.1/2.0 chip for connectivity to popular USB devices like hard disk, Flash memory, and digital camera and MP3 players.
The embedded 32-bits host CPU handles system initialization, DVD navigation, and other system applications. The AML3278 A/V processor provides a glueless interface to all external components: ATAPI loaders, USB interface chip, HDMI transmitter chip, audio DACs and memory. Numerous general-purpose I/O pins can be used to control the front panel display and other miscellaneous tasks. Together, the embedded host CPU and special glueless interfaces reduce the total system cost for all A/V applications from any media.
The AML3278 A/V processor features a sophisticated video sub-system that performs video enhancement and scaling functions. It supports DVD up-scaling capabilities to 720p and 1080i resolutions for the TV system. In addition, a digital TV interface is created for connecting to external HDMI or DVI transmitter for 100% digital solution between the DVD and TV systems. The digital TV interface is designed to work with a companion HDMI transmitter (AML3505) to drive the serial HDMI/DVI signals.
The video sub-system also integrates an NTSC/PAL TV encoder for traditional analog video outputs like S-Video, composite, YUV component, RGB and multiple VGA modes. The video encoder also supports high-quality de-interlaced progressive scan (480p/576p) with full Macrovision support. Contrast enhancement, hue adjustment, video scaling, video interpolation, pan-scan, letter-box, and zoom are also supported. In addition, four built in video DACs complement the video encoder further reducing system cost.
The integrated Audio AMRISCTM RISC processor performs advanced digital audio decoding and post-processing. The micro-coded engine provides support for all existing audio formats and it also has enough flexibility to accommodate new audio standards. Popular audio formats like MPEG, LPCM, Dolby AC-3 5.1, HDCD, MP-3 and WMA are supported. In addition, SPDIF (IEC958) input and outputs are supported. AML3278 also supports the MLP loss-less compression and PCM format for DVD-Audio with sample rate up to 192 KHz for two channels and 96 KHz for multi-channels.
Since AML3728 supports DVD-Audio, the Audio AMRISC processor also supports MLP and high sample rate PCM audio formats.
The USB interface provides the necessary high speed interconnections to an external USB chip. The external USB chip can support up to 2 high-speed USB ports. The AML3278 firmware includes the basic USB device driver, USB protocol stacks to support bulk and INTR transfer, Hub, Mass-Storage (MS) class, Picture Transfer Protocol (PTP) and PictBridge protocol. The USB firmware also supports multiple file systems and includes flexible file transfer functions between USB devices.
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The AML3278 also integrates a flexible disc loader front-end with complete servo control, signal recovery, descrambling, and error detection and correction. The analog front-end features high resolution ADC and DAC for servo control. A front-end optimized AMRISCTM RISC processor performs adaptive servo tracking algorithms and provides unique intelligence to work with disk media errors. The loader front-end is designed to work with a companion RF front-end chip (AML 3501) for interfacing to an OPU.
The adaptive AMPOWER-I algorithm is integrated into both the chip design and the firmware to reduce power consumption for portable applications. AMPOWER-I also provides higher performance within smaller, thermally constrained environments.
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2 Features The AML3278 chip is very flexible and most of the capabilities are under firmware control. The following list of features may or may not be included in the firmware library or binary, depending on the actual application and platform.
High Integration o Embedded 32-bits RISC processor for system control o Integrated disc servo front-end with complete servo control, signal recovery,
descrambling, and error detection and correction o Glueless interface to dual ports USB controller o Complete MPEG 1/2/4 decoding backend and video post processing logic o Complete audio decoding backend o Integrated TV encoder and Video DACs
MPEG 1/2 Decoding o MPEG video engine controlled by dedicated Video AMRISCTM processor o MPEG-2 ML/MP conforming to ISO-13818 o MPEG-1 ML/MP conforming to ISO-11172 o On-chip CSS descrambler o Compliant with DVD Specification 1.0 for read-only Disc decoding o DVD Sub-picture and highlight decoding and display o Advanced error detection, concealment, and recovery scheme o Backward compatible VCD (1.0 to 3.0) decoding o Super VCD decoding
MPEG 4 Decodingo MPEG-4 and DivX 3.x/4.x/5.x compliant o GMC and Q-Pel compatible o Digital Right Management (DRM) engine for content management o Multiple language DivX sub-title support
Video Processingo 3:2 pull-down for 24 fps displaying at 30 fps o 2:2 pull-down for 24 fps displaying at 25 fps o Automatic frame rate adoption when playing non-DVD/VCD contents (like .mpg and .avi
files)o Adaptive pixel-based de-interlacing algorithm o Variable steps video zooming (up to 8x) o Letterboxi and pan/scan o Special trick modes:
Pause, single-step slow motion reverse playback Multiple steps fast forward/backward
o Built-in NTSC to PAL scaling or vice-versa o On-Screen-Display (OSD) capable of supporting up to 256 fixed colors or 16
programmable colors o OSD alpha-blending over video display
TV Encodero Interlaced NTSC output 720x480 at 30 fps, with Macrovision 7.1L1 anti-taping o Interlaced PAL output 720x576 at 25 fps, with Macrovision 7.1L1 anti-taping
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o Progressive NTSC output 480p at 60 fps, with Macrovision 1.03 anti-taping o Progressive PAL output 576p at 50 fps, with Macrovision 1.03 anti-taping o High definition output of 720p and 1080i at 50/60 fps o VGA output for computer monitors and LCD panels. VGA (640x480), SVGA (800x600),
XVGA (1024x768) and SXVGA (1280x1024) are supported o Interlaced S-Video, component, composite and SCART output o Simultaneous output of progressive and interlaced video o Closed caption modulation in the vertical blanking intervals o WSS/CMGS insertion o CCIR656 and CCIR 601 YCbCr output digital LCD panel connections o Full resolution (up to 1920x1080i) digital video output for HDMI/DVI connection o Programmable tint, brightness and other TV enhancements
Graphics o Graphics engine supports JPEG and BMP image decoding o Graphics can be scaled independently of the video output o Unified MPEG video and graphics memory architecture for maximum flexibility and
system cost savings
Audio Decoding o Built-in Audio AMRISCTM processor with extensions specifically designed for audio
processing o On-the-fly switching of audio streams during playback o Full MPEG audio layers I, II and III o Compliant with Dolby AC-3 5.1 channel decoding o DVD-Audio with full CPPM processing o HDCD support o MP3 music CD/DVD support o WMA music CD/DVD support
Audio Post Processing and Output o Supports 8 channels linear PCM output. I2S or EIAJ DAC-compatible o IEC958 (S/PDIF) digital output o DTS audio pass-through o AC-3 two channels down-mixing o Virtual surround sound to create 3-D spatial sound field from two audio channels o Prologic II to convert stereo audio source to multi-channel audio output o Full speaker configurations and bass management with adjustable crossover settings o Muting, volume control, etc. o Karaoke functions like integrated echo control and key control.
Audio Input o IEC958 (S/PDIF) digital input with frame decoding to accommodate A/V receiver
applications o PWM signals for tracking clock difference for external audio inputs o Two channels analog audio input
Front-end Loader Interface and Control o Direct interface to AML3501 Front-End RF device for DVD/CD loader support o DSP servo control with adaptive servo tracking algorithm o Support up to 6x DVD speed and 24x CD speed o Supported medias:
DVD-Video (from DVD-ROM. DVD±R and DVD±R/W) VCD and DVCD (from CD-ROM, CD±R and CD±RW)
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SVCD (from CD-ROM, CD±R and CD±RW) CD-DA and HDCD (CD-ROM, CD±R and CD±RW) DualDisc, Enhanced CD and Hyper CD DivX video (from all CD and DVD medias) JPEG and BMP (from all CD and DVD medias) MP3 and WMA (from all CD and DVD medias)
Front-End Loader Read-channel o Read-channel support for all popular CD/DVD formats o Intelligent sync detection and correction logic o Integrated multi-pass ECC engine o Digital over-sampling slicer
Front-End RF support (via AML3501 RF Front-End Device) o Support AGC and equalizer/filter for CD and DVD medias o 70 KHz bandwidth for the focus, tracking and pull-in circuits o Programmable input gain control amplifiers o Servo algebra signals used for optical alignment, seeking, focusing, and tracking o 50 MHz channels o Supports individual RF inputs for DVD (differential or single ended) and CD (single ended) o Programmable attenuator o Programmable boost/equalization o Less than 2% total harmonic distortion o No external filter components required o Auto laser power control o Programmable power management support (AMPOWER-I)
USB Interface o Glueless USB interface to external USB controller o Support dual ports USB 1.1 or USB 2.0 interface o Device mode, host mode, and OTG interfaces o DMA support for data movement for BULK, INTR and ISO transfer o USB device driver, native USB protocol stack supported in firmware o Integrated support for Mass-storage class (MS-Class), Picture Transfer Protocol (PTP)
and PictBridge protocol o USB Hub support o Video, audio and image decoding from USB attached MS-Class or PTP devices o Photo printing to USB attached PictBridge devices
IDE Hard Disk Interface o Direct interface to IDE hard drive for mass storage o Provides MP3 ripping to hard disk for up to 192kbps o Allows transfer of files between internal hard disk and external USB devices o Video, audio and image decoding from hard disk o Master/Slave mode support
Host CPU Sub-system o 32-bit CPU dedicated for user applications o Embedded debug interface using ICE/JTAG o Shared MPEG SDRAM as run time data storage for minimal system cost
System, Peripherals and Interfaces o Single 27 MHz clock input or crystal oscillator input o Optional audio PLL input for high precision audio applications
AML3278 A/V Processor User Guide Version 0.71
12/21/2005 10/40 Amlogic Proprietary
o AMPOWER-I power/frequency control algorithm for portable applications o Supports 8 or 16-bit FLASH o Support 16-bit SDRAM for front-end, MPEG, audio and host CPU o Numerous programmable GPIO pins for system control and interrupts o 1.2 volt and 3.3 volt power supplies o 5 volt TTL level I/O support o Small 256 pins PQFP package
