MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1 ... · EEM (S: 3+1) Comp_E (up to 16 inputs) FRAM 64KB 32KB RAM 2KB Power Mgmt LDO SVS Brownout SMCLK ACLK MDB MAB HFXIN HFXOUT Spy-Bi

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820

SLASE23E –JANUARY 2015–REVISED AUGUST 2018

MSP430FR697x(1), MSP430FR687x(1), MSP430FR692x(1), MSP430FR682x(1)Mixed‑‑Signal Microcontrollers

1 Device Overview

1

1.1 Features1

(1) The RTC is clocked by a 3.7-pF crystal.

• Embedded Microcontroller– 16-Bit RISC Architecture up to 16-MHz Clock– Wide Supply Voltage Range From 3.6 V Down

to 1.8 V (Minimum Supply Voltage is Restrictedby SVS Levels, See the SVS Specifications)

• Optimized Ultra-Low-Power Modes– Active Mode: Approximately 100 µA/MHz– Standby (LPM3 With VLO): 0.4 µA (Typical)– Real-Time Clock (RTC) (LPM3.5):

0.35 µA (Typical) (1)– Shutdown (LPM4.5): 0.04 µA (Typical)

• Ultra-Low-Power Ferroelectric RAM (FRAM)– Up to 64KB of Nonvolatile Memory– Ultra-Low-Power Writes– Fast Write at 125 ns per Word (64KB in 4 ms)– Unified Memory = Program, Data, and Storage

in One Single Space– 1015 Write Cycle Endurance– Radiation Resistant and Nonmagnetic

• Intelligent Digital Peripherals– 32-Bit Hardware Multiplier (MPY)– Three-Channel Internal Direct Memory Access

(DMA)– RTC With Calendar and Alarm Functions– Five 16-Bit Timers With up to Seven

Capture/Compare Registers– 16-Bit and 32-Bit Cyclic Redundancy Checker

(CRC16, CRC32)• High-Performance Analog

– Up to 8-Channel Analog Comparator– 12-Bit Analog-to-Digital Converter (ADC) With

Internal Reference and Sample-and-Hold andup to 8 External Input Channels

– Integrated 116-Segment LCD Driver WithContrast Control

• Code Security and Encryption– 128-Bit or 256-Bit AES Security Encryption and

Decryption Coprocessor (MSP430FR69xx(1)Only)

– True Random Number Seed for RandomNumber Generation Algorithm

– Lockable Memory Segments for IPEncapsulation and Secure Storage

• Multifunction Input/Output Ports– All I/O Pins Support Capacitive Touch Capability

Without Need for External Components– Accessible Bit-, Byte- and Word-Wise (in Pairs)– Edge-Selectable Wakeup From LPM on Ports

P1 to P4– Programmable Pullup and Pulldown on All Ports

• Enhanced Serial Communication– eUSCI_A0 and eUSCI_A1 Support:

– UART With Automatic Baud-Rate Detection– IrDA Encode and Decode– SPI at Rates up to 10 Mbps

– eUSCI_B0 and eUSCI_B1 Support:– I2C With Multiple-Slave Addressing– SPI at Rates up to 10 Mbps

• Flexible Clock System– Fixed-Frequency DCO With 10 Selectable

Factory-Trimmed Frequencies– Low-Power Low-Frequency Internal Clock

Source (VLO)– 32-kHz Crystals (LFXT)– High-Frequency Crystals (HFXT)

• Development Tools and Software– Free Professional Development Environments

With EnergyTrace++™ Technology for PowerProfiling and Debugging

– Microcontroller Development Boards Available• Family Members

– Device Comparison Summarizes the AvailableVariants and Packages

• For Complete Module Descriptions, See theMSP430FR58xx, MSP430FR59xx, andMSP430FR6xx Family User's Guide

http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com/tool/ENERGYTRACEhttp://www.ti.com/lit/pdf/SLAU367http://www.ti.com/lit/pdf/SLAU367

2

MSP430FR6972, MSP430FR69721, MSP430FR6970, MSP430FR6872MSP430FR68721, MSP430FR6870, MSP430FR6922, MSP430FR69221MSP430FR6920, MSP430FR6822, MSP430FR68221, MSP430FR6820SLASE23E –JANUARY 2015–REVISED AUGUST 2018 www.ti.com

Submit Documentation FeedbackProduct Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721

MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221MSP430FR6820

Device Overview Copyright © 2015–2018, Texas Instruments Incorporated

1.2 Applications• Heat Cost Allocators• Utility Meters – Electricity, Water, and Gas• Thermostats

• Portable Medical Equipment• Sensor Management• Weigh Scales

1.3 DescriptionThis ultra-low-power MSP430FRxx FRAM microcontroller family consists of several devices featuringembedded nonvolatile FRAM, a 16-bit CPU, and different sets of peripherals targeted for variousapplications. The architecture, FRAM, and peripherals, combined with seven low-power modes, areoptimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a newnonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability andreliability of flash, all at lower total power consumption.

(1) For the most current part, package, and ordering information for all available devices, see the PackageOption Addendum in Section 9, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see theMechanical Data in Section 9.

Device Information (1)PART NUMBER PACKAGE BODY SIZE (2)

MSP430FR6972IPMR LQFP (64) 10 mm × 10 mmMSP430FR6972IRGC VQFN (64) 9 mm × 9 mmMSP430FR6922IG56 TSSOP (56) 6.1 mm × 14 mm

http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLASE23E&partnum=MSP430FR6972http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com

EEM

(S: 3+1)

Comp_E

(up to 16inputs)

FRAM

64KB32KB

RAM

2KB

PowerMgmt

LDOSVS

Brownout

SMCLK

ACLK

MDB

MAB

HFXOUTHFXIN

Spy-Bi-

Wire

CRC32

CRC-32-ISO-3309

CRC16

CRC-16-CCITT

BusControlLogic

MAB

MDB

MAB

MDB

MCLK

MPY32

AES256

SecurityEn-/De-cryption

(128/256)

ADC12_B

(up to 16std. inputs,

up to 8diff. inputs)

ClockSystem

CPUXV2incl. 16

Registers

JTAG

Interface

DMA

Controller

3 Channel

REF_A

VoltageReference

MPUIP Encap

TB0

Timer_B7 CC

Registers(int./ext.)

TA0

Timer_A3 CC


TA1

Timer_A3 CC


RTC_C

Calendarand

CounterMode

LCD_C

(up to116 seg;

static,2 to 4 mux)

eUSCI_A0eUSCI_A1

(UART,IrDA,SPI)

eUSCI_B0eUSCI_B1

(I C,SPI)

2

LPM3.5 Domain

P1.x,P2.x

I/O PortP5, P6

2x8 I/Os

PC1x16 I/Os

I/O PortP7

1x8 I/Os

PD1x8 I/Os

I/O PortP9

1x8 I/Os

PE1x8 I/Os

I/O PortPJ

1x8 I/Os

I/O PortsP3, P4

2x8 I/Os

PB1x16 I/Os

I/O PortsP1, P2

2x8 I/Os

PA1x16 I/Os

P9.x

up to1x8

PJ.x

Watchdog

TA2

Timer_A2 CC

Registers(int. only)

TA 3

Timer_A5 CC

Registers

Capacitive Touch IO 0, Capacitive Touch IO 1

P7.x

up to1x8

up to1x8

up to2x8

up to2x8

up to2x8

P3.x,P4.x P5.x,P6.x

LFXOUT,LFXIN,

Tiny RAM26B

Copyright © 2016, Texas Instruments Incorporated

3


www.ti.com SLASE23E –JANUARY 2015–REVISED AUGUST 2018



Device OverviewCopyright © 2015–2018, Texas Instruments Incorporated

1.4 Functional Block DiagramFigure 1-1 shows the functional block diagram.

NOTE: AES256 is not implemented in the MSP430FR682x, MSP430FR687x, MSP430FR682x1, and MSP430FR687x1devices.

NOTE: HFXIN and HFOUT are not implemented in the MSP430FR692x, MSP430FR682x, MSP430FR692x1, andMSP430FR682x1 devices.

Figure 1-1. Functional Block Diagram

http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLASE23E&partnum=MSP430FR6972http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820

4




Table of Contents Copyright © 2015–2018, Texas Instruments Incorporated

Table of Contents1 Device Overview ......................................... 1

1.1 Features .............................................. 11.2 Applications........................................... 21.3 Description............................................ 21.4 Functional Block Diagram ............................ 3

2 Revision History ......................................... 53 Device Comparison ..................................... 6

3.1 Related Products ..................................... 84 Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 94.2 Pin Attributes ........................................ 124.3 Signal Descriptions.................................. 184.4 Pin Multiplexing ..................................... 264.5 Buffer Type.......................................... 264.6 Connection of Unused Pins ......................... 26

5 Specifications ........................................... 275.1 Absolute Maximum Ratings ......................... 275.2 ESD Ratings ........................................ 275.3 Recommended Operating Conditions............... 275.4 Active Mode Supply Current Into VCC Excluding

External Current .................................... 285.5 Typical Characteristics - Active Mode Supply

Currents ............................................. 295.6 Low-Power Mode (LPM0, LPM1) Supply Currents

Into VCC Excluding External Current ................ 295.7 Low-Power Mode LPM2, LPM3, LPM4 Supply

Currents (Into VCC) Excluding External Current .... 305.8 Low-Power Mode With LCD Supply Currents (Into

VCC) Excluding External Current .................... 325.9 Low-Power Mode LPMx.5 Supply Currents (Into

VCC) Excluding External Current .................... 335.10 Typical Characteristics, Low-Power Mode Supply

Currents ............................................. 345.11 Typical Characteristics, Current Consumption per

Module .............................................. 355.12 Thermal Resistance Characteristics ................ 35

5.13 Timing and Switching Characteristics ............... 366 Detailed Description ................................... 64

6.1 Overview ............................................ 646.2 CPU ................................................. 646.3 Operating Modes .................................... 656.4 Interrupt Vector Table and Signatures .............. 676.5 Bootloader (BSL).................................... 706.6 JTAG Operation ..................................... 706.7 FRAM................................................ 716.8 RAM ................................................. 716.9 Tiny RAM............................................ 716.10 Memory Protection Unit (MPU) Including IP

Encapsulation ....................................... 716.11 Peripherals .......................................... 726.12 Device Descriptors (TLV) .......................... 1096.13 Memory ............................................ 1126.14 Identification........................................ 128

7 Applications, Implementation, and Layout ...... 1297.1 Device Connection and Layout Fundamentals .... 1297.2 Peripheral- and Interface-Specific Design

Information ......................................... 1338 Device and Documentation Support .............. 136

8.1 Getting Started and Next Steps ................... 1368.2 Device Nomenclature .............................. 1368.3 Tools and Software ................................ 1378.4 Documentation Support............................ 1398.5 Related Links ...................................... 1408.6 Community Resources............................. 1408.7 Trademarks ........................................ 1418.8 Electrostatic Discharge Caution ................... 1418.9 Export Control Notice .............................. 1418.10 Glossary............................................ 141

9 Mechanical, Packaging, and OrderableInformation ............................................. 142


5





Revision HistoryCopyright © 2015–2018, Texas Instruments Incorporated

2 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from January 25, 2017 to August 30, 2018 Page

• Updated Section 3.1, Related Products ........................................................................................... 8• Added note (1) to Table 5-2, SVS................................................................................................. 36• Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise Considerations ... 133• Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design Requirements .. 134• Updated text and figure in Section 8.2, Device Nomenclature .............................................................. 136


Copyright © 2015–2018, Texas Instruments IncorporatedDevice ComparisonSubmit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

6


3 Device Comparison

Table 3-1 and Table 3-2 summarize the available family members.

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, anumber sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM outputgenerators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, anumber sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM outputgenerators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.(4) eUSCI_B supports I2C with multiple slave addresses and SPI.(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and

FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

Table 3-1. Device Comparison – Family Members With UART BSL

DEVICE FRAM(KB)SRAM(KB)

CLOCKSYSTEM Timer_A

(1) Timer_B (2)eUSCI

AES ADC12_B LCD_C I/O PACKAGEA (3) B (4)

MSP430FR6972 64 2DCOHFXTLFXT

3, 3 (5)2, 5 (6) (7) 7 2 2 yes 8 ext 112 seg 51

64 PM64 RGC


3, 3 (5)2, 5 (6) (7) 7 2 2 no 8 ext 112 seg 51

64 PM64 RGC


3, 3 (5)2, 5 (6) (7) 7 2 2 yes 8 ext 112 seg 51

64 PM64 RGC


3, 3 (5)2, 5 (6) (7) 7 2 2 no 8 ext 112 seg 51

64 PM64 RGC

MSP430FR6922 64 2 DCOLFXT3, 3 (5)

2, 5 (6) (7) 7 2 2 yes 8 ext116 seg100 seg(DGG)

5246 (DGG)

64 PM64 RGC56 DGG

MSP430FR6822 64 2 DCOLFXT3, 3 (5)

2, 5 (6) (7) 7 2 2 no 8 ext116 seg100 seg(DGG)

5246 (DGG)

64 PM64 RGC56 DGG

MSP430FR6920 32 2 DCOLFXT3, 3 (5)


5246 (DGG)

64 PM64 RGC56 DGG

MSP430FR6820 32 2 DCOLFXT3, 3 (5)

2, 5 (6) (7) 7 2 2 no 8 ext116 seg100 seg(DGG)

5246 (DGG)

64 PM64 RGC56 DGG

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLASE23E&partnum=MSP430FR6972http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com

Copyright © 2015–2018, Texas Instruments Incorporated Device ComparisonSubmit Documentation Feedback

Product Folder Links: MSP430FR6972 MSP430FR69721 MSP430FR6970 MSP430FR6872 MSP430FR68721MSP430FR6870 MSP430FR6922 MSP430FR69221 MSP430FR6920 MSP430FR6822 MSP430FR68221

MSP430FR6820

7



(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, anumber sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM outputgenerators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, anumber sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM outputgenerators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.(4) eUSCI_B supports I2C with multiple slave addresses and SPI.(5) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.(6) Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).(7) Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR692x(1) and FR682x(1) with RGC and PM packages. For FR692x(1) and

FR682x(1) with DGG package and all other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).

Table 3-2. Device Comparison – Family Members With I2C BSL

DEVICE FRAM(KB)SRAM(KB)

CLOCKSYSTEM Timer_A

(1) Timer_B (2)eUSCI

AES ADC12_B LCD_C I/O PACKAGEA (3) B (4)


3, 3 (5)2, 5 (6) (7) 7 2 2 yes 8 ext 112 seg 51

64 PM64 RGC


3, 3 (5)2, 5 (6) (7) 7 2 2 no 8 ext 112 seg 51

64 PM64 RGC

MSP430FR69221 64 2 DCOLFXT3, 3 (5)


5246 (DGG)

64 PM64 RGC56 DGG

MSP430FR68221 64 2 DCOLFXT3, 3 (5)

2, 5 (6) (7) 7 2 2 no 8 ext116 seg100 seg(DGG)

5246 (DGG)

64 PM64 RGC56 DGG

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLASE23E&partnum=MSP430FR6972http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com

8




Device Comparison Copyright © 2015–2018, Texas Instruments Incorporated

3.1 Related ProductsFor information about other devices in this family of products or related products, see the following links.TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous

futureProducts for MSP430 ultra-low-power sensing and measurement microcontrollers One platform.

One ecosystem. Endless possibilities.Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power single-

chip MCUs with integrated sensing peripheralsCompanion Products for MSP430FR6972 Review products that are frequently purchased or used with

this product.Reference Designs for MSP430FR6972 The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TIexperts to help you jump start your system design, all TI Designs include schematic or blockdiagrams, BOMs, and design files to speed your time to market. Search and downloaddesigns at ti.com/tidesigns.

http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.comhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLASE23E&partnum=MSP430FR6972http://www.ti.com/product/msp430fr6972?qgpn=msp430fr6972http://www.ti.com/product/msp430fr69721?qgpn=msp430fr69721http://www.ti.com/product/msp430fr6970?qgpn=msp430fr6970http://www.ti.com/product/msp430fr6872?qgpn=msp430fr6872http://www.ti.com/product/msp430fr68721?qgpn=msp430fr68721http://www.ti.com/product/msp430fr6870?qgpn=msp430fr6870http://www.ti.com/product/msp430fr6922?qgpn=msp430fr6922http://www.ti.com/product/msp430fr69221?qgpn=msp430fr69221http://www.ti.com/product/msp430fr6920?qgpn=msp430fr6920http://www.ti.com/product/msp430fr6822?qgpn=msp430fr6822http://www.ti.com/product/msp430fr68221?qgpn=msp430fr68221http://www.ti.com/product/msp430fr6820?qgpn=msp430fr6820http://www.ti.com/microcontrollers/overview.htmlhttp://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/msp/products.page#http://www.ti.com/microcontrollers/msp430-ultra-low-power-mcus/ultrasonic-performance-sensing-mcus/products.htmlhttp://www.ti.com/product/MSP430FR6972#relProdshttp://www.ti.com/general/docs/refdesignsearchresults.tsp?keyword=MSP430FR6972http://www.ti.com/tidesigns

1P4.3/UCA0SOMI/UCA0RXD/UCB1STE

2P1.4/UCB0CLK/UCA0STE/TA1.0/S3

3P1.5/UCB0STE/UCA0CLK/TA0.0/S2

4P1.6/ TA0.1/S1UCB0SIMO/UCB0SDA/

5P1.7/ TA0.2/S0UCB0SOMI/UCB0SCL/

6R33/LCDCAP

7P6.0/R23

8P6.1/R13/LCDREF

9P6.2/COUT/R03

10P6.3/COM0

11P6.4/TB0.0/COM1/S31

12P6.5/TB0.1/COM2/S30

13P6.6/TB0.2/COM3/S29

14P3.0/UCB1CLK/S28

15P3.1/ S27UCB1SIMO/UCB1SDA/

16P3.2/ S26UCB1SOMI/UCB1SCL/

17

DV

SS

1

18

DV

CC

1

19

TE

ST

/SB

WT

CK

20

RS

T/N

MI/S

BW

TD

IO

21

PJ.0

/TD

O/T

B0O

UT

H/S

MC

LK

/SR

SC

G1

22

PJ.1

/TD

I/T

CLK

/MC

LK

/SR

SC

G0

23

PJ.2

/TM

S/A

CLK

/SR

OS

CO

FF

24

PJ.3

/TC

K/C

OU

T/S

RC

PU

OF

F

25

P3.3

/TA

1.1

/TB

0C

LK

/S25

26

P3.4

/UC

A1S

IMO

/UC

A1T

XD

/TB

0.0

/S24

27

P3.5

/UC

A1S

OM

I/U

CA

1R

XD

/TB

0.1

/S23

28

P3.6

/UC

A1C

LK

/TB

0.2

/S22

29

P3.7

/UC

A1S

TE

/TB

0.3

/S21

30

P2.3

/UC

A0S

TE

/TB

0O

UT

H/S

20

31

P2.2

/UC

A0C

LK

/TB

0.4

/RT

CC

LK

/S19

32

P2.1

/UC

A0S

OM

I/U

CA

0R

XD

/TB

0.5

/DM

AE

0/S

18

33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S17

34 P7.0/TA0CLK/S16

35 P7.1/TA0.0/ACLK/S15

36 P7.2/TA0.1/S14

37 P7.3/TA0.2/S13

38 P7.4/SMCLK/S12

39 DVSS2

40 DVCC2

41 P1.3/TA1.2/A3/C3

42 P1.2/TA1.1/TA0CLK/COUT/A2/C2

43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

45 P9.4/A12/C12

46 P9.5/A13/C13

47 P9.6/A14/C14

48 P9.7/A15/C15

49

AV

CC

1

50

AV

SS

1

51

PJ.4

/LF

XIN

52

PJ.5

/LF

XO

UT

53

AV

SS

2

54

P5.4

/UC

A1S

IMO

/UC

A1T

XD

/S11

55

P5.5

/UC

A1S

OM

I/U

CA

1R

XD

/S10

56P

5.6

/UC

A1C

LK

/S9

57P

5.7

/UC

A1S

TE

/TB

0C

LK

/S8

58

P4.4

/UC

B1S

TE

/TA

1C

LK

/S7

59

P4.5

/UC

B1C

LK

/TA

1.0

/S6

60

P4.6

/TA

1.1

/S5

UC

B1S

IMO

/UC

B1S

DA

/

61

P4.7

/TA

1.2

/S4

UC

B1S

OM

I/U

CB

1S

CL/

62

DV

SS

3

63

DV

CC

3

64

P4.2

/UC

A0S

IMO

/UC

A0T

XD

/UC

B1C

LK

MSP430FR692x

MSP430FR682x

9





Terminal Configuration and FunctionsCopyright © 2015–2018, Texas Instruments Incorporated

4 Terminal Configuration and Functions

4.1 Pin DiagramsFigure 4-1 show the pinout for the 64-pin PM and RGC packages of the MSP430FR692x(1) andMSP430FR682x(1) MCUs.

On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RXOn devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK

NOTE: TI recommends connecting the RGC package thermal pad to VSS.

Figure 4-1. 64-Pin PM and RGC Packages (Top View), MSP430FR692x(1) MSP430FR682x(1)


1P4.3/UCA0SOMI/UCA0RXD/UCB1STE/S4

2P1.4/UCB0CLK/UCA0STE/TA1.0/S3

3P1.5/UCB0STE/UCA0CLK/TA0.0/S2

4P1.6/ TA0.1/S1UCB0SIMO/UCB0SDA/

5P1.7/ TA0.2/S0UCB0SOMI/UCB0SCL/

6R33/LCDCAP

7P6.0/R23

8P6.1/R13/LCDREF

9P6.2/COUT/R03

10P6.3/COM0

11P6.4/TB0.0/COM1/S30

12P6.5/TB0.1/COM2/S29

13P6.6/TB0.2/COM3/S28

14P3.0/UCB1CLK/TA3.2/S27

15P3.1/ S26UCB1SIMO/UCB1SDA/TA3.3/

16P3.2/ S25UCB1SOMI/UCB1SCL/TA3.4/

17

DV

SS

1

18

DV

CC

1

19

TE

ST

/SB

WT

CK

20

RS

T/N

MI/S

BW

TD

IO

21

PJ.0

/TD

O/T

B0O

UT

H/S

MC

LK

/SR

SC

G1

22

PJ.1

/TD

I/T

CLK

/MC

LK

/SR

SC

G0

23

PJ.2

/TM

S/A

CLK

/SR

OS

CO

FF

24

PJ.3

/TC

K/C

OU

T/S

RC

PU

OF

F

25

P3.3

/TA

1.1

/TB

0C

LK

/S24

26

P3.4

/UC

A1S

IMO

/UC

A1T

XD

/TB

0.0

/S23

27

P3.5

/UC

A1S

OM

I/U

CA

1R

XD

/TB

0.1

/S22

28

P3.6

/UC

A1C

LK

/TB

0.2

/S21

29

P3.7

/UC

A1S

TE

/TB

0.3

/S20

30

P2.3

/UC

A0S

TE

/TB

0O

UT

H/S

19

31

P2.2

/UC

A0C

LK

/TB

0.4

/RT

CC

LK

/S18

32

P2.1

/UC

A0S

OM

I/U

CA

0R

XD

/TB

0.5

/DM

AE

0/S

17

33 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S16

34 P7.0/TA0CLK/S15

35 P7.1/TA0.0/ACLK/S14

36 P7.2/TA0.1/S13

37 P7.3/TA0.2/S12

38 P7.4/SMCLK/S11

39 DVSS2

40 DVCC2

41 P1.3/TA1.2/A3/C3

42 P1.2/TA1.1/TA0CLK/COUT/A2/C2

43 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

44 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-

45 P9.4/A12/C12

46 P9.5/A13/C13

47 P9.6/A14/C14

48 P9.7/A15/C15

49

AV

CC

1

50

AV

SS

1

51

PJ.4

/LF

XIN

52

PJ.5

/LF

XO

UT

53

AV

SS

2

54555657

P5.7

/UC

A1S

TE

/TB

0C

LK

/S10

58

P4.4

/UC

B1S

TE

/TA

1C

LK

/S9

59

P4.5

/UC

B1C

LK

/TA

1.0

/S8

60P

4.6

/TA

1.1

/S7

UC

B1S

IMO

/UC

B1S

DA

/61

P4.7

/TA

1.2

/S6

UC

B1S

OM

I/U

CB

1S

CL/

62

DV

SS

3

63

DV

CC

3

64

P4.2

/UC

A0S

IMO

/UC

A0T

XD

/UC

B1C

LK

/S5

MSP430FR697x

MSP430FR687x

AV

SS

3

PJ.7

/HF

XO

UT

PJ.6

/HF

XIN

10




Terminal Configuration and Functions Copyright © 2015–2018, Texas Instruments Incorporated

Figure 4-2 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR697x(1) andMSP430FR687x(1) MCUs.


NOTE: TI recommends connecting the RGC package thermal pad to VSS.

Figure 4-2. 64-Pin PM and RGC Packages (Top View) – MSP430FR697x(1), MSP430FR687x(1)


43

44

45

46

47

48

49

50

51

52

53

54

55

56

15

16

17

18

19

20

21

22

23

24

25

26

27

28

7

8

9

10

11

12

13

14

29

30

31

32

33

34

35

36

37

38

39

40

41

42

1

2

3

4

5

6

MSP430FR692x

MSP430FR682x

P1.4/UCB0CLK/UCA0STE/TA1.0/S3

P1.5/UCB0STE/UCA0CLK/TA0.0/S2

P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1

P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0

R33/LCDCAP

P6.0/R23

P6.1/R13/LCDREF

P6.2/COUT/R03

P6.3/COM0

P6.4/TB0.0/COM1/S27

P6.5/TB0.1/COM2/S26

P6.6/TB0.2/COM3/S25

P3.0/UCB1CLK/TA3.2/S24



DVSS2

DVCC2

TEST/SBWTCK

RST /NMI/SBWTDIO

PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1

PJ.1/TDI/TCLK/MCLK/SRSCG0

PJ.2/TMS/ACLK/SROSCOFF

PJ.3/TCK/COUT/SRCPUOFF

P3.3/TA1.1/TB0CLK/S21 P3.4/UCA1SIMO/UCA1TXD/TB0.0/S20

P3.5/UCA1SOMI/UCA1RXD/TB0.1/S19

P3.6/UCA1CLK/TB0.2/S18

P3.7/UCA1STE/TB0.3/S17

P2.3/UCA0STE/TB0OUTH/S16

P2.2/UCA0CLK/TB0.4/RTCCLK/S15

P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S14

P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S13

P7.0/TA0CLK/S12

P7.1/TA0.0/ACLK/S11

P7.2/TA0.1/S10

P7.3/TA0.2/S9

P7.4/SMCLK/S8

DVSS3

DVCC3

P1.3/TA1.2/A3/C3

P1.2/TA1.1/TA0CLK/COUT/A2/C2

P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+

P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREF-

AVCC1

AVSS1

PJ.4/LFXIN

PJ.5/LFXOUT

AVSS2P4.4/UCB1STE/TA1CLK/S7

P4.5/UCB1CLK/TA1.0/S6



P9.4/A12/C12

P9.5/A13/C13

P9.6/A14/C14

P9.7/A15/C15

11






Figure 4-3 shows the pinout for the 56-pin DGG package of the MSP430FR692x(1) andMSP430FR682x(1) MCUs.


Figure 4-3. 56-Pin DGG Package (Top View) – MSP430FR692x(1), MSP430FR682x(1)


12





(1) Signals names with (RD) denote the reset default pin name.(2) To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.(3) Sz = The LCD segment that is assigned to each pin can vary by package – see the "LCD SEG" columns for the assignment on this pin.(4) Signal Types: I = Input, O = Output, I/O = Input or Output.(5) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)(6) Reset States:

OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabledN/A = Not applicable

4.2 Pin AttributesTable 4-1 lists the attributes of each pin.

Table 4-1. Pin Attributes

FR692x(1), FR682x(1) FR697x(1),FR687x(1)SIGNAL NAME (1)

(2) (3)SIGNALTYPE (4)

BUFFERTYPE (5)

POWERSOURCE

RESETSTATEAFTERBOR (6)

PM, RGC DGG PM, RGCPINNO.

LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

1 1 S4

P4.3 (RD) I/O LVCMOS DVCC OFFUCA0SOMI I/O LVCMOS DVCC –UCA0RXD I LVCMOS DVCC –UCB1STE I/O LVCMOS DVCC –Sz O Analog DVCC –

2 S3 7 S3 2 S3

P1.4 (RD) I/O LVCMOS DVCC OFFUCB0CLK I/O LVCMOS DVCC –UCA0STE I/O LVCMOS DVCC –TA1.0 I/O LVCMOS DVCC –Sz O Analog DVCC –

3 S2 8 S2 3 S2

P1.5 (RD) I/O LVCMOS DVCC OFFUCB0STE I/O LVCMOS DVCC –UCA0CLK I/O LVCMOS DVCC –TA0.0 I/O LVCMOS DVCC –Sz O Analog DVCC –

4 S1 9 S1 4 S1

P1.6 (RD) I/O LVCMOS DVCC OFFUCB0SIMO I/O LVCMOS DVCC –UCB0SDA I/O LVCMOS DVCC –BSL_DAT I LVCMOS DVCC –TA0.1 I/O LVCMOS DVCC –Sz O Analog DVCC –

5 S0 10 S0 5 S0

P1.7 (RD) I/O LVCMOS DVCC OFFUCB0SOMI I/O LVCMOS DVCC –UCB0SCL I/O LVCMOS DVCC –BSL_CLK I LVCMOS DVCC –TA0.2 I/O LVCMOS DVCC –Sz O Analog DVCC –

6 11 6R33 I/O Analog DVCC –LCDCAP I/O Analog DVCC –

7 12 7P6.0 (RD) I/O LVCMOS DVCC OFFR23 I/O Analog DVCC –

8 13 8P6.1 (RD) I/O LVCMOS DVCC OFFR13 I/O Analog DVCC –LCDREF I Analog – –


13






Table 4-1. Pin Attributes (continued)



BUFFERTYPE (5)

POWERSOURCE



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

9 14 9P6.2 (RD) I/O LVCMOS DVCC OFFCOUT O LVCMOS DVCC –R03 I/O Analog DVCC –

10 15 10P6.3 (RD) I/O LVCMOS DVCC OFFCOM0 O Analog DVCC –

11 S31 16 S27 11 S30

P6.4 (RD) I/O LVCMOS DVCC OFFTB0.0 I/O LVCMOS DVCC –COM1 O Analog DVCC –Sz O Analog DVCC –

12 S30 17 S26 12 S29


13 S29 18 S25 13 S28


14 S28 19 S24 14 S27

P3.0 (RD) I/O LVCMOS DVCC OFFUCB1CLK I/O LVCMOS DVCC –TA3.2 I/O LVCMOS DVCC –Sz O Analog DVCC –

15 S27 20 S23 15 S26

P3.1 (RD) I/O LVCMOS DVCC OFFUCB1SIMO I/O LVCMOS DVCC –UCB1SDA I/O LVCMOS DVCC –TA3.3 I/O LVCMOS DVCC –Sz O Analog DVCC –

16 S26 21 S22 16 S25

P3.2 (RD) I/O LVCMOS DVCC OFFUCB1SOMI I/O LVCMOS DVCC –UCB1SCL I/O LVCMOS DVCC –TA3.4 I/O LVCMOS DVCC –Sz O Analog DVCC –

17 17 DVSS1 P Power – N/A18 18 DVCC1 P Power – N/A

19 22 19TEST I LVCMOS DVCC OFFSBWTCK I LVCMOS DVCC –

20 23 20RST I LVCMOS DVCC OFFNMI I LVCMOS DVCC –SBWTDIO I/O LVCMOS DVCC –

21 24 21

PJ.0 (RD) I/O LVCMOS DVCC OFFTDO O LVCMOS DVCC –TB0OUTH I LVCMOS DVCC –SMCLK O LVCMOS DVCC –SRSCG1 O LVCMOS DVCC –


14








BUFFERTYPE (5)

POWERSOURCE



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

22 25 22

PJ.1 (RD) I/O LVCMOS DVCC OFFTDI I LVCMOS DVCC –TCLK I LVCMOS DVCC –MCLK O LVCMOS DVCC –SRSCG0 O LVCMOS DVCC –

23 26 23

PJ.2 (RD) I/O LVCMOS DVCC OFFTMS I LVCMOS DVCC –ACLK O LVCMOS DVCC –SROSCOFF O LVCMOS DVCC –

24 27 24

PJ.3 (RD) I/O LVCMOS DVCC OFFTCK I LVCMOS DVCC –COUT O LVCMOS DVCC –SRCPUOFF O LVCMOS DVCC –

25 S25 28 S21 25 S24

P3.3 (RD) I/O LVCMOS DVCC OFFTA1.1 I/O LVCMOS DVCC –TB0CLK I LVCMOS DVCC –Sz O Analog DVCC –

26 S24 29 S20 26 S23

P3.4 (RD) I/O LVCMOS DVCC OFFUCA1SIMO I/O LVCMOS DVCC –UCA1TXD O LVCMOS DVCC –TB0.0 I/O LVCMOS DVCC –Sz O Analog DVCC –

27 S23 30 S19 27 S22

P3.5 (RD) I/O LVCMOS DVCC OFFUCA1SOMI I/O LVCMOS DVCC –UCA1RXD I LVCMOS DVCC –TB0.1 I/O LVCMOS DVCC –Sz O Analog DVCC –

28 S22 31 S18 28 S21

P3.6 (RD) I/O LVCMOS DVCC OFFUCA1CLK I/O LVCMOS DVCC –TB0.2 I/O LVCMOS DVCC –Sz O Analog DVCC –

29 S21 32 S17 29 S20

P3.7 (RD) I/O LVCMOS DVCC OFFUCA1STE I/O LVCMOS DVCC –TB0.3 I/O LVCMOS DVCC –Sz O Analog DVCC –

30 S20 33 S16 30 S19

P2.3 (RD) I/O LVCMOS DVCC OFFUCA0STE I/O LVCMOS DVCC –TB0OUTH I LVCMOS DVCC –Sz O Analog DVCC –

31 S19 34 S15 31 S18

P2.2 (RD) I/O LVCMOS DVCC OFFUCA0CLK I/O LVCMOS DVCC –TB0.4 I/O LVCMOS DVCC –RTCCLK O LVCMOS DVCC –Sz O Analog DVCC –


15









BUFFERTYPE (5)

POWERSOURCE



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

32 S18 35 S14 32 S17

P2.1 (RD) I/O LVCMOS DVCC OFFUCA0SOMI I/O LVCMOS DVCC –UCA0RXD I LVCMOS DVCC –BSL_RX I LVCMOS DVCC –TB0.5 I/O LVCMOS DVCC –DMAE0 I LVCMOS DVCC –Sz O Analog DVCC –

33 S17 36 S13 33 S16

P2.0 (RD) I/O LVCMOS DVCC OFFUCA0SIMO I/O LVCMOS DVCC –UCA0TXD O LVCMOS DVCC –BSL_TX O LVCMOS DVCC –TB0.6 I/O LVCMOS DVCC –TB0CLK I LVCMOS DVCC –Sz O Analog DVCC –

34 S16 37 S12 34 S15P7.0 (RD) I/O LVCMOS DVCC OFFTA0CLK I LVCMOS DVCC –Sz O Analog DVCC –

35 S15 38 S11 35 S14

P7.1 (RD) I/O LVCMOS DVCC OFFTA0.0 I/O LVCMOS DVCC –ACLK O LVCMOS DVCC –Sz O Analog DVCC –

36 S14 39 S10 36 S13P7.2 (RD) I/O LVCMOS DVCC OFFTA0.1 I/O LVCMOS DVCC –Sz O Analog DVCC –

37 S13 40 S9 37 S12P7.3 (RD) I/O LVCMOS DVCC OFFTA0.2 I/O LVCMOS DVCC –Sz O Analog DVCC –

38 S12 41 S8 38 S11P7.4 (RD) I/O LVCMOS DVCC OFFSMCLK O LVCMOS DVCC –Sz O Analog DVCC –

39 42 39 DVSS2 P Power – N/A40 43 40 DVCC2 P Power – N/A

41 44 41

P1.3 (RD) I/O LVCMOS DVCC OFFTA1.2 I/O LVCMOS DVCC –A3 I Analog AVCC –C3 I Analog AVCC –

42 45 42

P1.2 (RD) I/O LVCMOS DVCC OFFTA1.1 I/O LVCMOS DVCC –TA0CLK I LVCMOS DVCC –COUT O LVCMOS DVCC –A2 I Analog AVCC –C2 I Analog AVCC –


16








BUFFERTYPE (5)

POWERSOURCE



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

43 46 43

P1.1 (RD) I/O LVCMOS DVCC OFFTA0.2 I/O LVCMOS DVCC –TA1CLK I LVCMOS DVCC –COUT O LVCMOS DVCC –A1 I Analog AVCC –C1 I Analog AVCC –VREF+ O Analog AVCC –VeREF+ I Analog – –

44 47 44

P1.0 (RD) I/O LVCMOS DVCC OFFTA0.1 I/O LVCMOS DVCC –DMAE0 I LVCMOS DVCC –RTCCLK O LVCMOS DVCC –A0 I Analog AVCC –C0 I Analog AVCC –VREF- O Analog AVCC –VeREF- I Analog – –

45 48 45P9.4 (RD) I/O LVCMOS DVCC OFFA12 I Analog AVCC –C12 I Analog AVCC –




49 52 49 AVCC1 P Power – N/A50 53 50 AVSS1 P Power – N/A

51 54 51PJ.4 (RD) I/O LVCMOS DVCC OFFLFXIN I Analog AVCC –

52 55 52PJ.5 (RD) I/O LVCMOS DVCC OFFLFXOUT O Analog AVCC –

53 56 53 AVSS2 P Power – N/A

54PJ.7 (RD) I/O LVCMOS DVCC OFFHFXOUT O Analog AVCC –

55PJ.6 (RD) I/O LVCMOS DVCC OFFHFXIN I Analog AVCC –

56 AVSS3 P Power – N/A

54 S11

P5.4 (RD) I/O LVCMOS DVCC OFFUCA1SIMO I/O LVCMOS DVCC –UCA1TXD O LVCMOS DVCC –Sz O Analog DVCC –


17









BUFFERTYPE (5)

POWERSOURCE



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

55 S10

P5.5 (RD) I/O LVCMOS DVCC OFFUCA1SOMI I/O LVCMOS DVCC –UCA1RXD I LVCMOS DVCC –Sz O Analog DVCC –

56 S9P5.6 (RD) I/O LVCMOS DVCC OFFUCA1CLK I/O LVCMOS DVCC –Sz O Analog DVCC –

57 S8 57 S10

P5.7 (RD) I/O LVCMOS DVCC OFFUCA1STE I/O LVCMOS DVCC –TB0CLK I LVCMOS DVCC –Sz O Analog DVCC –

58 S7 1 S7 58 S9

P4.4 (RD) I/O LVCMOS DVCC OFFUCB1STE I/O LVCMOS DVCC –TA1CLK I LVCMOS DVCC –Sz O Analog DVCC –

59 S6 2 S6 59 S8

P4.5 (RD) I/O LVCMOS DVCC OFFUCB1CLK I/O LVCMOS DVCC –TA1.0 I/O LVCMOS DVCC –Sz O Analog DVCC –

60 S5 3 S5 60 S7

P4.6 (RD) I/O LVCMOS DVCC OFFUCB1SIMO I/O LVCMOS DVCC –UCB1SDA I/O LVCMOS DVCC –TA1.1 I/O LVCMOS DVCC –Sz O Analog DVCC –

61 S4 4 S4 61 S6

P4.7 (RD) I/O LVCMOS DVCC OFFUCB1SOMI I/O LVCMOS DVCC –UCB1SCL I/O LVCMOS DVCC –TA1.2 I/O LVCMOS DVCC –Sz O Analog DVCC –

62 5 62 DVSS3 P Power – N/A63 6 63 DVCC3 P Power – N/A

64 64 S5

P4.2 (RD) I/O LVCMOS DVCC OFFUCA0SIMO I/O LVCMOS DVCC –UCA0TXD O LVCMOS DVCC –UCB1CLK I/O LVCMOS DVCC –Sz O Analog DVCC –


18





4.3 Signal DescriptionsTable 4-2 describes the signals.

Table 4-2. Signal Descriptions

FUNCTION SIGNALNAME

FR692x(1), FR682x(1) FR697x(1),FR687x(1)SIGNAL

TYPE DESCRIPTIONPM, RGC DGG PM, RGCPINNO.

LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

ADC

A0 44 47 44 I Analog input A0A1 43 46 43 I Analog input A1A2 42 45 42 I Analog input A2A3 41 44 41 I Analog input A3A12 45 48 45 I Analog input A12A13 46 49 46 I Analog input A13A14 47 50 47 I Analog input A14A15 48 51 48 I Analog input A15VREF+ 43 46 43 O Output of positive reference voltageVREF- 44 47 44 O Output of negative reference voltage

VeREF+ 43 46 43 I Input for an external positive referencevoltage to the ADC

VeREF- 44 47 44 I Input for an external negative referencevoltage to the ADC

BSL (I2C)BSL_CLK 5 10 5 I BSL clock (I2C BSL)BSL_DAT 4 9 4 I/O BSL data (I2C BSL)

BSL (UART)BSL_RX 32 35 32 I BSL receive (UART BSL)BSL_TX 33 36 33 O BSL transmit (UART BSL)

Clock

ACLK 23352638

2335 O ACLK output

HFXIN 55 I Input terminal of crystal oscillator XT2HFXOUT 54 O Output terminal for crystal oscillator XT2LFXIN 51 54 51 I Input terminal for crystal oscillator XT1LFXOUT 52 55 52 O Output terminal of crystal oscillator XT1MCLK 22 25 22 O MCLK output

RTCCLK 31443447

3144 O RTC clock output for calibration

SMCLK 21382441

2138 O SMCLK output

Comparator

C0 44 47 44 I Comparator input C0C1 43 46 43 I Comparator input C1C2 42 45 42 I Comparator input C2C3 41 44 41 I Comparator input C3C12 45 48 45 I Comparator input C12C13 46 49 46 I Comparator input C13C14 47 50 47 I Comparator input C14C15 48 51 48 I Comparator input C15

COUT

9244243

14274546

9244243

O Comparator output


19






Table 4-2. Signal Descriptions (continued)

FUNCTION SIGNALNAME



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

Debug

SBWTCK 19 22 19 I Spy-Bi-Wire input clockSBWTDIO 20 23 20 I/O Spy-Bi-Wire data input/output

SRCPUOFF 24 27 24 O Low-power debug: CPU status registerCPUOFF

SROSCOFF 23 26 23 O Low-power debug: CPU status registerOSCOFF

SRSCG0 22 25 22 O Low-power debug: CPU status registerSCG0

SRSCG1 21 24 21 O Low-power debug: CPU status registerSCG1TCK 24 27 24 I Test clockTCLK 22 25 22 I Test clock inputTDI 22 25 22 I Test data inputTDO 21 24 21 O Test data output port

TEST 19 22 19 I Test mode pin - select digital I/O on JTAGpinsTMS 23 26 23 I Test mode select

DMA DMAE0 32443547

3244 I DMA external trigger input

GPIO

P1.0 44 47 44 I/O General-purpose digital I/OP1.1 43 46 43 I/O General-purpose digital I/OP1.2 42 45 42 I/O General-purpose digital I/OP1.3 41 44 41 I/O General-purpose digital I/OP1.4 2 7 2 I/O General-purpose digital I/OP1.5 3 8 3 I/O General-purpose digital I/OP1.6 4 9 4 I/O General-purpose digital I/OP1.7 5 10 5 I/O General-purpose digital I/OP2.0 33 36 33 I/O General-purpose digital I/OP2.1 32 35 32 I/O General-purpose digital I/OP2.2 31 34 31 I/O General-purpose digital I/OP2.3 30 33 30 I/O General-purpose digital I/OP3.0 14 19 14 I/O General-purpose digital I/OP3.1 15 20 15 I/O General-purpose digital I/OP3.2 16 21 16 I/O General-purpose digital I/OP3.3 25 28 25 I/O General-purpose digital I/OP3.4 26 29 26 I/O General-purpose digital I/OP3.5 27 30 27 I/O General-purpose digital I/OP3.6 28 31 28 I/O General-purpose digital I/OP3.7 29 32 29 I/O General-purpose digital I/O


20






FUNCTION SIGNALNAME



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

GPIO

P4.2 64 64 I/O General-purpose digital I/OP4.3 1 1 I/O General-purpose digital I/OP4.4 58 1 58 I/O General-purpose digital I/OP4.5 59 2 59 I/O General-purpose digital I/OP4.6 60 3 60 I/O General-purpose digital I/OP4.7 61 4 61 I/O General-purpose digital I/OP5.4 54 I/O General-purpose digital I/OP5.5 55 I/O General-purpose digital I/OP5.6 56 I/O General-purpose digital I/OP5.7 57 57 I/O General-purpose digital I/OP6.0 7 12 7 I/O General-purpose digital I/OP6.1 8 13 8 I/O General-purpose digital I/OP6.2 9 14 9 I/O General-purpose digital I/OP6.3 10 15 10 I/O General-purpose digital I/OP6.4 11 16 11 I/O General-purpose digital I/OP6.5 12 17 12 I/O General-purpose digital I/OP6.6 13 18 13 I/O General-purpose digital I/OP7.0 34 37 34 I/O General-purpose digital I/OP7.1 35 38 35 I/O General-purpose digital I/OP7.2 36 39 36 I/O General-purpose digital I/OP7.3 37 40 37 I/O General-purpose digital I/OP7.4 38 41 38 I/O General-purpose digital I/OP9.4 45 48 45 I/O General-purpose digital I/OP9.5 46 49 46 I/O General-purpose digital I/OP9.6 47 50 47 I/O General-purpose digital I/OP9.7 48 51 48 I/O General-purpose digital I/OPJ.0 21 24 21 I/O General-purpose digital I/OPJ.1 22 25 22 I/O General-purpose digital I/OPJ.2 23 26 23 I/O General-purpose digital I/OPJ.3 24 27 24 I/O General-purpose digital I/OPJ.4 51 54 51 I/O General-purpose digital I/OPJ.5 52 55 52 I/O General-purpose digital I/OPJ.6 55 I/O General-purpose digital I/OPJ.7 54 I/O General-purpose digital I/O

I2C

UCB0SCL 5 10 5 I/O USCI_B0: I2C clock (I2C mode)UCB0SDA 4 9 4 I/O USCI_B0: I2C data (I2C mode)

UCB1SCL 1661214

1661 I/O USCI_B1: I

2C clock (I2C mode)

UCB1SDA 1560203

1560 I/O USCI_B1: I

2C data (I2C mode)


21







FUNCTION SIGNALNAME



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

LCD

COM0 10 15 10 O LCD common output COM0 for LCDbackplane



COM3 13 18 13 O LCD common output COM3 for LCDbackplaneLCDCAP 6 11 6 I LCD capacitor connection

LCDREF 8 13 8 I External reference voltage input forregulated LCD voltage

R03 9 14 9 I/O Input/output port of lowest analog LCDvoltage (V5)

R13 8 13 8 I/O Input/output port of third most positiveanalog LCD voltage (V3 or V4)

R23 7 12 7 I/O Input/output port of second most positiveanalog LCD voltage (V2)

R33 6 11 6 I/O Input/output port of most positive analogLCD voltage (V1)


22






FUNCTION SIGNALNAME



LCDSEG

PINNO.

LCDSEG

PINNO.

LCDSEG

LCD Sz

1 S4 O

LCD segment output (package specific)

64 S5 O5 S0 10 S0 5 S0 O4 S1 9 S1 4 S1 O3 S2 8 S2 3 S2 O2 S3 7 S3 2 S3 O

61 S4 4 S4 61 S6 O60 S5 3 S5 60 S7 O59 S6 2 S6 59 S8 O58 S7 1 S7 58 S9 O57 S8 57 S10 O56 S9 O55 S10 O54 S11 O38 S12 41 S8 38 S11 O37 S13 40 S9 37 S12 O36 S14 39 S10 36 S13 O35 S15 38 S11 35 S14 O34 S16 37 S12 34 S15 O33 S17 36 S13 33 S16 O32 S18 35 S14 32 S17 O31 S19 34 S15 31 S18 O30 S20 33 S16 30 S19 O29 S21 32 S17 29 S20 O28 S22 31 S18 28 S21 O27 S23 30 S19 27 S22 O26 S24 29 S20 26 S23 O25 S25 28 S21 25 S24 O16 S26 21 S22 16 S25 O15 S27 20 S23 15 S26 O14 S28 19 S24 14 S27 O13 S29 18 S25 13 S28 O12 S30 17 S26 12 S29 O11 S31 16 S27 11 S30 O

Power

AVCC1 49 52 49 P Analog power supplyAVSS1 50 53 50 P Analog ground supplyAVSS2 53 56 53 P Analog ground supplyAVSS3 56 P Analog ground supplyDVCC1 18 18 P Digital power supplyDVCC2 40 43 40 P Digital power supplyDVCC3 63 6 63 P Digital power supplyDVSS1 17 17 P Digital ground supplyDVSS2 39 42 39 P Digital ground supplyDVSS3 62 5 62 P Digital ground supply

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