MRO Fast Tip-Tilt...1.0 2011-07-15 CAH Final tweeks to request suggested by DFB. First release. Objective To assess the suitability of an Andor iXon X3 897 camera for the Magdalena

MRO Fast Tip-Tilt

Andor iXon X3 897 Custom Clocking Evaluation

MRO-TRE-CAM-1120-0118

Bodie Seneta, Alex Rea and Chris [email protected]@[email protected]

rev 1.015 July 2011

Cavendish LaboratoryMadingley Road

Cambridge CB3 0HEUK

Change Record

Revision Date Authors Changes0.1 2011-03-30 EBS First draft.0.2 2011-06-10 EBS Second draft, using results from purchased

camera.0.3 2011-06-26 EBS Complete rework including fix to very bad

noise calculation error and new centroid testresults.

0.4 2011-07-04 EBS Centroid analysis reworked for consistencybetween real data and theory. Many minorcorrections.

0.5 2011-07-08 CAH Corrections to centroid analysis and pho-ton rates (fig 5 revised). Reorganised sec-tions. Finalised conclusions and recommen-dations. Additional minor stylistic correc-tions.

0.6 2011-07-14 CAH/JSY Corrections to many sections via DFBs com-ments. Revised recommendations. Updatedfigures.

1.0 2011-07-15 CAH Final tweeks to request suggested by DFB.First release.

Objective

To assess the suitability of an Andor iXon X3 897 camera for the Magdalena RidgeObservatory Interferometer fast tip-tilt (FTT) system when the camera has beenupgraded with a trial customised fast CCD readout mode written by Andor. Re-sults using the standard readout mode are included for comparison.

Reference Documents

RD1 MRO-TRE-CAM-0000-0101: Derived Requirements – rev 1.0, August 31st2010

Scope

This document forms part of the documentation for the fast tip-tilt system to bedeveloped for and installed at the Magdalena Ridge Observatory Interferometer.It describes tests undertaken to evaluate the performance of a customised CCDclocking scheme devised by Andor for their iXon X3 897 camera, under condi-tions similar to those to be encountered in operation.

1

It is assumed that the reader is familiar with the astronomical concept of stellarmagnitudes, as well as readout methods for charge coupled devices (CCDs) andelectron multiplying CCDs (EMCCDs) in particular.

2

Contents

1 Introduction 4

2 Conventional and Custom Clocking Schemes 5

2.1 Conventional Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Custom Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Experimental Layout 7

4 Assessing the Impact of Noise on Centroiding Performance 9

5 Description of Tests 9

6 Test Results 10

6.1 Readout latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2 Qualitative Image Fidelity . . . . . . . . . . . . . . . . . . . . . . . . 11

6.3 Dark Frame Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.3.1 Effects of clocking scheme and parallel clock voltage . . . . 12

6.3.2 Effect of temperature on custom clocking . . . . . . . . . . . 16

6.3.3 Effects of integration time on custom clocking . . . . . . . . 17

6.4 Illumination Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4.1 Effect of using a faint strobed source during custom clocking 18

6.4.2 Effects of clocking scheme on centroiding accuracy . . . . . 18

7 Summary 22

8 Recommendations 22

8.1 Change in basic readout strategy . . . . . . . . . . . . . . . . . . . . 22

8.2 Mode switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.3 Proposal for way forward . . . . . . . . . . . . . . . . . . . . . . . . 24

3

1 Introduction

The FTT system for the Magdalena Ridge Observatory Interferometer is requiredto image a celestial source, calculate the position of this image, and move a com-pensating mirror — with minimal latency — to correct for the tilt component ofthe wavefront perturbations introduced by the atmosphere. Hence the image sen-sor component will form the detection element of a servo system. Some relevantrequirements for the imaging sensor (RD1) include:

• A minimum size of the rapidly read out sub-frame of 3.6 × 3.6 arc-secondson the sky;

• The ability to centre this sub-frame anywhere within 10 arc-seconds of thecenter of a total field of view of 60× 60 arc-seconds.

• The need for a closed-loop bandwidth of 40 Hz, with a goal of 50 Hz. Thisbandwidth requirement need not be met for the faintest specified targets(16th magnitude). For these faintest targets RD1 suggests a closed loopbandwidth of around 15 Hz.

Since RD1 was written, the optical design of the fast-tip-tilt (FTT) system has beenfrozen, and the pixel scale of the camera has been fixed at 0.147 arc-seconds perpixel. This implies that the sub-frame size must be at least as large as 25 × 25pixels, and that a detector with dimensions of at least 408 × 408 pixels will beneeded. Furthermore, the camera readout latency has been measured which hasallowed us to establish a minimum frame rate requirement (see Subsection 6.1).

It is clear from vendor literature that the iXon X3 897 camera meets the sub-framesize requirement in principle, but the determination of its ability to meet the otherrequirements requires further testing. The conventional “region of interest” (ROI)readout available with the camera allows for a centrally placed sub-frame of ade-quate size to be read out at roughly 500Hz, but the readout latency is too long toallow our closed-loop bandwidth requirement to be met.

In order to deal with this problem, Andor has written a trial customised fastclocking scheme for evaluation. This custom scheme minimises the number ofserial shifts needed to get the data from the ROI out of the chip at the expenseof some contamination in the images from light outside the ROI. This was feltto be a reasonable approach because the typical number of stars in the 60 × 60arc-second field of view is expected to be no more than one or two in all cases.

This report summarises the tests we have carried out to determine whether thiscustom clocking mode meets the requirements of the FTT system. Where possiblewe have repeated the tests using the conventional ROI readout so as to act as acomparison, and to assess whether this mode could act as a suitable fall-back forsituations where a lower closed-loop bandwidth (i.e. 15 Hz) were acceptable.

Three kinds of tests were carried out:

• Latency measurements, to establish the required minimum frame rates;

4

• Dark frame tests, in which no external light was allowed to reach the cam-era, thereby allowing assessment of the array’s noise performance;

• Illuminated tests, in which an image of a point source was focused on theCCD. The source was either steady, or strobed in synchronisation with cam-era frames to simulate a rapidly moving image. These tests allowed assess-ment of the centroiding accuracy as a function of signal level.

For all the tests a range of CCD temperature and clocking voltage parameterswere explored.

Our overall conclusion is that both the custom and the conventional ROI clock-ing schemes produce centroid errors of similar magnitude for the signal levelstested. The standard ROI readout does not meet our latency requirement butthe custom readout mode does. However, a number of features of the customreadout scheme still require modification and these are reported in Section 8

The reader should note that the results in this document are not an official en-dorsement or detraction of Andor’s products, and no guarantee is made that ourinterpretation of Andor’s custom clocking scheme is correct.

2 Conventional and Custom Clocking Schemes

A clocking scheme is the sequence of voltages applied to a CCD in order to movethe charge in the pixels to a pre-amplifier, where it can be measured and digitised.The Andor X3 897 camera uses an E2V CCD97 chip [1], which allows considerableflexibility in how this is done. In particular, it is not necessary to clock out everypixel in the CCD if one is only interested in a subregion of the array.

For the purposes of this memorandum, two clocking schemes were investigated:conventional ROI clocking and a faster custom clocking scheme developed byAndor to meet our high frame readout requirement. The following two subsec-tions present our current understanding of how each of these clocking strategieswere implemented. Should these summary descriptions be inaccurate, we wouldwelcome clarification.

2.1 Conventional Clocking

In conventional ROI mode our understanding is that the charge in the CCD imagesection is firstly parallel-shifted into the CCD storage section, which can be inde-pendently clocked out while the image section begins exposure of a new image.The charge in the region of interest is then parallel-shifted towards the readoutregister, with all the pixel rows prior to the first row containing the ROI beingdiscarded. The CCD rows that contain the region of interest are then read outand digitised. Although all the row values are read out, only those pixels withinthe ROI are subsequently made available to the user.

The following aspects of this “standard” readout mode are worth noting:

5

1. Because every pixel in any row containing the region of interest in read out,there is no time penalty associated with increasing the width of the ROI.

2. Conversely, this scheme is inefficient if the width of the region of interest issmall compared to the full CCD width, because a large fraction of time willbe spent clocking out and reading pixels outside the ROI.

3. Within the readout register, charge generated by the exposure in any pixelnever gets added to the charge in any other pixel, so there is never ambi-guity as to where on the CCD image section the charge that is eventuallydigitised came from.

In our lab tests with the Andor X3 897, we found that that a 23 × 23 sub-framecentred on the 512× 512 pixel light-sensitive region of the chip could be read outat around 520 Hz.

2.2 Custom Clocking

The customised clocking scheme tested was based upon a proposal to Andor byour team, further refined through face-to-face and on-line discussions betweenthe two groups.

It is our understanding that in this scheme, and as before, the exposed CCD pix-els are all first shifted to the storage region. Subsequently, all the rows prior tothe first containing the ROI are shifted into the readout register, read, and thesevalues discarded. Then, the first row containing data of interest is clocked intothe readout register. However, instead of then reading out this whole row, thereadout register is only clocked along by the width of the ROI. The next row isthen clocked into the readout register, which places the charge from the pixelsof interest in the most recent row of the ROI adjacent to those pixels from theprevious ROI row. This process is repeated until charge from all the pixels fromthe region of interest are stored entirely within the readout register. Finally, thewhole of the serial readout register is read out a single time so as to obtain thepixel values for the ROI in a sequential form.

Once again, there are a number of aspects of this custom readout mode worthnoting:

1. This clocking scheme minimises the number of serial clock shifts requiredto get the data out of the ROI, greatly decreasing the acquisition latency. Forregions of interest whose width is a small fraction of the full CCD width, thesaving in time is considerable.

2. The primary penalty of this strategy is that as each new row is shifted intothe output register, charge from pixels outside the ROI gets summed withcharges from earlier rows of the ROI that have previously been dumped intothe serial register. The charge from such pixels is expected to be small due tothe high probability that the rest of the chip contains no other sources, but

6

any target-independent charge, e.g. arising from thermally induced fluc-tuations or clock-induced charge effects, will contribute to this “spuriousbackground”

3. The size of the region of interest is limited by the length of the readoutregister. We believe that in the case of the iXon X3 it was this that led to thecustom region of interest being fixed at 23× 23 pixels.

The trial custom readout scheme was limited to a region of interest that was dis-placed 100 pixels in the serial and parallel shift directions from the origin of thelight-sensitive area of the chip. In our lab tests with the Andor X3 897, we foundthat this 23× 23 sub-frame could be read out at approximately 1500 Hz, i.e. somethree times faster than with the conventional ROI readout.

3 Experimental Layout

The experimental apparatus used for our tests consisted of an iXon X3 897 cameraat one end of an optical table and a light source at the other. The tests wereconducted in a darkened room, and where possible cardboard sheets were usedto shield the experiment from any stray ambient light.

The camera (Figure 1, left) was attached by its front plate to a custom mount sim-ilar to the mount proposed for the fast tip-tilt system. The imaging optic was acommercial telephoto lens, which was adjusted to produce an image of the lightsource with a Gaussian profile and FWHM of 3.75 pixels. This was broadly sim-ilar to what would be expected of a real star when focused onto the FTT sensorat one of the MROI unit telescopes. The lens was stopped down to f/32 to re-duce the input light level to one comparable to those likely to be encountered inpractice.

The light source (Figure 1, right) used was an Avago Technologies HLMP-6000-F0010 light emitting diode (LED), chosen for its rapid 15 ns response time, peak

Figure 1: Left: The Andor camera in its custom mount, facing the light source atthe far end of the optical table. Right: The LED light source (mounted on the bluebreadboard) with its neutral density attenuators in front.

7

Figure 2: Circuit schematic for the strobed light source.

wavelength of 640 nm (at which the CCD has a quantum efficiency of 95%) andcircular, diffused face. It could be completely turned on or off between one cam-era exposure and the next. The LED was wired with additional circuitry onto abreadboard that could be moved horizontally via a micrometer gauge. This al-lowed the image of the source on the CCD to be moved by calibrated sub-pixeldistances for testing the effects of the different readout modes on the centroiderror.

The circuitry driving the LED (see figure 2) was simple. The camera FIRE linesignalled the beginning of an exposure [2] and this signal was input to a pairof D flip-flops wired as a two bit counter. The counter lines in turn fed a NORgate, which only went high when the inputs were both low — that is, for onecycle in every four of the counter. The NOR gate provided sufficient power tolight the LED via a current limiting resistor. This provided more than sufficientillumination for the camera: in fact a 4.1 neutral density filter was necessary toreduce the illumination to the levels we would expect from the faintest observableobjects expected in astronomical use.

The camera was driven by a host computer running Windows 7 and Andor’sSolis software to acquire the data reported on in this memorandum. For eachacquisition, 1000 consecutive sub-frames were acquired and saved on the localhard disc as a FITS image stack. Two frame rates were tested: 300 Hz and 1000 Hz.The first of these is the rate suggested in RD1 as that likely to be used for theobservation of the faintest sources, whereas the second was used to establish howwell the hardware performed at the highest frame rates. Analysis of the imagedata was carried out with the FITS analysis programs Spydr and ImageJ, as wellas in-house coded Python scripts.

8

4 Assessing the Impact of Noise on Centroiding Per-formance

In order to assess the impact of the two clocking schemes on the image qualitydelivered by the Andor camera a fixed light source was used to illuminate theCCD so as to mimic a stellar image with a FWHM of 3.75 pixels. The RMS quad-cell centroid “jitter” as measured from 1000 consecutive image frames was thenused as a metric to assess the level of noise in the image data.

It is well known (see RD1 and references therein) that the RMS one-axis centroidjitter derived from a sequence of noisy images can be written as 1:

σjitter =3π

16

1

SNRFWHM , (1)

where SNR is the signal to noise ratio and FWHM is the full-width at half maxi-mum intensity of the assumed diffraction-limited image. The reader should notethat since the test image was not a diffraction-limited Airy pattern but closer to aGaussian, this formula will be inaccurate at some level.

The SNR, allowing for electron multiplying gain noise, is given by:

SNR =N√

2N + nσr2(2)

where N is the number of photons detected per image frame, n is the number ofpixel reads, and σr is the effective readout noise (referred to the electron multiply-ing input). The factor of 2 under the square root represents the noise introducedby the stochastic nature of the electron multiplying process.

For the test camera with a pre-amplifier gain of 5.2× and a 100 ns serial shift pe-riod, the readout noise is specified as∼ 52 electrons. The faintest observing targetexpected for the MROI FTT system is a 16th magnitude star, which correspondsto a detected flux at the FTT sensor of roughly 11400 photons per second. Finally,the centroid method used for the tests employed a 10× 10 pixel quad cell, and sothe appropriate value for n was 100.

These equations and data allowed us to predict the centroid jitter expected due toreadout noise, stochastic electron multiplication noise, and the Poisson fluctua-tions in the incident light signal. The extent to which the measured centroid jitterexceeded these predictions was used to assess whether or not additional sourcesof noise were present in the image data.

5 Description of Tests

A range of tests were conducted to compare the performance of the conventionaland custom clocking schemes, in order to determine whether the custom schemewas suitable for the fast tip-tilt project. This set of tests comprised:

1The two-axis jitter will be√2 greater than this.

9

1. Latency measurements, to establish the required minimum frame rate;

2. Qualitative image fidelity tests imaging a steady source, as a function ofclocking scheme, parallel clock voltage and parallel clock rate;

3. Measurements of dark frame quality as a function of clocking scheme, par-allel clock voltage and parallel clock rate;

4. Measurements of dark frame quality in the custom clocking scheme as afunction of temperature;

5. Measurements of dark frame quality in the custom clocking scheme as afunction of integration time;

6. Checks for residual charge in the custom clocking scheme using a faintstrobed source.

7. Checks of the centroiding accuracy for faint sources, with both conventionaland custom clocking.

All the tests took place between the 1st and the 21st of June, 2011.

6 Test Results

6.1 Readout latency

RD1 states that the total exposure lag (half the exposure time, plus the readouttime, the centroid computation time and the mirror actuation time) should not in-troduce a servo phase lag of more than 25◦. For servo bandwidths of 50Hz, 40Hzand 15Hz (Section 1) the corresponding allowed time lags are 1.39 ms, 1.74 msand 4.63 ms.

The centroid computation time and mirror actuation time were not measured aspart of these tests, but were conservatively estimated to take 0.1 ms in total. This,together with the measured readout latency, was used to estimate the maximumexposure time and hence the minimum frame rate requirements.

In this first test, the camera FIRE signal and the DMA transfer interrupt on thecamera PCI card were connected to an oscilloscope for monitoring the readoutlatency. The camera FIRE signal goes from high to low at the end of an exposure,while the interrupt line goes low when the data has been transferred to computermemory and is available for processing. Hence the time between these two eventscould be used to measure the readout latency.

As mentioned earlier, the test sub-frame was a 23 × 23 region displaced 100 pix-els in the serial and parallel shift directions from the origin of the light-sensitivearea of the chip. Readout times for both the conventional and custom clockingschemes were measured. The camera parallel and serial clock periods for this

10

test were set to 500 ns and 100 ns respectively. For this sub-frame size and loca-tion, the conventional and custom readout times were measured to be 1.85 msand 0.69 ms respectively.

If we assume a minimum exposure time equal to the readout time, we can see thatconventional ROI readout scheme will not allow closed loop bandwidths of 50 Hzor 40 Hz to be met, while the custom clocking scheme does. These tests confirmthat the trial custom clocking scheme can deliver the servo bandwidth that werequire, but that conventional ROI readout can only meet the needs of the lowest15 Hz closed-loop bandwidth that is compatible with faint source sensing.

6.2 Qualitative Image Fidelity

The qualitative fidelity of an image of a faint, steady source was investigated as afunction of the parallel clocking voltage for both the conventional and customisedclocking schemes. In Andor’s programming interface, the parallel clock voltagecan be set to values of “Normal” (“0”) though to “4”, with “4” being the highest.A higher value improves the ability of the camera to shift charge from one row tothe next, but it also causes the generation of additional clock-induced charge.

In our tests, the following parameters were held constant:

• CCD temperature = −80◦C;

• EMCCD gain = 250 & Pre-amp gain = 5.2×;

• Frame rate = 300 Hz;

• Serial clock period = 100 ns (the minimum available);

• Sub-frame size 23× 23 pixels & Sub-frame position (100, 100).

The pre-amp gain setting was chosen to minimise the readout noise, which shouldhave been ∼ 52 electrons per pixel for these settings. The EMCCD gain andframe rate were chosen to be those values suggested in RD1 for observations ofthe faintest required targets. The parallel clock periods were restricted to 300 nsand 500 ns, the shortest available, as our latency requirement implies the readoutmust be as fast as possible, but results were secured for all five parallel clock volt-age settings to see which gave better image quality. Our results are displayed inTable 1.

The most striking result observed was that no images were seen for a parallelclock period of 300 ns and a parallel clock voltage of 0 or 1, regardless of whetherconventional or custom clocking was used. It appears that parallel clock voltagesof less than “2” were not sufficient to shift charge from the exposure region intothe serial register at this clock rate. Clock voltages of “2” or higher producedimages for both readout schemes, although images acquired via custom clockinghad slightly more background noise, and this noise increased with parallel clockvoltage.

11

Clock Sequence Clock Voltage0 1 2 3 4

Conventional, 300 ns

Custom, 300 ns


Custom, 500 ns

Table 1: Typical images as a function of parallel clock voltage, clocking scheme,and parallel clock period. An identical colour mapping has been applied to allimages so as to allow straightforward comparison. Note that for the shortestclocking times of 300 ns, a clock voltage of at least 2 was necessary to transfercharge out of the CCD at all.

In contrast, when a 500 ns parallel clock period was used, an image was seen forevery clock voltage setting. For both conventional and custom clocking, the noisewas seen to increase with increasing clock voltage, with more noise apparent inthe custom case.

These results were useful for constraining the parameter space requiring furtherinvestigation. If 300 ns clocking is used, clock voltages of “0” or “1” cannot beused. It is also apparent that of the remaining options, the noise can be minimisedby using the lowest clock voltage available.

6.3 Dark Frame Quality

6.3.1 Effects of clocking scheme and parallel clock voltage

In these tests, the parameter space outlined in Subsection 6.2 above was exploredwith no light falling on the image sensor. In each case an image stack of 1000frames was acquired. Each stack was processed to give an average value perpixel. This emphasised any systematic artifacts introduced by either clockingscheme. Our results are shown in Table 2.

Significant systematic artifacts were visible for both the conventional and customclocking schemes. With conventional clocking, there were vertical bands evidentat the left and right of each average image. In the custom clocking scheme, thepattern was quite different, consisting of a darker vertical band on the left and a

12

Clock Sequence Clock Voltage0 1 2 3 4


Custom, 300 ns


Custom, 500 ns

Table 2: Dark-frame averages of 1000 frames as a function of parallel clock volt-age, parallel clock period, and clocking scheme. The colour mapping is the samefor all images and ranges from 85 to 110 counts.

bright horizontal region towards the top, and this pattern became more dominantwith increasing clocking voltage. In both cases, we believe that the systematicoffset is likely due to charge from pixels outside the region of interest gettingsummed with charge from pixels inside it. Even if those external pixels are un-illuminated, they can still carry thermally- and clock-induced charges.

In the case of conventional clocking, it is assumed that the charges contained inany light-sensitive pixels never get summed together. However, there are masked“guard pixels” surrounding the light-sensitive CCD region, which are used tocalibrate the background level, and it is possible that these are the source of thebands seen in Table 2.

The origin of artifacts seen when the custom clocking mode was used is less clear.We investigated one possible source by way of a numerical simulation in whichevery pixel of a “virtual” CCD was given a charge value of “1”, and this chipwas then clocked out according to the custom clocking scheme. During this pro-cedure, as noted in Subsection 2.2, charges from other nearby pixels get “addedinto” the pixels of interest within the serial register. Our simulation calculated thefinal charge values for each pixel in the output image, or equivalently, the num-ber of pixels that had been summed into each output image pixel, by the time itwould have been read out.

Figure 3 compares the result of this simulation with our real averaged dark framedata, and it is clear that there is qualitatively good agreement between the two.The surprise from the simulation is how much charge from extraneous pixels getssummed into the output image. Every image pixel in the final ROI appears to bethe sum of charges from at least four pixels (at the lower left), and up to twenty-

13

4

23

Figure 3: A comparison of our custom clocking simulation with real dark framedata. Left, simulation showing the number of CCD pixels that get summed intoeach image pixel. Right, a real 1000 frame dark average at “+3” clocking voltage.

three pixels towards the upper left of the ROI. In an ideal CCD at the MROI, thiswould not matter, as we expect the field to be mainly dark (i.e. with only a singletarget in the full field of view) and any additional pixels should thus contributeno charge. However, in reality there appears to be a roughly equal “non-target-related” contribution from every pixel in the CCD in our dark frames.

This contribution is unlikely to be thermal dark current, because the thermal con-tribution is only expected to be 0.001 electrons per pixel per second under ourmeasurement conditions. Nor can it be readout noise, because that is only addedon readout and does not depend on how the pixels are summed beforehand.

A remaining possible noise source is clock-induced charge, and we believe thismay be the likely candidate. Our understanding is that clock-induced chargeevents occur when the shifting of charges between pixels generates one or moreadditional electrons. This can occur randomly in any pixel, and increases as theclock voltage increases (as occurs in Table 2). The electron multiplying regis-ter simply amplifies this additional charge, so unlike readout noise it cannot beovercome by increasing the electron multiplying gain.

The clock-induced-charge specification for the Andor camera (at -85◦ C, with a100 ns serial shift time a 500 ns vertical shift time, and an EM gain of 1000×) is0.005 events per pixel for a 30 ms exposure time. Hence, for a summed readoutof 1000 frames, but with a shorter exposure time as in Figure 3, and assuming aconversion factor of 12.27 electrons per data number, one would expect at mostroughly two data counts at the bottom left and up to ∼ 9 events in the worst-case summing region towards the upper left of the ROI2. Our summed data, col-lected with an exposure time of a few milliseconds, showed an enhanced countof roughly 0.5 data numbers in the brightest region of the stacked dark frame, i.e.not inconsistent with our expectation.

2For an exposure time shorter than 30 ms, one would expect a decreased contribution fromthermally-generated spurious events.

14

We have attempted to assess the impact of this quasi-deterministic non-uniformbackground by examining the histograms of the pixel values (in digitised counts)and RMS pixel deviation from the mean (“σ”, in electrons) for each of the imagestacks shown in Table 2. These results are displayed in Figure 4 where the RMSvalues are refered to the output of the gain register.

70 90 110 130 150 170 1900

0.02

0.04

0.06

0.08

0.1

Dark Histograms, Conventional Clock 300ns

T=-80degC, EMCCD Gain 250, Preamp Gain 5.2x

V=“Normal”, σ=58.3V=”1”, σ=58.6V=”2”, σ=60.3V=”3”, σ=63.0V=”4”, σ=68.6

Counts/ADU

Pro

ba

bili

ty

70 90 110 130 150 170 1900

0.02

0.04

0.06

0.08

0.1

Dark Histograms, Conventional Clock 500ns



Counts/ADU

Pro

ba

bili

ty

70 90 110 130 150 170 1900

0.02

0.04

0.06

0.08

0.1

Dark Histograms, Fast Clock 300ns



Counts/ADU

Pro

ba

bili

ty

70 90 110 130 150 170 1900

0.02

0.04

0.06

0.08

0.1

Dark Histograms, Fast Clock 500ns



Counts/ADU

Pro

ba

bili

ty

Figure 4: Pixel histograms of the image stacks shown in Table 2 and correspond-ing RMS pixel deviation from the mean (“σ”), in electrons, referred to the outputof the gain register. Note how for the custom “fast” clocking scheme (lower row)the use of a high clocking voltage leads to an undesirable wing towards higherpixel values.

If we eliminate those regions of parameter space that we know are uninteresting,i.e. where 300 ns parallel clocking is combined with a clock voltage of “0” or “1”(Subsection 6.2), then we can see that the lowest noise option available with con-ventional ROI clocking is where the parallel clock time is 500 ns and a “Normal”voltage is used. In this case, this gives a dark frame RMS pixel deviation σ = 59.0electrons. For the custom clocking scheme, the same parallel clock time and volt-age give the lowest RMS pixel deviation, although in this case it has σ = 71.6electrons. For an electron multiplying gain of 250, the effective readout noises forthese two cases are thus 0.24 and 0.29 electrons respectively.

For the faintest targets expected for the MROI FTT system, we know that the typi-cal photon rate will be of order 50–100 detected photons per∼ 3ms frame. At thislevel, the centroid error will be wholly dominated by photon noise fluctuationsand we expect these marginal increases in effective readout noise to be largelyirrelevant in compromising the performance of the FFT system as a whole. As aresult, we opted to conduct the remaining tests with a 500 ns parallel clock anda voltage of “Normal”, as being representative of the settings to be used at the

15

MROI installation.

6.3.2 Effect of temperature on custom clocking

A key element of the system design of the MROI is that effects that have thepossibility to degrade the local seeing at the observatory site be minimised. As aresult, it is desirable that the power consumed by the camera should be as low aspossible. Because most of the power is consumed by the camera’s Peltier cooler,it follows that reducing the demand on this (by operating the CCD at a warmertemperature) should significantly reduce the camera power consumption. Thetrade-off is that a warmer CCD also generates greater thermal noise, which raisesthe question of how warm the CCD can be before this becomes significant for FTToperation.

To assess the impact of running the chip “warm”, tests were run where series’ of1000 dark frames were acquired for a range of temperatures and parallel clockvoltages. The parameters held constant across these tests were:

• EMCCD gain = 250 & Pre-amp gain 5.2×;

• Parallel clock period = 500 ns;

• Parallel clock voltage = 0;

• Serial clock period = 100 ns;

• Frame rate = 300 Hz;

• Sub-frame size 23×23 pixels & Sub-frame position (100, 100).

The frame rate chosen was the slowest acquisition frame rate suggested in RD1,and as such was chosen to maximise the thermal noise contribution, thereby pro-viding a “worst case” scenario. Our results are summarised in Table 3.

Dataset Temperature ◦C-80 -60 -40 -20 -10

Stack RMS imageRMS noise (e−) 71.6 66.5 86.1 152.1 249.5

Table 3: Dark-frame RMS noise in custom clocking mode, as a function of CCDtemperature. The colour mapping is the same for all images and ranges from 0 to100 electrons per pixel per frame.

Table 3 shows that there was little change in the background noise between sensortemperatures of -80◦C and -60◦C, but that it increased from -40◦C upward. Hence

16

Temperature/◦C Integration Time/ms1 5 10

-80 68.8 71.3 73.5-60 64.8 66.7 70.2-40 80.0 84.4 89.7

Table 4: RMS electron noise per pixel per frame, as a function of temperature andintegration time for the custom clocking scheme.

it was clear that the camera could be operated at -60◦C rather than -80◦C withnegligible CCD thermal noise penalty and significant reduction in power dissi-pation. It is noteworthy that there appears to be a “sweet spot” at -60◦C wherethe noise contribution was lowest.

6.3.3 Effects of integration time on custom clocking

Although the FTT system is expected to normally operate with a servo bandwidthof 40Hz, and hence a relatively short integration time, a longer integration capa-bility is potentially useful for observations when the seeing is particularly good.Hence, the dark frame performance of the camera was also checked for integra-tion times of 1, 5 and 10 ms and CCD temperatures of -40◦C, -60◦C and -80◦C. Forthese tests we used the custom clocking scheme and the following “standard”settings:




• Parallel clock voltage = “0”;


The results of these tests are summarised in Table 4 and showed that an increasein integration time to 10 ms at -60◦C causes only a minor noise penalty, and therewill likely be no benefit to running the camera colder than this when observingat the MROI.

6.4 Illumination Tests

Additional tests were also carried out using the faint LED target. Firstly, thesource was strobed to test for residual charge on successive frames, and secondlythe source was reduced in brightness so as to test the centroiding accuracy as afunction of light level.

17

Frame number1 2 3 4 5 6 7 8

Table 5: Image sequence in which the CCD is illuminated by the light emit-ting diode source for one frame in every four. The un-illuminated frames areinspected for residual charge. All images here have the same colour map scale.

6.4.1 Effect of using a faint strobed source during custom clocking

During observing, the source image will move across the CCD on millisecondtimescales as the turbulent atmosphere refracts the source light. If the chargegenerated by this light is not completely removed after an exposure, then theremaining charge will contaminate the following exposure and cause an effectivelag in the computed centroid.

To determine the extent of any residual charge contamination, a 1000 frame imagesequence was acquired with the source light emitting diode on for one frame inevery four and the frames examined for the presence of residual charge in theimages when the LED was off. For these tests we only used the custom clockingscheme with a standard set of camera parameters:

• EMCCD gain = 250 & Pre-amp gain 5.2×;



• Parallel clock voltage = “0”;

• Temperature = -80◦C;


A typical sequence of frames is shown in Table 5.

Under these conditions, no evidence was found for residual charge in the un-illuminated frames.

6.4.2 Effects of clocking scheme on centroiding accuracy

In order to test the impact of the custom clocking scheme on the ability of thecamera to be used to centroid a faint target, a test was undertaken whereby theRMS “jitter” of the centroid of a fixed target was compared to that expected fromtheory (Section 4), and this was repeated for a range of light levels.

18

The absolute photon flux from the light source was firstly calibrated using thecamera in photon counting mode, with the test room blacked out and the lightpath additionally shielded by a cardboard enclosure. The flux of the source wasadjusted by placing calibrated neutral density filters in front of it. When an N =5.5 neutral density filter was placed in the beam the camera counted 30.9k pho-tons over a total integration time of 20 seconds, and 14.3k counts of backgroundover the same period with the source switched off3. With the source off and thecamera shutter closed, 14.4k counts were measured. Hence ∼16.5k photons, or∼ 830 photons per second, could be attributed to the source.

The neutral density was then adjusted to a value of 4.1 so as to yield a measuredphoton rate of approximately 20800 photons per second, close to that expectedfor a 15.4 magnitude target (19800/second). Once this calibration point was de-termined, other fluxes could be tested simply by changing the neutral densityfilter. Given the repeatability of the data, together with the uncertainties in theoptical densities of the ND filters used, we estimate that this rough calibrationwas accurate to approximately 20%.

After this calibration, 1000 frame image stacks were collected in analog detectionmode over the following region of parameter space:

• Neutral densities of 1.6 to 4.1, corresponding to celestial sources of magni-tudes 9.1 to 15.4;

• Conventional ROI and custom clocking modes at 300 Hz, the frame ratesuggested in RD1 for the faintest sources;

• Custom clocking at a frame rate of 1 kHz to determine the practical limitingperformance at that rate.

As per usual the following parameters were held constant:

• Temperature = -60◦C;




• Parallel clock voltage “normal”;


Examples of images for the different clocking parameters and neutral density lev-els are presented in Table 6. Centroids for each image stack were then calculatedfrom the pixel data using the following quad cell algorithm:

3The camera actually took 10000×2ms exposures in each case. This kept the maximum photoncount per pixel per exposure at no more than 0.2, that is, well within the photon counting domain.

19

Clock Sequence Neutral Density1.6 2.1 2.6 3.1 3.6 4.1

Conven., 300Hz

Custom, 300Hz

Custom, 1000Hz

Table 6: Examples of sub-frame images as a function of clocking scheme, framerate and neutral density (i.e. target magnitude). ND values of 1.6 and 4.1 corre-spond to a target magnitudes of roughly 9.1 and 15.4 respectively at the MROI.The colour scale is constant across all images and ranges from 85 to 1000 counts.

• A 10×10 quad cell (four quadrants of 5×5 pixels) was overlaid on the data,with the centre within a pixel’s distance of the known centre of the image.To achieve this during observing, one could do a first pass through the datacalculating a barycentre, which would determine where to place the quadcell centre for a second pass using the algorithm listed here.

• All the pixels in the image stack that were not contained within the quadcell were averaged to determine a background level.

• This background level was subtracted from every pixel in the image stack,so that the background was approximately zero.

• For each frame of data in the resulting image stack, the position of the imagein pixels was determine using a standard quad cell algorithm, i.e. with equalweights4

The measured RMS jitters of these centroid estimates were then compared withthe expected values predicted by the equations of Section 4 using values of n =100 pixels and σr=51.8/250 electrons (the manufacturer’s specified readout noisedivided by an electron multiplying gain of 250). Our results and these theoreticalpredictions are shown in Figure 5.

The principal conclusions to be drawn from our tests are as follows:

• At a 300 Hz frame rate, there appears to be no substantial difference in cen-troid estimation between the conventional ROI and custom clocking modes,

4The calibration of the quad-cell algorithm, so as to determine the scale-factor between nor-malised displacement and actual pixel values, was determined using simulated image data gen-erated for moderately high light levels, and with the same image FWHM to pixel size ratio as ourexperimental conditions.

20

8 9 10 11 12 13 14 15 160.01

0.1

1

Custom, 1000HzCustom, 300HzConventional, 300HzLimit, 1000HzLimit, 300Hz

Source brightness (stellar magnitude equivalent)

Ce

ntr

oid

err

or

(pix

els

)

Figure 5: Two-axis error of calculated centroid, as a function of clocking scheme,source magnitude at the MROI and frame rate. The theoretical limits to centroid-ing performance for frames rates of 300 Hz and 1000 Hz are also shown. Due tothe calibration uncertainties of our experimental set up these predictions are onlyaccurate to the 10% level, and hence these limits are shown as shaded bands.

at least down to photon rates comparable to those expected from a magni-tude 15.4 stellar target at the MROI.

• For both the conventional and custom clocking schemes, the measured cen-troid jitter is broadly speaking consistent with that expected for data com-promised by the photon, electron-multiplication and readout noise levelsexpected for the camera when operating at a frame rate of 300 Hz.

• Our data suggest that at a frame rate of 1000 Hz, and using the custom clock-ing scheme, the RMS centroid jitter is greater than expected, indicating thepossible presence of an excess noise contribution in this region of parameterspace.

21

7 Summary

The key conclusions from these initial tests of the trial custom clocking schemedeveloped by Andor can be summarised as follows:

• The custom clocking scheme allows our 40 Hz closed loop bandwidth re-quirement and our 50 Hz goal to be realised with some margin.

• At a frame rate of 300 Hz there is no evidence to suggest that the customclocking scheme degrades the ability to centroid a stellar image, beyondthat which is available using convention ROI readout.

• The trial custom clocking scheme does not currently allow positioning andsizing of the sub-frame to be read out to meet our requirements. Further-more, it leads to a non-uniform “background” in the ROI which may makeprecision centroiding difficult at the lowest light levels.

The first two of these conclusions are very reassuring, and suggest that we areclose to demonstrating an operating mode that meets the most critical require-ments of the MROI FTT system. Furthermore, the final conclusion was expectedgiven that the trial clocking scheme had not been designed with our desired flex-ibility built-in.

In view of these very positive conclusions, we believe that relatively minor ad-justments of the custom readout strategy will be able to realise the majority ofour needs, and recommend that Andor be commissioned to deliver a modifiedversion of their scheme, as outlined below, in the very near term.

8 Recommendations

Having undertaken an evaluation of Andor’s custom clocking scheme we believethat our key technical requirements can be met with the following adjustmentsand enhancements of the current trial code. Our first, and most pressing, requestis that the basic readout strategy be adjusted so as to limit the probability of signalbuildup from regions outside the region of interest. The other requests is to allowfor more convenient switching between different readout modes.

8.1 Change in basic readout strategy

The trial custom clocking scheme has been able to meet our low readout latencyrequirement by filling all the pixels of the ROI into the serial readout register,as though they originated from a “single row” of the CCD. Our understandingis that it is this that both allows an effective sub-frame readout rate higher than1 kHz and constrains the ROI sub-frame size to be no greater than 23×23 (= 529)pixels in size. In addition, because multiple parallel row transfers are needed to

22

populate the readout register, charges from outside the ROI are added “on topof” charges already residing in this register.

As a result, we wish to request a modification to the trial custom clocking schemesuch that a fixed-size 32 × 32 ROI is clocked out, but in four steps, each of whichwould correspond to a 32× 8 sub-region of the ROI.

The center of the ROI would normally be located at the center of the 512×512 pixelactive area, but the new clocking scheme must allow for the central location of theROI to be varied by up to ±68 pixels in the horizontal and vertical directions.

Our revised clocking scheme to allow readout of the ROI would comprise thefollowing steps:

1. The exposed CCD pixels would all initially be shifted to the storage regionof the chip;

2. Subsequently, all the rows prior to the first containing the 32× 32 pixel ROIwould be parallel clocked into the readout register;

3. The whole of the readout register would then be serially clocked out, withnone of the data being recorded;

4. Then, the first row containing data of interest from the ROI would be par-allel clocked into the readout register. The register would then be clockedalong by 32 pixels, after which the next row of the ROI would be parallelclocked into the readout register. This would be repeated until the valuesin the first lower quarter (i.e. 32× 8 pixel region) of the ROI had been trans-fered into the readout register;

5. Thereafter, pixels from the readout register would be read out until all thepixels from the bottom quarter of the ROI had been digitised. Note that thiswould correspond to fewer serial clocks than in step [3] where every pixelin the readout register is assumed to have been clocked out;

6. The next three quarters of the ROI would then be readout by repeating steps[4] and [5] of the procedure three times;

This would be slower than the current trial custom readout, but we believe it willmeet all our requirements. In particular, for parallel and serial clock periods of500 ns and 100 ns respectively, we estimate that the 32×32 ROI could still be readout and digitised in around a millisecond.

8.2 Mode switching

With the current trial implementation, in order to be able to switch between the“conventional ROI” and “custom” readout modes it is necessary to exit the pro-gram and start again, reading in the appropriate configuration file at startup. This

23

restarting demands that the camera’s Peltier cooler switch off and on and henceit can take several minutes for the CCD temperature to stabilise.

It is essential that we be able to switch between conventional full-frame and cus-tom ROI clocking on a scale of seconds, without a need to power off the Peltiercooler.

8.3 Proposal for way forward

Finally, in order to facilitate the expedient delivery of a suitable custom clockingscheme, we suggest that this report be forwarded to our contacts at Andor, andthat a teleconference be set up as a mutually convenient time, as soon as possible.

References

[1] E2V Technologies, “CCD97-00 Back Illuminated 2-Phase IMO Series ElectronMultiplying CCD Sensor”, E2V Technologies Limited, UK (May 2004).

[2] Andor Technology PLC, “Hardware Guide: iXonEM+”, Version 1.2, UK (Au-gust 2008).

24