MR Interface Analysis including Chord Signaling Options

11Kandou Bus, S.A

MR Interface Analysis including Chord Signaling Options

David R StaufferMargaret Wang Johnston

Andy StewartAmin Shokrollahi

Kandou Bus SAMay 12, 2014

22Kandou Bus, S.A

Contribution Number: OIF2014.113Working Group: Physical & Link Layer WG (Electrical Track)Title: MR Interface Analysis including Chord Signaling Options

Source: David R [email protected] Bus, S.A.

Date: May 12, 2014

Abstract: This analysis compares signal integrity and power analysis results for various Chord Signaling codes in CEI-56G Medium Reach (MR) channel applications. Codes are compared to an NRZ baseline.

Notice: This contribution has been created to assist the Optical Internetworking Forum (OIF). This document is offered to the OIF solely as a basis for discussion and is not a binding proposal on the companies listed as resources above. Each company in the source list, and the OIF, reserves the rights to at any time to add, amend, or withdraw statements contained herein.

This Working Text represents work in progress by the OIF, and must not be construed as an official OIF Technical Report. Nothing in this document is in any way binding on the OIF or any of its members. The document is offered as a basis for discussion and communication, both within and without the OIF.

For additional information contact:The Optical Internetworking Forum, 48377 Fremont Blvd.,

Suite 117, Fremont, CA 94538510-492-4040 phone [email protected]

mailto:[email protected]

mailto:[email protected]

33Kandou Bus, S.A

Disclosure

• Kandou Bus, S.A. discloses that we own intellectual property related to Chord Signaling and other material described in this contribution.

• We are committed to RAND licensing of all of our technologies.

• We are committed to adhering to the bylaws of all standards organizations to which we contribute and maintain membership.

• We are committed to be good corporate citizens.

44Kandou Bus, S.A.

CEI Medium Reach Application

• Application is defined as ‒ 500 mm reach‒ one connector

• CEI-28G-MR Insertion Loss: approx. 20 dB @14 GHz.

55Kandou Bus, S.A

Channel Requirements

• Project Start states requirement that max loss is in the range of:‒ 15 to 25 dB at 14 GHz‒ 20 to 50 dB at 28 GHz

• This allows the project to pick a wide range of possible insertion loss equations; some are worse than current CEI-28G-MR and CEI-28G-LR channels.

• This contribution:‒ Projects three possible equations for channel insertion loss;‒ Compares signaling options (NRZ, PAM-4, ENRZ) for each of

these channel options; and‒ Provides power analysis comparing NRZ and ENRZ

signaling.

66Kandou Bus, S.A

CEI Channel Equation

• Basic CEI Insertion Loss Equation:

𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 =𝑐𝑐𝑐 + 𝑐𝑐𝑐

𝑓𝑓 × 𝑓𝑓𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏

𝑓𝑓𝑏𝑏+ 𝑐𝑐𝑐

𝑓𝑓 × 𝑓𝑓𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏

𝑓𝑓𝑏𝑏𝑓𝑓𝑏𝑏𝑚𝑚𝑚𝑚 ≤ 𝑓𝑓 <

𝑓𝑓𝑏𝑏𝑐

𝑐𝑐𝑐 + 𝑐𝑐𝑐𝑓𝑓 × 𝑓𝑓𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏

𝑓𝑓𝑏𝑏𝑓𝑓𝑏𝑏𝑐≤ 𝑓𝑓 ≤ 𝑓𝑓𝑏𝑏

• CEI-28G-MR:

fbmax = 28.1, c1 = 1.083, c2 = 2.436,c3 = 0.698, c4 = -17.83, c5 = 2.694

• CEI-28G-LR: fbmax = 25.8, c1 = 1.083, c2 = 3.35,c3 = 0.96, c4 = -9.25, c5 = 2.694

77Kandou Bus, S.A

Channel Options

• Channel options generated using:‒ fbmax = 56.2‒ c1 = 1.083 (same as CEI-28G-LR/MR)‒ c2 = adjusted to produce desired loss‒ c3 = c1 / 3.4895 (to match CEI-28G-LR/MR slope)‒ c4 = calculated to avoid discontinuity at fb/2‒ c5 = 2.694 (same as CEI-28G-LR/MR)

• Channel options:‒ Option 3: Extends CEI-28G-MR channel (c2 = 2.436)‒ Option 2: Extends CEI-28G-LR channel (c2 = 3.35)‒ Option 1: Set for 50 dB loss @28 GHz (c2 = 3.663)

88Kandou Bus, S.A.

Channel Options

99Kandou Bus, S.A.

Channel Models and Simulation Conditions

• SDD21 for NRZ / PAM-4 shown in top figure.

• SDD21 for ENRZ including all subchannels in bottom figure.

• Channel Models were constructed by concatenating:‒ Package Model (5.4 mm)‒ Daughter card PCB (5 inches)

o FR4 (er=3.7, tanD=0.019)‒ Backplane connector (FCI)‒ PCB trace (8, 13, or 15 inches)

o FR4 (er=3.7, tanD=0.019)‒ Package Model (5.4 mm)

• Simulation Conditions:‒ Tx Launch: 1000 mVppd‒ 3-tap FFE, CTLE, 20-tap DFE‒ No random jitter.‒ Pass/Fail: 25 mVppd, 0.25 UI eye‒ BER 1E-15 w/o FEC or 1E-6 w/FEC.

1010Kandou Bus, S.A.

KEYE Results - NRZ

• Simulation conditions:‒ NRZ @56 GBd‒ Tx Launch: 1000 mVppd‒ FFE (3-tap)‒ CTLE (0 to 12 dB)‒ DFE (20-tap)‒ BER = 1E-6 (assumes FEC)

• Results:‒ Pass/fail criteria:

o > 25 mVppd eye heighto > 0.25 UI eye width

‒ Case 3 eye is open.‒ Case 1 & 2 eyes are closed.

Channel #1-49.8 dB @28.1 GHz




KEYE Results – PAM4

• Simulation conditions:‒ PAM-4 @28 GBd‒ Tx Launch: 1000 mVppd‒ FFE (3-tap)‒ CTLE (0 to 12 dB)‒ DFE (20-tap)‒ BER = 1E-6 (assumes FEC)



‒ Case 3 eyes are open.‒ Case 1 & 2 eyes are closed.





KEYE Results – ENRZ

• Simulation conditions:‒ ENRZ @37 GBd‒ Tx Launch: 1000 mVppd‒ FFE (3-tap)‒ CTLE (0 to 12 dB)‒ DFE (20-tap)‒ BER = 1E-6 (assumes FEC)



‒ Case 1 & 2 & 3 eyes are open.

‒ Sub-channel #2 eyes are shown at left (worst case).Sub-channel #1, #3 eyes are slightly better.





KEYE Results – ENRZ w/o FEC

• Simulation conditions:‒ ENRZ @37 GBd‒ Tx Launch: 1000 mVppd‒ FFE (3-tap)‒ CTLE (0 to 12 dB)‒ DFE (20-tap)‒ BER = 1E-15 (no FEC)


o > 25 mVppd eye height

o > 0.25 UI eye width‒ Case 3 eyes are open.‒ ENRZ will work w/o FEC

on this channel.SC#0

SC#1Channel #3, 1e-15

SC#2


KEYE Results - Detail

Channel #1: Pkg (5.4mm) + 5in PCB +FCI conn. + 15in PCB + Pkg (5.4mm)



1515Kandou Bus, S.A

KEYE Results - Observations

• Results are consistent with prior published data:‒ NRZ has open eyes for channel losses up to 30dB.‒ NRZ operation can be extended up to 36 dB using FEC.‒ PAM-4 simulations tend to show similar results to NRZ

for equivalent channels and signal processing.o Advantage of lower channel loss at lower baud rate is

offset by lower launch amplitude.• ENRZ performance tends to be better because:

‒ ENRZ takes advantage of correlation across 4 wires (not just 2 wires).

‒ Baud rate is lower than NRZ; less channel loss.‒ ENRZ eye height is twice that of PAM-4.

1616Kandou Bus, S.A

How Does Coding Save Power?

• Chord codes have the potential to save power:‒ Less clocking power: CDR can be shared across wires. This

increases number of transitions available, reducing run length constraints on the CDR, and amortizing circuit size/power across more than one bit stream.

‒ Lower equalization power: o Lower baud rate = less attenuation = less equalization

required.o Better ISI tolerance can be achieved through proper code

design.‒ Lower Driver Power: Code design can reduce termination

line power.• This contribution analyzes ENRZ power consumption for a

reference architecture relative to an NRZ implementation using an equivalent architecture.

Presenter

Presentation Notes

Kandou’s products save power in a number of ways: Because the cost of clocking is amortized across more delivered bits, the cost-per-bit of clocking goes down significantly. Because more bits are delivered in one clock cycle, the clock frequency can be reduced, and hence heavy equalization is not needed. This saves a significant amount of power in very high speed applications over challenging channels. The line power can be controlled through code design, and therefore can be reduced significantly as well. Because multiple wires are lumped into a group, more compact designs are possible since components can be reused across multiple wires. This leads to lower area, and lower power.

1717Kandou Bus, S.A

Power Analysis Methodology

• Purpose: Benchmark power of an ENRZ reference design to an equivalent NRZ reference design.

• Methodology applied:‒ Kandou Wasp chip used as reference design for Serdes circuit

and logic blocks (TSMC 28 nm, 28 GBd).‒ Spice simulations used to determine power for circuit blocks of

the reference design. Logic block power estimated based on synthesis results.

‒ Determine rules for scaling each block to other frequencies.‒ Scale baseline power of each block to TSMC 16 nm process.‒ Equivalent circuit architecture assumptions are used for all

codes at all baud rates. (This avoids biasing results with architecture choices.)

• Benchmark: NRZ is used as a benchmark for the analysis methodology. This can be compared to power of existing examples of CEI-25G-LR Serdes products.

Presenter

Presentation Notes

Kandou’s products save power in a number of ways: Because the cost of clocking is amortized across more delivered bits, the cost-per-bit of clocking goes down significantly. Because more bits are delivered in one clock cycle, the clock frequency can be reduced, and hence heavy equalization is not needed. This saves a significant amount of power in very high speed applications over challenging channels. The line power can be controlled through code design, and therefore can be reduced significantly as well. Because multiple wires are lumped into a group, more compact designs are possible since components can be reused across multiple wires. This leads to lower area, and lower power.


NRZ Power Estimate (CEI-25G-LR Baseline)

Power Total (mW) 1310.00Data Throughput (Gb/s) 112.00Energy per Bit (pJ/bit) 11.71

• Baseline configuration:‒ 112 Gb/s interface‒ NRZ signaling‒ 4 lanes @28 GBd‒ CEI-25G-LR compliant‒ TSMC 28 nm process‒ DFE: 12-tap

• Typical power: 11.71 pJ/bit

• Calculation is comparable to examples of CEI-25G-LR Serdes known to the author.

Termination, 20.00

Tx Analog, 318.80

Rx Analog, 360.80

CDR, 95.60

DFE, 174.00

Clock Dist., 144.60

Digital Logic, 168.80

PLL, 27.40

Power Breakdown (mW)


NRZ Power Estimate (CEI-56G-MR)


• Baseline configuration:‒ 112 Gb/s interface‒ NRZ - 2 lanes @56 Gb/s‒ TSMC 16 nm process‒ DFE: 20 tap‒ FEC required but not included in

power budget.


• Analysis shows 16% power reduction for next generation.‒ Power advantage of next process node

is offset by higher baud rate.‒ Power is not scaling by 30% as has

been the case for prior generations of NRZ Serdes.

‒ Industry requires larger power reductions than past generations.

Termination, 10.00

Tx Analog, 268.80

Rx Analog, 286.72

CDR, 76.48 DFE, 157.97

Clock Dist., 130.10


PLL, 33.54



ENRZ Power Estimate (CEI-56G-MR)


• Baseline configuration:‒ 112 Gb/s interface‒ ENRZ - 1 lane @37 Gb/s‒ TSMC 16 nm process‒ DFE: 20 tap‒ FEC not included – requirement

depends on baseline.


• Analysis shows 42% power reduction for next generation.‒ Baud rate scales more in line with

process transistor speeds.‒ Power reduction is exceeds 30%

scaling typical of prior generations.

Termination, 5.00

Tx Analog, 130.80

Rx Analog, 152.56

CDR, 75.80

DFE, 156.56 Clock Dist., 77.50


PLL, 26.34


2121Kandou Bus, S.A

Summary• Three channels were analyzed with various insertion losses consistent

with the ranges in the project start.‒ Only the best of these channels had open eyes for NRZ or PAM-4

signaling simulations.o FEC was required in both cases.

‒ ENRZ eyes were open for all channels.o FEC was only required for the two higher loss channels.

• NRZ and ENRZ power was analyzed:‒ NRZ power is not scaling at the same rate as prior generations.‒ ENRZ offers significant power savings over an NRZ implementation.‒ Target of 6.79 pJ/bit is projected for ENRZ.

• Analysis demonstrates advantage of ENRZ over NRZ:‒ CEI-56G-MR channel can be defined for a higher insertion loss than can

be supported for other signaling methods.‒ Substantial power savings are possible.

2222Kandou Bus, S.AKandou Bus, S.A

KANDOUreinventing the

BUS

Documents

MR Interface Analysis including Chord Signaling Options