MPC5645S Microcontroller Reference Manual - …cache.freescale.com/files/32bit/doc/ref_manual/MPC5645SRM.pdf · MPC5645S Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor

MPC5645S Microcontroller Reference Manual, Rev. 8

Freescale Semiconductor 1

MPC5645S MicrocontrollerReference Manual

Devices Supported:MPC5645S

MPC5645SRMRev. 8

March 2015


2 Freescale Semiconductor

This page is intentionally left blank.



Chapter 1Introduction

1.1 The MPC5645S microcontroller .....................................................................................................551.2 MPC5645S device summary ...........................................................................................................551.3 Device block diagram ......................................................................................................................571.4 Feature summary .............................................................................................................................581.5 Feature details .................................................................................................................................61

1.5.1 Low-power operation ........................................................................................................611.5.2 e200z4d core .....................................................................................................................641.5.3 Crossbar switch (XBAR) ..................................................................................................641.5.4 Enhanced Direct Memory Access (eDMA) ......................................................................651.5.5 Interrupt Controller (INTC) ..............................................................................................661.5.6 QuadSPI serial flash memory controller ...........................................................................661.5.7 System Integration Unit Lite (SIUL) ................................................................................671.5.8 On-chip flash memory with ECC .....................................................................................671.5.9 SRAM ...............................................................................................................................681.5.10 On-chip graphics SRAM ..................................................................................................681.5.11 Memory Protection Unit (MPU) .......................................................................................691.5.12 2D Graphics Accelerator (GFX2D) ..................................................................................691.5.13 Display Control Unit (DCU3) ...........................................................................................691.5.14 Display Control Unit Lite (DCULite) ...............................................................................711.5.15 Timing Controller (TCON) and RSDS interface ..............................................................711.5.16 RLE decoder .....................................................................................................................711.5.17 DRAM controller ..............................................................................................................721.5.18 Video Input Unit (VIU2) ...................................................................................................721.5.19 Boot Assist Module (BAM) ..............................................................................................731.5.20 Enhanced Modular Input/Output System (eMIOS) ..........................................................731.5.21 Analog-to-Digital Converter (ADC) .................................................................................731.5.22 Deserial Serial Peripheral Interface (DSPI) ......................................................................741.5.23 FlexCAN ...........................................................................................................................751.5.24 Serial communication interface module (LINFlex) ..........................................................761.5.25 Inter-Integrated Circuit (I2C) controller modules .............................................................771.5.26 System clocks and clock generation modules ...................................................................771.5.27 Periodic Interrupt Timer (PIT) ..........................................................................................781.5.28 Real Time Counter (RTC) .................................................................................................781.5.29 System Timer Module (STM) ...........................................................................................781.5.30 Software Watchdog Timer (SWT) ....................................................................................791.5.31 Stepper Motor Controller (SMC) ......................................................................................791.5.32 Stepper Stall Detect (SSD) ................................................................................................791.5.33 Sound Generator Module (SGM) .....................................................................................801.5.34 IEEE 1149.1 JTAG controller (JTAGC) ...........................................................................801.5.35 Nexus Development Interface (NDI) ................................................................................80

1.6 How to use the MPC5645S documents ...........................................................................................811.6.1 The MPC5645S document set ..........................................................................................811.6.2 Reference manual content .................................................................................................82



1.7 Using the MPC5645S ......................................................................................................................831.7.1 Hardware design ...............................................................................................................831.7.2 Input/output pins ...............................................................................................................841.7.3 Software design .................................................................................................................851.7.4 Other features ....................................................................................................................85

Chapter 2Memory Map

Chapter 3Signal Description

3.1 Introduction .....................................................................................................................................913.2 Package pinouts ...............................................................................................................................913.3 Signal descriptions ..........................................................................................................................95

3.3.1 Pad configuration during reset phases ..............................................................................953.3.2 Voltage supply pins ...........................................................................................................953.3.3 System pins .......................................................................................................................973.3.4 Nexus pins .........................................................................................................................983.3.5 DRAM interface ...............................................................................................................993.3.6 VIU muxing ....................................................................................................................1023.3.7 SGM muxing ...................................................................................................................1033.3.8 RSDS special function muxing .......................................................................................1033.3.9 Functional ports ..............................................................................................................105

Chapter 4Safety

4.1 Register Protection ........................................................................................................................1314.1.1 Introduction .....................................................................................................................131

4.1.1.1 Overview .......................................................................................................1314.1.1.2 Features .........................................................................................................1314.1.1.3 Modes of Operation ......................................................................................132

4.1.2 External Signal Description ............................................................................................1324.1.3 Memory Map and Register Description ..........................................................................132

4.1.3.1 Memory Map ................................................................................................1334.1.3.2 Register description ......................................................................................134

4.1.4 Functional Description ....................................................................................................1364.1.4.1 General ..........................................................................................................1364.1.4.2 Change Lock Settings ...................................................................................1374.1.4.3 Access Errors ................................................................................................139

4.1.5 Reset ................................................................................................................................1404.2 Software Watchdog Timer (SWT) .................................................................................................140

4.2.1 Overview .........................................................................................................................1404.2.2 Features ...........................................................................................................................1404.2.3 Modes of operation .........................................................................................................1414.2.4 External signal description ..............................................................................................142



4.2.5 Memory map and register description ............................................................................1424.2.5.1 Memory map .................................................................................................142

4.2.6 Register summary ...........................................................................................................1434.2.6.1 SWT Control Register (SWT_CR) ...............................................................1434.2.6.2 SWT Interrupt Register (SWT_IR) ...............................................................1444.2.6.3 SWT Time-Out Register (SWT_TO) ............................................................145

4.2.7 Functional Description ....................................................................................................147

Chapter 5Analog-to-Digital Converter (ADC)

5.1 Overview .......................................................................................................................................1495.1.1 Device-specific features ..................................................................................................1495.1.2 Device-specific implementation .....................................................................................150

5.2 Introduction ...................................................................................................................................1505.3 Register descriptions .....................................................................................................................151

5.3.1 Introduction .....................................................................................................................1515.3.2 Control logic registers .....................................................................................................153

5.3.2.1 Main Configuration Register (MCR) ............................................................1535.3.2.2 Main Status Register (MSR) .........................................................................155

5.3.3 Interrupt registers ............................................................................................................1575.3.3.1 Interrupt Status Register (ISR) ......................................................................1575.3.3.2 Channel Pending Registers (CEOCFR[1..2]) ...............................................1585.3.3.3 Interrupt Mask Register (IMR) .....................................................................1595.3.3.4 Channel Interrupt Mask Register (CIMR[1..2]) ...........................................1605.3.3.5 Watchdog Threshold Interrupt Status Register (WTISR) .............................1615.3.3.6 Watchdog Threshold Interrupt Mask Register (WTIMR) ............................162

5.3.4 DMA registers .................................................................................................................1635.3.4.1 DMA Enable Register (DMAE) ...................................................................1635.3.4.2 DMA Channel Select Register (DMAR[1..2]) .............................................163

5.3.5 Threshold registers ..........................................................................................................1645.3.5.1 Introduction ...................................................................................................1645.3.5.2 Threshold Control Register (TRCx, x = [0..3]) ............................................1655.3.5.3 Threshold Register (THRHLR[0:3]) ............................................................165

5.3.6 Conversion timing registers CTR[1..2] ...........................................................................1665.3.7 Mask registers .................................................................................................................168

5.3.7.1 Introduction ...................................................................................................1685.3.7.2 Normal Conversion Mask Registers (NCMR[1..2]) .....................................1685.3.7.3 Injected Conversion Mask Registers (JCMR[1..2]) ......................................169

5.3.8 Delay registers ................................................................................................................1705.3.8.1 Decode Signals Delay Register (DSDR) ......................................................1705.3.8.2 Power-down Exit Delay Register (PDEDR) .................................................170

5.3.9 Data registers ..................................................................................................................1715.3.9.1 Introduction ...................................................................................................1715.3.9.2 Channel Data Register (CDRn) ....................................................................172

5.4 Functional description ...................................................................................................................173



5.4.1 Analog channel conversion .............................................................................................1735.4.1.1 Normal conversion ........................................................................................1735.4.1.2 Start of normal conversion ............................................................................1735.4.1.3 Normal conversion operating modes ............................................................1745.4.1.4 Injected channel conversion ..........................................................................1755.4.1.5 Abort conversion ...........................................................................................176

5.4.2 Analog clock generator and conversion timings .............................................................1775.4.3 ADC sampling and conversion timing ............................................................................1775.4.4 Programmable analog watchdog .....................................................................................179

5.4.4.1 Introduction ...................................................................................................1795.4.5 DMA functionality ..........................................................................................................1805.4.6 Interrupts .........................................................................................................................1805.4.7 External decode signals delay .........................................................................................1815.4.8 Power-down mode ..........................................................................................................1815.4.9 Auto-clock-off mode .......................................................................................................181

Chapter 6Boot Assist Module (BAM)

6.1 Overview .......................................................................................................................................1836.2 Features .........................................................................................................................................1836.3 Boot modes ....................................................................................................................................1836.4 Memory map .................................................................................................................................1836.5 Functional description ...................................................................................................................184

6.5.1 Entering boot modes .......................................................................................................1846.5.2 Reset Configuration Half Word Source (RCHW) ..........................................................1856.5.3 Single Chip boot mode ...................................................................................................187

6.5.3.1 Boot and alternate boot .................................................................................1876.5.4 Boot through BAM .........................................................................................................187

6.5.4.1 Executing BAM ............................................................................................1876.5.4.2 BAM software flow ......................................................................................1876.5.4.3 BAM resources .............................................................................................1896.5.4.4 Download and execute the new code ............................................................1896.5.4.5 Download 64-bit password and password check ..........................................1906.5.4.6 Download start address, VLE bit and code size ...........................................1916.5.4.7 Download data ..............................................................................................1926.5.4.8 Execute code .................................................................................................192

6.5.5 Boot from UART ............................................................................................................1926.5.5.1 Configuration ................................................................................................1926.5.5.2 Protocol .........................................................................................................193

6.5.6 Bootstrap with CAN .......................................................................................................1936.5.6.1 Configuration ................................................................................................1936.5.6.2 Protocol .........................................................................................................194

6.5.7 Flash memory password swapping .................................................................................1956.5.8 Interrupts .........................................................................................................................195



Chapter 7CAN Sampler

7.1 Introduction ...................................................................................................................................1977.2 Main features .................................................................................................................................1977.3 Register description .......................................................................................................................198

7.3.1 CAN Sampler Control Register (CR) .............................................................................1987.3.2 CAN Sampler Sample Registers 011 ............................................................................199

7.4 Functional description ...................................................................................................................2007.4.1 Enabling/disabling the CAN Sampler .............................................................................2017.4.2 Selecting the Rx port .......................................................................................................2017.4.3 Baud rate generation .......................................................................................................201

Chapter 8Clock Description

8.1 Clock architecture .........................................................................................................................2038.2 Auxiliary clocks ............................................................................................................................2058.3 Clock Generation Module (MC_CGM) ........................................................................................206

8.3.1 Introduction .....................................................................................................................2068.3.1.1 Overview .......................................................................................................2068.3.1.2 Features .........................................................................................................207

8.3.2 External signal description ..............................................................................................2088.3.3 Memory map and register definition ..............................................................................208

8.3.3.1 Register Descriptions ....................................................................................2148.3.4 Functional description .....................................................................................................226

8.3.4.1 System clock generation ...............................................................................2268.3.4.2 Dividers Functional Description ...................................................................2338.3.4.3 DRAM Controller Clock ..............................................................................2348.3.4.4 Output Clock Multiplexing ...........................................................................2348.3.4.5 Output Clock Division Selection ..................................................................234

8.4 Oscillators ......................................................................................................................................2358.4.1 Pierce oscillator (FXOSC) ..............................................................................................235

8.4.1.1 Introduction ...................................................................................................2358.4.1.2 Features .........................................................................................................2358.4.1.3 Modes of operation .......................................................................................2358.4.1.4 Block diagram ...............................................................................................2358.4.1.5 External signal description ............................................................................2368.4.1.6 Memory map and register definition ............................................................2378.4.1.7 Functional description ...................................................................................237

8.4.2 External crystal oscillator (SXOSC) ...............................................................................2388.4.2.1 Features .........................................................................................................2388.4.2.2 Functional description ...................................................................................2388.4.2.3 Register description ......................................................................................239

8.4.3 SIRC digital interface .....................................................................................................2408.4.3.1 Introduction ...................................................................................................2408.4.3.2 Slow Internal RC Oscillator (128 kHz) ........................................................240



8.4.3.3 Register description ......................................................................................2418.4.4 FIRC digital interface .....................................................................................................242

8.4.4.1 Introduction ...................................................................................................2428.4.4.2 Functional Description (16 MHz) .................................................................2428.4.4.3 Register Description .....................................................................................242

8.5 Frequency-modulated phase-locked loop (FMPLL) .....................................................................2448.5.1 Introduction .....................................................................................................................2448.5.2 Overview .........................................................................................................................2448.5.3 Features ...........................................................................................................................2448.5.4 Memory map ...................................................................................................................2458.5.5 Register description ........................................................................................................245

8.5.5.1 Control register (CR) ....................................................................................2458.5.5.2 Modulation register (MR) .............................................................................248

8.5.6 Functional description .....................................................................................................2498.5.6.1 Normal mode ................................................................................................2498.5.6.2 Progressive clock switching ..........................................................................2508.5.6.3 Normal Mode with frequency modulation ....................................................2518.5.6.4 Powerdown mode .........................................................................................2528.5.6.5 1:1 Mode (FMPLL0 only) ............................................................................252

8.5.7 Recommendations ...........................................................................................................2528.6 Clock Monitor Unit (CMU) ..........................................................................................................253

8.6.1 Introduction .....................................................................................................................2538.6.2 Main features ..................................................................................................................2538.6.3 Block diagram .................................................................................................................2548.6.4 Memory map and register description ............................................................................254

8.6.4.1 Control Status Register (CMU_CSR) ...........................................................2558.6.4.2 Frequency Display Register (CMU_FDR) ...................................................2568.6.4.3 High Frequency Reference Register FMPLL0 (CMU_HFREFR) ...............2568.6.4.4 Low Frequency Reference Register FMPLL0 (CMU_LFREFR) ................2578.6.4.5 Interrupt Status Register (CMU_ISR) ..........................................................2578.6.4.6 Measurement Duration Register (CMU_MDR) ...........................................258

8.6.5 Functional description .....................................................................................................2588.6.5.1 Crystal clock monitor ....................................................................................2598.6.5.2 PLL clock monitor ........................................................................................2598.6.5.3 Frequency meter ...........................................................................................259

Chapter 9Crossbar Switch (XBAR)

9.1 Information specific to this device ................................................................................................2619.1.1 Device-specific block diagram .......................................................................................2619.1.2 XBAR Master ID Numbers ............................................................................................2619.1.3 Unsupported features ......................................................................................................262

9.2 Introduction ...................................................................................................................................2629.2.1 Overview .........................................................................................................................2629.2.2 Features ...........................................................................................................................262



9.2.3 Limitations ......................................................................................................................2639.2.4 General Operation ...........................................................................................................263

9.3 XBAR registers .............................................................................................................................2649.3.1 Register summary ...........................................................................................................2649.3.2 XBAR Register Descriptions ..........................................................................................266

9.3.2.1 Master Priority Register ................................................................................2669.3.2.2 Slave General Purpose Control Register ......................................................2699.3.2.3 Master General Purpose Control Register ....................................................271

9.3.3 Coherency .......................................................................................................................2729.4 Function .........................................................................................................................................272

9.4.1 Arbitration .......................................................................................................................2729.4.1.1 Arbitration During Undefined Length Bursts ...............................................2739.4.1.2 Fixed Priority Operation ...............................................................................2739.4.1.3 Round-Robin Priority Operation ..................................................................274

9.4.2 Priority Assignment ........................................................................................................2749.4.2.1 Context Switching .........................................................................................2749.4.2.2 Priority Elevation ..........................................................................................275

9.4.3 Master Port Functionality ...............................................................................................2759.4.3.1 General ..........................................................................................................2759.4.3.2 Master Port Decoders ....................................................................................2779.4.3.3 Master Port Capture Unit ..............................................................................2779.4.3.4 Master Port Registers ....................................................................................2779.4.3.5 Master Port State Machine ............................................................................277

9.4.4 Slave Port Functionality ..................................................................................................2789.4.4.1 General ..........................................................................................................2789.4.4.2 Slave Port Muxes ..........................................................................................2799.4.4.3 Slave Port Registers ......................................................................................2809.4.4.4 Slave Port State Machine ..............................................................................280

9.5 Initialization/Application Information ..........................................................................................2859.6 Interface .........................................................................................................................................285

9.6.1 Overview .........................................................................................................................2869.6.2 Master Ports ....................................................................................................................286

9.6.2.1 Ignored Accesses ..........................................................................................2869.6.2.2 Terminated Accesses .....................................................................................2869.6.2.3 Taken Accesses .............................................................................................2869.6.2.4 Stalled Accesses ............................................................................................2869.6.2.5 Error Response Terminated Accesses ...........................................................287

9.6.3 Slave Ports ......................................................................................................................287

Chapter 10Deserial Serial Peripheral Interface (DSPI)

10.1 Introduction ...................................................................................................................................28910.2 Block diagram ...............................................................................................................................28910.3 Overview .......................................................................................................................................28910.4 Features .........................................................................................................................................290



10.5 Modes of operation ........................................................................................................................29110.5.1 Master mode ...................................................................................................................29110.5.2 Slave mode ......................................................................................................................29110.5.3 Module disable mode ......................................................................................................29110.5.4 External stop mode .........................................................................................................29210.5.5 Debug mode ....................................................................................................................292

10.6 Device-specific information ..........................................................................................................29210.7 External signal description ............................................................................................................292

10.7.1 Signal overview ..............................................................................................................29210.7.2 Signal names and descriptions ........................................................................................293

10.7.2.1 Peripheral Chip Select / Slave Select (CS_0) ...............................................29310.7.2.2 Peripheral Chip Selects 12 (CS1:2) ............................................................29310.7.2.3 Serial Input (SIN_x) ......................................................................................29310.7.2.4 Serial Output (SOUT_x) ...............................................................................29310.7.2.5 Serial Clock (SCK_x) ...................................................................................293

10.8 Memory map and register description ...........................................................................................29310.8.1 Memory map ...................................................................................................................29310.8.2 Register description ........................................................................................................294

10.8.2.1 DSPI Module Configuration Register (DSPIx_MCR) .................................29410.8.2.2 DSPI Transfer Count Register (DSPIx_TCR) ..............................................29710.8.2.3 DSPI Clock and Transfer Attributes Registers 07 (DSPIx_CTARn) .........29810.8.2.4 DSPI Status Register (DSPIx_SR) ................................................................30410.8.2.5 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) ....30610.8.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................30810.8.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) .............................................31010.8.2.8 DSPI Transmit FIFO Registers 04 (DSPIx_TXFRn) .................................31110.8.2.9 DSPI Receive FIFO Registers 04 (DSPIx_RXFRn) ...................................311

10.9 Functional description ...................................................................................................................31210.9.1 Modes of operation .........................................................................................................313

10.9.1.1 Master Mode .................................................................................................31310.9.1.2 Slave Mode ...................................................................................................31410.9.1.3 Module Disable Mode ..................................................................................31410.9.1.4 External Stop Mode ......................................................................................31410.9.1.5 Debug Mode .................................................................................................314

10.9.2 Start and Stop of DSPI Transfers ....................................................................................31410.9.3 Serial Peripheral Interface (SPI) Configuration ..............................................................315

10.9.3.1 SPI Master Mode ..........................................................................................31610.9.3.2 SPI Slave Mode ............................................................................................31610.9.3.3 FIFO Disable Operation ................................................................................31610.9.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism .....................31610.9.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism .......................317

10.9.4 DSPI Baud Rate and Clock Delay Generation ...............................................................31810.9.4.1 Baud Rate Generator .....................................................................................31910.9.4.2 CS to SCK Delay (tCSC) ..............................................................................319



10.9.4.3 After SCK Delay (tASC) ..............................................................................31910.9.4.4 Delay after Transfer (tDT) ............................................................................320

10.9.5 Transfer Formats .............................................................................................................32110.9.5.1 Classic SPI Transfer Format (CPHA = 0) .....................................................32210.9.5.2 Classic SPI Transfer Format (CPHA = 1) .....................................................32310.9.5.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0) ..............................32410.9.5.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) ..............................32510.9.5.5 Continuous Selection Format ........................................................................32610.9.5.6 Clock Polarity Switching between DSPI Transfers ......................................327

10.9.6 Continuous Serial Communications Clock .....................................................................32810.9.7 Interrupts/DMA Requests ...............................................................................................329

10.9.7.1 End of Queue Interrupt Request (EOQF) .....................................................33010.9.7.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF) ................................33010.9.7.3 Transfer Complete Interrupt Request (TCF) .................................................33010.9.7.4 Transmit FIFO Underflow Interrupt Request (TFUF) ..................................33110.9.7.5 Receive FIFO Drain Interrupt or DMA Request (RFDF) .............................33110.9.7.6 Receive FIFO Overflow Interrupt Request (RFOF) .....................................33110.9.7.7 FIFO Overrun Request (TFUF) or (RFOF) ..................................................331

10.9.8 Power Saving Features ....................................................................................................33110.9.8.1 External Stop Mode ......................................................................................33110.9.8.2 Module Disable Mode ..................................................................................33210.9.8.3 Slave Interface Signal Gating .......................................................................332

10.10 Initialization and Application Information ....................................................................................33210.10.1How to Change Queues ..................................................................................................33210.10.2Baud Rate Settings ..........................................................................................................33310.10.3Delay Settings .................................................................................................................33410.10.4Calculation of FIFO Pointer Addresses ..........................................................................334

10.10.4.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO ...33510.10.4.2 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO ..335

Chapter 11Display Control Unit (DCU3)

11.1 Introduction ...................................................................................................................................33711.1.1 Overview .........................................................................................................................33811.1.2 Features ...........................................................................................................................33911.1.3 Modes of operation .........................................................................................................340

11.2 External signal description ............................................................................................................34111.2.1 Overview .........................................................................................................................34111.2.2 Detailed signal descriptions ............................................................................................341

11.3 Memory map and register definition .............................................................................................34211.3.1 Memory map ...................................................................................................................34211.3.2 Register map ...................................................................................................................34211.3.3 Register summary ...........................................................................................................348



11.3.4 Register descriptions .......................................................................................................35911.3.4.1 Control Descriptor L0_1 Register (CtrlDescL0_1) ......................................35911.3.4.2 Control Descriptor L0_2 Register .................................................................36011.3.4.3 Control Descriptor L0_3 Register .................................................................36111.3.4.4 Control Descriptor L0_4 Register .................................................................36211.3.4.5 Control Descriptor L0_5 Register .................................................................36411.3.4.6 Control Descriptor L0_6 Register .................................................................36511.3.4.7 Control Descriptor L0_7 Register .................................................................36711.3.4.8 Control Descriptor Cursor 1 Register (CtrlDescCursor_1) ..........................36711.3.4.9 Control Descriptor Cursor 2 Register (CtrlDescCursor_2) ..........................36811.3.4.10 Control Descriptor Cursor 3 Register (CtrlDescCursor_3) ..........................36911.3.4.11 Control Descriptor Cursor 4 Register (CtrlDescCursor_4) ..........................36911.3.4.12 DCU3 Mode Register (DCU_MODE) .........................................................37011.3.4.13 BGND Register .............................................................................................37211.3.4.14 DISP_SIZE Register .....................................................................................37311.3.4.15 HSYN_PARA Register .................................................................................37311.3.4.16 VSYN_PARA Register .................................................................................37411.3.4.17 SYN_POL Register .......................................................................................37511.3.4.18 Threshold Register ........................................................................................37611.3.4.19 Interrupt Status Register (INT_STATUS) .....................................................37711.3.4.20 Interrupt Mask Register (INT_MASK) ........................................................37811.3.4.21 COLBAR Registers ......................................................................................38011.3.4.22 Divide Ratio Register (DIV_RATIO) ...........................................................38411.3.4.23 SIGN_CALC_1 Register ..............................................................................38511.3.4.24 SIGN_CALC_2 Register ..............................................................................38611.3.4.25 CRC_VAL Register ......................................................................................38611.3.4.26 PDI Status Register .......................................................................................38711.3.4.27 PDI Status Mask Register .............................................................................38811.3.4.28 PARR_ERR_STATUS Register ....................................................................38911.3.4.29 Mask PARR_ERR status register ..................................................................39211.3.4.30 THRESHOLD_INP_BUF_1 Register ..........................................................39411.3.4.31 THRESHOLD_INP_BUF_2 Register ..........................................................39511.3.4.32 LUMA Component Register .........................................................................39511.3.4.33 Red Chroma Components .............................................................................39611.3.4.34 Green Chroma Component Register .............................................................39611.3.4.35 BLUE chroma Component Register .............................................................39711.3.4.36 CRC_POS Register .......................................................................................39811.3.4.37 FG0_FCOLOR Register ...............................................................................39811.3.4.38 FG0_bcolor ...................................................................................................39911.3.4.39 LYR_INTPOL_EN .......................................................................................40111.3.4.40 LYR_LUMA_COMPONENT ......................................................................40111.3.4.41 LYR_CHROMA_RED .................................................................................40211.3.4.42 LYR_CHROMA_GREEN ............................................................................40211.3.4.43 LYR_CHROMA_BLUE ...............................................................................40311.3.4.44 COMP_IMSIZE ............................................................................................404



11.3.4.45 Global Protection Register ............................................................................40411.3.4.46 Soft Lock Bit Register L0 .............................................................................40511.3.4.47 Soft Lock Bit Register L1 .............................................................................40711.3.4.48 Soft Lock DISP_SIZE Register ....................................................................40811.3.4.49 Soft Lock HSYNC/VSYNC PARA Register ................................................40911.3.4.50 Soft Lock POL Register ................................................................................41011.3.4.51 Soft Lock L0_TRANSP Register .................................................................41011.3.4.52 Soft Lock L1_TRANSP Register .................................................................412

11.4 Functional description ...................................................................................................................41211.4.1 Graphic sources ...............................................................................................................41311.4.2 TFT LCD panel configuration ........................................................................................41311.4.3 DCU3 mode selection and background color .................................................................41511.4.4 Layer configuration and blending ...................................................................................416

11.4.4.1 Blending priority of layers ............................................................................41711.4.4.2 Control Descriptors .......................................................................................41911.4.4.3 Layer size and positioning ............................................................................41911.4.4.4 Graphics and data format ..............................................................................42011.4.4.5 Alpha and chroma-key blending ...................................................................42411.4.4.6 Transparency mode and blending .................................................................43011.4.4.7 Luminance mode ...........................................................................................43311.4.4.8 Tile mode ......................................................................................................434

11.4.5 Hardware cursor ..............................................................................................................43511.4.6 CLUT/tile RAM ..............................................................................................................43611.4.7 Gamma correction ...........................................................................................................43711.4.8 Temporal dithering ..........................................................................................................43811.4.9 Special DDR mode .........................................................................................................43911.4.10Run Length Encoding (RLE) mode ................................................................................439

11.4.10.1 RLE decoding scheme ..................................................................................44011.5 Timing, Error and Interrupt Management .....................................................................................440

11.5.1 Synchronizing to panel frame rate ..................................................................................44111.5.2 Managing the DCU3 FIFOs and DMA activity ..............................................................44111.5.3 Error detection ................................................................................................................44311.5.4 Interrupt generation .........................................................................................................443

11.6 Register protection ........................................................................................................................44411.6.1 Operation of scheme .......................................................................................................44411.6.2 List of protected registers ...............................................................................................445

11.7 Safety Mode ..................................................................................................................................44511.7.1 CRC area description ......................................................................................................447

11.7.1.1 Configuring the CRC calculation .................................................................44711.7.2 Summary of operation ....................................................................................................448

11.8 Parallel Data Interface (camera interface) .....................................................................................44911.8.1 PDI interface description ................................................................................................449

11.8.1.1 Introduction ...................................................................................................44911.8.1.2 PDI interaction with other modules ..............................................................44911.8.1.3 Features .........................................................................................................451



11.8.1.4 ITU-R BT.656 sync information extraction ..................................................45111.8.1.5 Normal and Narrow Mode ............................................................................45311.8.1.6 Modes of operation based on sync extraction ...............................................45511.8.1.7 Mode of operation depending on PDI[17:0] .................................................45911.8.1.8 PDI-related Interrupts ...................................................................................460

11.9 Switch between DCU mode and PDI mode (top-level description) .............................................46111.9.1 Changes in the configuration ..........................................................................................462

11.9.1.1 PDI slave mode .............................................................................................46211.9.1.2 PDI sync detection/validation .......................................................................46211.9.1.3 Other assumptions .........................................................................................463

11.10 DCU3 initialization .......................................................................................................................46311.11 Glossary .........................................................................................................................................464

Chapter 12Display Control Unit Lite (DCULite)


12.2 External signal description ............................................................................................................46812.2.1 Detailed signal descriptions ............................................................................................469

12.3 Memory map and register definition .............................................................................................47012.3.1 Memory map ...................................................................................................................47012.3.2 Register map ...................................................................................................................47012.3.3 Register summary ...........................................................................................................47312.3.4 Register descriptions .......................................................................................................483

12.3.4.1 Control Descriptor L0_1 Register (CtrlDescL0_1) ......................................48312.3.4.2 Control Descriptor L0_2 Register .................................................................48412.3.4.3 Control Descriptor L0_3 Register .................................................................48512.3.4.4 Control Descriptor L0_4 Register .................................................................48612.3.4.5 Control Descriptor L0_5 Register .................................................................48812.3.4.6 Control Descriptor L0_6 Register .................................................................48812.3.4.7 Control Descriptor L0_7 Register .................................................................48912.3.4.8 Control Descriptor Cursor 1 Register (CtrlDescCursor_1) ..........................49012.3.4.9 Control Descriptor Cursor 2 Register (CtrlDescCursor_2) ..........................49012.3.4.10 Control Descriptor Cursor 3 Register (CtrlDescCursor_3) ..........................49112.3.4.11 Control Descriptor Cursor_4 Register (CtrlDescCursor_4) .........................49212.3.4.12 DCULite Mode Register (DCU_MODE) .....................................................49212.3.4.13 BGND Register .............................................................................................49412.3.4.14 DISP_SIZE Register .....................................................................................49512.3.4.15 HSYN_PARA Register .................................................................................49612.3.4.16 VSYN_PARA Register .................................................................................49612.3.4.17 SYN_POL Register .......................................................................................49712.3.4.18 Threshold Register (THRESHOLD) ............................................................49812.3.4.19 Interrupt Status Register (INT_STATUS) .....................................................499



12.3.4.20 Interrupt Mask Register (INT_MASK) ........................................................50012.3.4.21 COLBAR registers ........................................................................................50112.3.4.22 Clock Divider Ratio (DIV_RATIO) register ................................................50512.3.4.23 SIGN_CALC_1 register ...............................................................................50612.3.4.24 SIGN_CALC_2 register ...............................................................................50712.3.4.25 CRC_VAL register ........................................................................................50712.3.4.26 PDI Status Register (PDI_STATUS) .............................................................50812.3.4.27 PDI Status Mask Register (MASK_PDI_STATUS) .....................................50912.3.4.28 PARR_ERR Status Register (PARR_ERR_STATUS) ..................................51012.3.4.29 MASK_PARR_ERR_STATUS register ........................................................51212.3.4.30 THRESHOLD_INPUT BUF_1 Register ......................................................51312.3.4.31 Luma Component Register (LUMA) ............................................................51412.3.4.32 Red Chroma Components (RED) .................................................................51412.3.4.33 Green Chroma Component Register (GREEN) ............................................51512.3.4.34 Blue Chroma Component Register (BLUE) .................................................51512.3.4.35 CRC_POS Register .......................................................................................51612.3.4.36 FG0_fcolor Register .....................................................................................51712.3.4.37 FG0_bcolor ...................................................................................................51712.3.4.38 LYR_INTPOL_EN .......................................................................................51812.3.4.39 LYR_LUMA_COMPONENT ......................................................................51812.3.4.40 LYR_CHROMA_RED .................................................................................51912.3.4.41 LYR_CHROMA_GREEN ............................................................................52012.3.4.42 LYR_CHROMA_BLUE ...............................................................................52012.3.4.43 COMP_IMSIZE ............................................................................................52112.3.4.44 Global Protection Register ............................................................................52112.3.4.45 Soft Lock Bit Register L0 .............................................................................52212.3.4.46 Soft Lock Bit Register L1 .............................................................................52312.3.4.47 Soft Lock DISP_SIZE Register ....................................................................52512.3.4.48 Soft Lock HSYNC/VSYNC PARA Register ................................................52612.3.4.49 Soft Lock POL Register ................................................................................52712.3.4.50 Soft Lock L0_TRANSP Register .................................................................52712.3.4.51 Soft Lock L1_TRANSP Register .................................................................528

12.4 Functional description ...................................................................................................................52912.4.1 Graphic sources ...............................................................................................................53012.4.2 TFT LCD panel configuration ........................................................................................53012.4.3 DCULite mode selection and background color .............................................................53212.4.4 Layer configuration and blending ...................................................................................533

12.4.4.1 Blending priority of layers ............................................................................53412.4.4.2 Control Descriptors .......................................................................................53612.4.4.3 Layer size and positioning ............................................................................53612.4.4.4 Graphics and data format ..............................................................................53712.4.4.5 Alpha and Chroma-key blending ..................................................................54012.4.4.6 Transparency mode and blending .................................................................54712.4.4.7 Luminance mode ...........................................................................................55012.4.4.8 Tile mode ......................................................................................................551



12.4.5 Hardware cursor ..............................................................................................................55212.4.6 CLUT RAM ....................................................................................................................55312.4.7 Gamma correction ...........................................................................................................55412.4.8 Temporal dithering ..........................................................................................................55512.4.9 Special DDR mode .........................................................................................................55612.4.10Run Length Encoding (RLE) mode ................................................................................556

12.4.10.1 RLE decoding scheme ..................................................................................55712.5 Timing, error and interrupt management ......................................................................................557

12.5.1 Synchronizing to panel frame rate ..................................................................................55812.5.2 Managing the DCULite FIFOs and DMA activity .........................................................55812.5.3 Error detection ................................................................................................................56012.5.4 Interrupt generation .........................................................................................................560

12.6 Register protection ........................................................................................................................56112.6.1 Operation of scheme .......................................................................................................56112.6.2 List of protected registers ...............................................................................................562

12.7 Safety mode ...................................................................................................................................56212.7.1 CRC area description ......................................................................................................564

12.7.1.1 Configuring the CRC calculation .................................................................56412.7.2 Summary of operation ....................................................................................................565

12.8 Parallel Data Interface (camera interface) .....................................................................................56612.8.1 PDI interface description ................................................................................................566

12.8.1.1 Introduction ...................................................................................................56612.8.1.2 PDI interaction with other modules ..............................................................56612.8.1.3 Features .........................................................................................................56812.8.1.4 ITU-R BT.656 sync information extraction ..................................................56812.8.1.5 Normal and Narrow Mode ............................................................................57012.8.1.6 Modes of Operation Based on Sync Extraction ............................................57212.8.1.7 Mode of operation depending on PDI[17:0] .................................................57612.8.1.8 PDI-related Interrupts ...................................................................................577

12.9 Switch between DCU mode and PDI mode (top-level description) .............................................57812.9.1 Changes in the configuration ..........................................................................................579

12.9.1.1 PDI slave mode .............................................................................................57912.9.1.2 PDI sync detection/validation .......................................................................57912.9.1.3 Other assumptions .........................................................................................580

12.10 DCULite initialization ...................................................................................................................58012.11 Glossary .........................................................................................................................................580

Chapter 13DRAM Controller (DRAMC)

13.1 Introduction ...................................................................................................................................58313.1.1 Overview .........................................................................................................................584

13.2 Features .........................................................................................................................................58413.3 Memory map and register definition .............................................................................................585

13.3.1 Memory map ...................................................................................................................58513.3.2 Register descriptions .......................................................................................................586



13.3.2.1 DRAMC System Configuration Register (DRAMC_SCR) .........................58613.3.2.2 Timing Configuration ...................................................................................59013.3.2.3 DRAMC Command Register (DRAMC_CMD) ..........................................59513.3.2.4 DRAMC Compact Command Register (DRAMC_CCMD) ........................59513.3.2.5 DQS Config Offset Count Register (DRAMC_DQS_OC) ..........................59713.3.2.6 DQS Config Offset Time Register (DRAMC_DQS_OT) ............................59813.3.2.7 DQS Delay Status (DRAMC_DQS_DS) ......................................................59813.3.2.8 DRAMC Extra Attributes (DRAMC_EXTRA) ...........................................599

13.4 Functional description ...................................................................................................................60013.4.1 Interfacing with the DRAM ............................................................................................600

13.4.1.1 Connecting the DRAM .................................................................................60013.4.2 Programming DRAM Device Internal Configuration Register ......................................60013.4.3 DRAM Command Engine ..............................................................................................60013.4.4 Write Buffer ....................................................................................................................60113.4.5 Timing Manager ..............................................................................................................60113.4.6 DRAM Read Block and DRAM Write Block ................................................................60113.4.7 Bus Interface ...................................................................................................................602

Chapter 14DRAMC Priority Manager

14.1 Introduction ...................................................................................................................................60314.2 Features .........................................................................................................................................60414.3 Detailed signal description ............................................................................................................60514.4 Memory map and register definition .............................................................................................606

14.4.1 Memory map ...................................................................................................................60614.4.2 Register descriptions .......................................................................................................608

14.4.2.1 prioman_config1, prioman_config2 (CFG1, CFG2) ....................................60814.4.2.2 HPCFG ..........................................................................................................60914.4.2.3 Lookup table main upper registers (MLUTU0MLUTU4) .........................61014.4.2.4 Lookup table main lower registers (MLUTL0MLUTL4) ..........................61114.4.2.5 Lookup table alternate upper registers (ALUTU0ALUTU4) .....................61214.4.2.6 Lookup table alternate lower registers (ALUTL0ALUTL4) ......................61314.4.2.7 Performance monitor config register (PMCFG) ...........................................61414.4.2.8 Event Time Timer (EVTMR) ........................................................................61514.4.2.9 Event Time Preset (EVPRST) ......................................................................61514.4.2.10 Performance monitor address registers .........................................................61614.4.2.11 Counter registers ...........................................................................................617

14.5 Functional description ...................................................................................................................62414.5.1 Description of operation overview ............................................................................62514.5.2 Description of operation block diagram ....................................................................62514.5.3 Congestion detector ........................................................................................................627

Chapter 15e200z4d Core

15.1 Overview .......................................................................................................................................629



15.2 Features .........................................................................................................................................63015.2.1 Execution Unit Features ..................................................................................................631

15.2.1.1 Instruction Unit Features ..............................................................................63115.2.1.2 Integer Unit Features ....................................................................................63215.2.1.3 Load/Store Unit Features ..............................................................................632

15.2.2 L1 Cache Features ..........................................................................................................63215.2.3 Memory Management Unit Features ..............................................................................63315.2.4 System Bus (Core Complex Interface) Features .............................................................63315.2.5 Nexus 3+ Features ..........................................................................................................633

15.3 Programming model ......................................................................................................................63415.3.1 Register set ......................................................................................................................63415.3.2 Instruction set ..................................................................................................................63615.3.3 Interrupts and exception handling ...................................................................................637

15.4 Microarchitecture summary ..........................................................................................................63915.5 Availability of detailed documentation .........................................................................................640

Chapter 16eDMA Channel Mux (DMACHMUX)


16.2 External signal description ............................................................................................................64216.2.1 Overview .........................................................................................................................642

16.3 Memory map and register definition .............................................................................................64216.3.1 Register descriptions .......................................................................................................643

16.3.1.1 Channel configuration registers ....................................................................64316.4 Functional description ...................................................................................................................646

16.4.1 DMA Channels with periodic triggering capability .......................................................64616.4.2 DMA Channels with no triggering capability .................................................................64816.4.3 "Always Enabled" DMA Sources ...................................................................................648

16.5 Initialization/application information ............................................................................................64916.5.1 Reset ................................................................................................................................64916.5.2 Enabling and configuring sources ...................................................................................649

Chapter 17Enhanced Modular IO Subsystem (eMIOS)

17.1 Introduction ...................................................................................................................................65317.2 Features .........................................................................................................................................65417.3 Modes of operation ........................................................................................................................65417.4 Device-specific information ..........................................................................................................654

17.4.1 Unsupported features ......................................................................................................65517.4.2 Device-specific configuration .........................................................................................65517.4.3 eMIOS clocking configuration .......................................................................................65517.4.4 Channel types ..................................................................................................................656



17.4.5 Unified Channel Block ...................................................................................................65817.5 External signal description ............................................................................................................659

17.5.1 Overview .........................................................................................................................65917.5.2 Detailed signal descriptions ............................................................................................659

17.5.2.1 emiosi[n] - eMIOS200 Channel Input Signal ...............................................65917.5.2.2 emioso[n] - eMIOS200 Channel Output Signal ...........................................65917.5.2.3 emios_flag_out[n] - eMIOS200 Channel Flag Signal ..................................659

17.6 Memory map and register description ...........................................................................................65917.6.1 Memory map ...................................................................................................................659

17.6.1.1 Unified Channel memory map ......................................................................66017.6.2 Register description ........................................................................................................661

17.6.2.1 eMIOS200 Module Configuration Register (MCR) .....................................66117.6.2.2 eMIOS200 Global FLAG Register (GFR) ....................................................66217.6.2.3 eMIOS200 Output Update Disable (OUDR) ................................................66317.6.2.4 eMIOS200 Disable Channel (UCDIS) .........................................................66417.6.2.5 eMIOS200 UC A Register (CADR[n]) ........................................................66617.6.2.6 eMIOS200 UC B Register (CBDR[n]) .........................................................66617.6.2.7 eMIOS200 UC Counter Register (CCNTR[n]) ............................................66717.6.2.8 eMIOS200 UC Control Register (CCR[n]) ..................................................66817.6.2.9 eMIOS200 UC Status Register (CSR[n]) .....................................................67217.6.2.10 eMIOS200 UC Alternate A Register (ALTCADR[n]) .................................673

17.7 Functional description ...................................................................................................................67417.7.1 Unified Channel (UC) .....................................................................................................676

17.7.1.1 UC Modes of Operation ................................................................................67817.7.1.2 Input Programmable Filter (IPF) ..................................................................69317.7.1.3 Clock Prescaler (CP) .....................................................................................69417.7.1.4 Effect of Freeze on the Unified Channel ......................................................694

17.7.2 Global Clock Prescaler Submodule (GCP) .....................................................................69417.7.2.1 Effect of Freeze on the GCP .........................................................................695

17.8 Initialization/application information ............................................................................................69517.8.1 Considerations ................................................................................................................69517.8.2 Application Information .................................................................................................695

17.8.2.1 Time Base Generation ...................................................................................69617.8.2.2 Coherent Accesses ........................................................................................69817.8.2.3 Channel/Modes Initialization ........................................................................698

Chapter 18Enhanced Direct Memory Access (eDMA)

18.1 Introduction ...................................................................................................................................69918.1.1 Overview .........................................................................................................................70018.1.2 Features ...........................................................................................................................700

18.2 Memory map/register definition ..............................................................

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MPC5645S Microcontroller Reference Manual - …cache.freescale.com/files/32bit/doc/ref_manual/MPC5645SRM.pdf · MPC5645S Microcontroller Reference Manual, Rev. 8 Freescale Semiconductor