MPC555.ppt

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Part II: MPC555 Internal I/O Modules, Hardwareinterconnects, Interrupt Controller, External

Interrupt ESR

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External Interrupt ESRTwo major aspects:

Exception processing: Interrupt and resumeprogramming execution

Interrupt processing: Read interrupt registers, findand call ISR

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External Interrupt ESRGeneral procedures:

1. Save machine contexts

2. Re-enable interrupts

3. Save user-level registers

4. Read interrupt vector code

5. Calculate ISR address and jump to ISR

6. Restore machine contexts and user-level registers

7. Return to program execution

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External Interrupt Exception

Prologue; STEP 1: SAVE "MACHINE CONTEXT"

stwu sp, -40 (sp)

stw r3, 24 (sp)

mfsrr0 r3stw r3, 12 (sp)

mfsrr1 r3

stw r3, 16 (sp)

; STEP 2: make execution recoverable and enable

; external interrupt

mtspr EIE, r3

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Set MSR[EE] and MSR[RI] bits; others:

EIE: set MSR[EE] and MSR[RI]

EID: set MSR[RI] only

Create stack frame, saving r3, SRR0, SRR1

Must use r3 or some other GPR because

SRR0:1 cannot be saved directly

MSR[EE] and MSR[RI] are cleared, i.e.,Interrupt disabled and execution not

recoverable

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Prologue (Continue); STEP 3: SAVE OTHER APPROPRIATE CONTEXTmflr r3

stw r3, 8 (sp)

mfcr r3

stw r3, 20 (sp)

stw r4, 28 (sp)

stw r5, 32 (sp)stw r6, 36 (sp)

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Save LR and CR

LR will be changed when calling ISR

ISR will have branches that change CR

r3 is used because CR and LR cannot besaved into memory directly

Save other registers

assume that any ISR uses only r3-r6

must save more if ISR is written in C

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MPC555 Interrupt ControllerFeatures:

Support sixteen priority levels

Interrupt masking: To help enable and disable interruptsselectively

Interrupt vector code: To help generate ISR address

Interrupt prioritization: To help select the interrupt with

the highest priority

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MPC555 Interrupt Controller

Eight interrupt levels assigned to internal devicesEight IRQ pins reserved for extern devices

Hard drive, video card,

IRQ[0]: connect to reset

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USIU

U-BUS

8

8

IRQ[0:7]

external

IRQ

Reset

Timer

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1

1

3

2

4

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MPC555 Interrupt ControllerProgramming interface

SIPEND: Interrupt pending register, recording all

pending interrupt signalsSIMASK: Interrupt mask register, storing the mask bits

SIVEC: Interrupt vector code, storing the vector code forthe interrupt of the highest priority

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MPC555 Interrupt ControllerSIPEND: Eight internal interrupt sources, eight

external interrupt sources; interleaved together

UIPEND is located at UIMB

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L7 for 7-31 UIPENDL0 L1 L2 L3 L4 L5 L6

From IMB3 peripherals

I0

External IRQ[0:7]

I1 I2 I3 I4 I5 I6 I7

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7 reserved

16 31SIPEND

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MPC555 Interrupt ControllerSIMASK: 16 effective bits, one for each interrupt

source

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16 31SIPEND


16 31SIMASK

Masked Interrupt Signals 0-15

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MPC555 Interrupt ControllerSIVEC: Vector code for the most urgent interrupt

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Priority Arbiter Hardware

Masked Interrupt Signals 0-15

0 0 X X X X 0 0SIVEC

Priority: 0 Highest

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MPC555 Exceptions and Interrupts

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ExternalInterrupt ESR

Interrupt

controller

device 1 device 2 device n

CPU

External interrupt exception

External Interrupts

Other ESR Other ESR

ISR 1 ISR 2 ISR n

SIVEC

SIMASK

SIPEND

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Prologue (Continue); STEP 4: DETERMINE INTERRUPT SOURCElis r3, SIVEC@halbz r3, SIVEC@l (r3)

lis r4, IRQ_table@hori r4, r4, IRQ_table@l

add r4, r3, r4

mtlr r4

; STEP 5: BRANCH TO INTERRUPT HANDLER

blrl

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Load 8-bit SIVEC into r3

SIVEC here is a 32-bit constant

0x2FC01C

Set up jump inst address in ajump

table

use lis and ori to load IRQ table

base

add offset to get the ISR address

move jump inst address to LR

blrl: branch to address in LR and save PC+4 in LR

basically this is a function call using function pointer at target address: b kth_isr_addr

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Set Up ISR AddressesUse Jump table:IRQ_jump_table:

b irq0_handler ; interrupt pin 0

b level0_handler ; interrupt level 0


b level1_handler ; interrupt level


b level7_handler ; interrupt level 7

irq0_hanlder: ; IRQ0 ISR put here

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Set Up ISR AddressesUse address table

InterruptTable:

.long irq0_handler ; interrupt pin 0

.long level0_handler ; interrupt level 0



;



irq0_hanlder: ; IRQ0 ISR put here

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Epilogue; STEP 6: RESTORE CONTEXTlwz r4, 28 (sp)

lwz r5, 32 (sp)

lwz r6, 36 (sp)

lwz r3, 8 (sp)

mtcrf 0xff, r3

lwz r3, 20 (sp)

mtlr r3

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Restore r4, r5, r6, which were saved

in prologue

Restore CR and LR

again use r3 as a bridge

CR and LR (and any other SPR)

cannot be loaded directly with datafrom memory

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Epilogue (Continue); STEP 6: RESTORE CONTEXT

mtspr NRI, r3

lwz r3, 12 (sp)

mtsrr0 r3

lwz r3, 16 (sp)

mtsrr1 r3

lwz r3, 24 (sp)

addi sp, sp, 40

; STEP 7: RETURN TO PROGRAM

rfi ; End of Interrupt

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Restore SRR0, SRR1 and r3

again use r3 as a bridge in restoring

SRR0 and SRR1

r3 is the first to be saved and the last

one to be restored

rfi (return from interrupt):

restores MSR bits saved in SRR1

restores next-PC saved in SRR0

Clear MSR[RI] and MSR[EE]

cannot beinterrupted from now on;

NRI: SPR for fast clearing MSR[EE]

and MSR[RI]

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External Interrupt ESRGeneral Setup

Set up SIMASK

Set up ISR table Set up device interrupt level

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MPC555 On-Chip I/O

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5

1

4

2

3

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MPC555 On-Chip I/O

TPU3: Time Processor Units, 3

rd

version; versatilefunctions, e.g. counting pulses

MIOS1: Modular I/O System;

QADC64: Queued Analog-to-digital converter

TouCAN: Control Area Network, two-wire, up to1Mbps and 40m; e.g. network inside vehicle

QSMCM: Queued Serial Multi-channel Module

IMB3 bus: Inter-Module Bus

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TPU3 TPU3 MIOS1 QADC64 QADC64 TouCAN TouCAN QSMCM

IMB3 Bus 1

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UIMB: U-bus to IMB Interface

UIMB: U-bus to IMB interface

UIPEND: Interrupt pending reg.

U-bus: Unified bus, connecting multiple internal buses

UMCR[IRQUX]: Enable level 7-31

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UIPEND

IMB3 Bus

U-Bus

addr/data

Other bus

Interrupt

controller

232

8

UMCR[IRQUX]

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UIMB: U-bus to IMB InterfaceThe interface converts 32 interrupt levels on IMB3 Bus to

8 interrupt levels on U-Bus

Level 0-6 to U-Bus level 0-6

Level 7-31 to U-Bus level 7

Interrupt handler reads full UIPEND through memory-mapped I/O

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Unified System Interface UnitThe USIU controls system start-up, system initialization andoperation, system protection, and the external system bus.

MPC555 USIU functions: System configuration and protection Interrupt controller System reset monitoring and generation Clock synthesizer Power management External bus interface (EBI) control Memory controller Debug support

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Internal I/O

ProcessorCore

USIU

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Unified System Interface Unit

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USIU 4

Timebase

Clock

PIT

PLL

SW watchdog

Decrementer

SIPEND

SIMASK

SIVEC

Internal I/O

through U-bus External IRQ

NMI control

IREQ

reset

Decr timer

Note: External IRQ is controlled by SIEL triggered by falling

edge or low level

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USIU Internal Interrupt SourcesMPC 555 has a crystal of 4MHz or 20MHz Time base: timer interrupt based on the clock; cannot be

reset

Real-time clock: timer interrupt based on real-time clock(like a watch); cannot be reset PIT: Periodic interrupt timer goes off everyn cycles PLL change of lock: Phase lock loop, used to provide

higher clock frequency; generate interrupt in abnormal

situation, e.g. lost the lock of the clock Software watch dog: Used to monitor help avoid software

deadlock Decrementer: Another timer interrupt, but is processed

by a special handler (less overhead)

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Connecting To PowerPC Core

Three interrupt lines to processor core: IREQ, NMI, and Decrementer

MSR[EE]: Enable external interrupt IREQ: External interrupt NMI: Non-maskable interrupt (e.g. reset button is pushed) Decrementer: fast timer interruptOther processor components not shown

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MSR[EE]Vector table

n+0x100

n+0x500

n+0x900

&

SRR1SRR0

Inst buffer

inst

addr

to mem

IREQ

NMI

Decrementer

5

1

2

3

inst

Finally!

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Connecting To PowerPC CoreRefers to three handlers for1. Maskable Interrupt2. Non-maskable interrupt3. Decrementer (low-overhead timer)

When an interrupt happens, hardware: Waits for current inst to complete Saves PC to SRR0 Saves MSR[EE] to SRR1, Clear MSR[EE] Transfer control to n+0x100,n+0x500, or n+0x900,respectivelyThe rest is left to software handler

All I/O interrupts share the same interrupt handler

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Documents

MPC555.ppt