Motor Control Lab Using Altera Nano FPGA

Introduction:We describe a Laboratory exercise to learn control of a small DC motor using Altera FPGA

DE0-Nano Board. This board uses Cyclone IV FPGA chip and has ADC (analog to digital 8 channel 12 bit) component on the board. A softcore RISC 32 bit processor (NIOS) is implemented on the Cyclone IV using Quartus V12 development platform. Programs are written using C, VHDL and Verilog to generate PWM (pulse with modulation) signal. The PWM signal is routed to external pins and wired to external H-Bridge, H-Bridge has separate power supply and is wired to drive dc motor. The external 12 bit DAC (digital to analog converter) connected to Nano’s external I2C and output wired to one of ADC inputs for feedback measurements. The DAC output could drive dc motor by buffering through a power amplifier. The Power amplifier would be wired to drive dc motor with less noise or buzz sound coming from motor at low speeds. Data logging of digital samples from ADC periodically logged to EEPROM. The demo will ramp the PWM from 0% to 100% and loop, so motor will go from stop, continue to go faster until is at max speed reached and repeat sequence.

DesignStart with a designs provided (Fig 1) where DE0-Nano board will have the IP of NIOS in the

design. Add another I2C interface to be routed to an external pins for DAC and EEprom. Also extend the boards routing of the GPIOs to the NIOS module. The PWM described in Fig 2 as the functional part of a NIOS ISR is written in C. The Quartus IDE shown in Fig 3 is where all modules are compiled to a software object file (SOF) that will be loaded onto the Nano board. The NIOS IDE (Fig 4) is where the C / assembler code is compiled, linked and ready to be loaded into the NIOS program space. Wire up boards and run as shown in the results section. For simplicity, only the PWM portion is done in detail.

ResultsFig 5 shows the layout design and the plan for wiring. The breadboard and

fabricated prototype I/O cards are shown in Fig 6. For ease of storing and reassembly, the 26pin socket header made things much easier to separate boards for storage, redesign, and going back to testing. As testing of ADC, DAC, and PWM went well, the design advanced to the stage of Eagle layout design that was sent out for fabrication (shown as Fig 7). Choosing a simple flag on the DC motor shaft was first indicator, but found that it made it hard to determine rotational speed differences. It is better to use a dc motor with a gear box as this visual makes it easier to observe rate changes for demonstration purposes. The Nios design mapping and routing all I/O pins made it possible in C to also set and read any pin of GPIO connectors as in or out under C control.

ConclusionWith flexibility to distribute functions among circuit layout in HDL and use of some peripheral chips (ADC,DAC,EEPROM, Accelerometer, Flash) the implementation was

completed. Trade off of doing PWM in HDL or C could always be revisited, but choice of doing it as an ISR in C code allowed ease to try variations and quickly run them. Possible to do future test designs for conditions like gentle start or be aggressive for high torque start conditions. The NIOS ISR (found in BSP section) made implementation of timing and logging functions easier to support. It was easy to tweak the base frequency of the PWM. The demonstration module is friendly enough to use and suggest to be used for robot driving. The flexible Quartus HDL design IDE and deployment of the NIOS, proved to be useful environment to take a concept signal, shape it, map/route it, and then wire it through bus structures achieving control of motors and sensors.

I2c 12 bit DAC http://www.karlssonrobotics.com/cart/search.php?mode=search&page=1 H-Bridge PCB http://www.karlssonrobotics.com/cart/breakout-board-for-l298n-full-bridge-motor-driver/ Full-Bridge Motor Driver Dual - L298N http://www.karlssonrobotics.com/cart/full-bridge-motor-driver-dual-l298n/

Gerald Jochum, Rohollah Mazrae Khoshki, Subra GanesanDepartment of Electrical and Computer Engineering

Oakland UniversityASEENCS2014

Fig 1, Block diagram of the DE0-Nano Basic motor drivers Fig 2, Block diagram of the PWM as NIOS logic

Fig 3, Quartus IDE Ver 12.0 showing project circuit

Fig 4, NIOS IDE showing C code and console

Fig 6, Prototype model built

Fig 7, Demonstration model built

Fig 5, wiring design used to breadboard