Motor Control From Concept to Production with Zynq …zedboard.org/sites/default/files/Zynq Motor Design Seminar OnDemand... · Motor Control From Concept to Production with Zynq

Motor Control

From Concept to Production

with Zynq®-7000 AP SoC Avnet Design Seminar

Course Objectives

During this course you will gain insight into:

● Avnet Zynq-7000 AP SoC / Analog Devices Intelligent Drives Kit

● Simulink® modeling for simulation and C / HDL code

generation, including a new prototype workflow targeting the

Xilinx Zynq-7000 All Programmable SoC

● Integrating Simulink models into Zynq-based motor control

using Xilinx Vivado® Design Suite

2

Moving from Simulink to Zynq

3

Simulation

Prototype

Production

Agenda

4

Topic

Introducing the Zynq®-7000 AP SoC Intelligent Drives Kit

Demo 1 Zynq IDK in Operation / Base Reference Design

Analog Devices High Performance Servo Solution

Prototype with Zynq Support Package from MathWorks®

Demo 2 Code generation and execution on Zynq IDK

Deploy Simulink® FOC with Xilinx Vivado® Design Suite

Demo 3 Adding a custom controller to Base Reference Design

Motor Control



Agenda

6

Topic








Zynq-7000 Family Highlights

● Complete ARM®-based Processing System o Dual ARM Cortex™-A9 MPCore™

o L1, L2 Caches and On-Chip Memory

o Fully Integrated Memory Controllers

o I/O Peripherals (CAN, USB, Ethernet, UART, …)

● Tightly Integrated Programmable Logic o Used to extend Processing System

o Scalable density and performance 30k – 440k LCs, 80 – 2,020 DSP Blocks

● Flexible Array of I/O o Wide range of external multi standard I/O

o High performance integrated serial transceivers

o Analog-to-Digital Converter inputs

Performance/power of an ASIC with the flexibility of an FPGA

Zynq Delivers Unprecedented Integration

● One scalable platform for all products

● Reduced BOM

● Higher reliability / better MTBF

● Lower PCB and assembly cost

8

DSP DSP uP

Zynq Delivers Unprecedented Performance

● Advanced algorithms require fast, deterministic processing

● Field Oriented Control (FOC) loops suffer sequential delay in MCU

● Scalable to any number of motors with no performance loss in Zynq

9

Zynq-7000 AP SoC / Analog Devices Intelligent Drives Kit

10

Avnet ZedBoard (AES-Z7EV-7Z020-G)

Analog Devices

Motor FMC (AD-FMCMOTCON1-EBZ)

● Features ZedBoard low-cost community baseboard

● Introducing ADI High Performance Servo Solution

● Leverages MathWorks® workflow for Zynq

● Xilinx solution for Motor Control and Industrial Networking

Zynq-7000 AP SoC / Analog Devices IDK Features

• Function

• Drive BDC, BLDC, PMSM, Stepper motors up to 48V @ 18A

• ADI isolation for power and digital signals

• AD7401A isolated ΣΔ data converters

• XADC connection

• Dual Gigabit IEEE1588 Ethernet

• 8GB SD Card

• Linaro® Linux framework with Field Oriented Controller from MathWorks

• Xilinx Vivado Design Edition voucher

• MathWorks Motor Control Design Package (optional)

11

em.avnet.com/zynq7000idk

AES-ZIDK-ADI-G

$995

Base Kit

Analog Devices Dynamometer

● Push-button, digital control and measurement of a dynamic load to

test real-time Zynq motor control performance

● Analog Discovery™ USB oscilloscope for load signal capture and

control directly from MATLAB

AES-ZIDK-ADI-DYNO-G

$1695

Base Kit + Dynamometer

em.avnet.com/zynq7000idk

Dynamometer Block Diagram

13

Dynamometer Drive System30 Pin Connector

Embedded Control Board

3 Phase MOSFET Bridge GIntegrated

Controller

Current & Speed Measurement

Rigid Coupling

Zynq Intelligent Drives Platform

M

Analog Discovery

User Interface (Keys + LCD)

Instrumentation Control Toolbox

Zynq Intelligent

Drives Kit

3-phase MOSFET bridge

adjusts generator load

User Interface to

change load

profiles and view

speed/current

Measure signals and control

load using Analog Discover

Module with MATLAB

ADI Base Reference Design – concept diagram

14

Processing System Programmable Logic

Cortex™-A9

LINUX

AD-FMCMOTCON1

P

W

M

AX

I In

terc

on

ne

ct

DMA

A

X

I

HDL code C code

Motor

Controller

User Space GUI

Application

USB 2.0

Power

Inverters

ΣΔ ADC

Encoder

Interface

Iso

lati

on

Motor Control


with Zynq®-7000 AP SoC

Next Topic in the Series:


Motor Control



Agenda

17

Topic








The World Leader in High Performance Signal Processing Solutions

Analog Devices

High Performance Servo Drive

ADI High Performance Servo Drive

Controller Board

Low Voltage Drive Board

Signal Chain

Dynamometer

ADI Reference Designs

Support Model - Online Customer Support Model

Analog Devices Wiki

Analog Devices EngineerZone

Zynq-7000 All Programmable SoC / ADI Intelligent Drives Kit

Next Steps

Agenda



Complete drive system demonstrating efficient control of multiple motor types

• High quality power sources

• Reliable power, control, and feedback signals isolation

• Accurate measurement of motor current & voltage signals

• High speed interfaces for control signals to allow fast controller response

• Industrial Ethernet high speed interface

• Flexible control with FPGA/SoC interface

Example reference designs showing how to use the control solution with Xilinx

FPGAs / SoCs and Simulink

21

AD-FMCMOTCON1-EBZ


Target applications include

Industrial servos and drives

Manufacturing, assembly, and automation

Medical diagnostic

Surgical assist robotics

Video surveillance and machine vision

Power efficient drives for transportation

22

AD-FMCMOTCON1-EBZ

Hardware – Controller Board

Compatible with all Xilinx

FPGA/SoC platforms with FMC Low

Pin Count (LPC) or High Pin Count

(HPC) connectors

Fully isolated control and feedback

signals

Current and voltage measurement

using isolated ADCs

Xilinx XADC interface

2 x Gbit Ethernet PHYs for high

speed industrial communication

Hall + Differential Hall + Encoder +

Resolver interfaces

FMC signals voltage adaptation

interface for seamless operation on

all FMC voltage levels

CONTROLLER BOARD

Current & Voltage Measurement

ISO

LATI

ON

Power

ISO

LATI

ON

XADC Interface

ISO

LATI

ON

Position Sensors Interfaces

(Hall + Encoder + RDC) ISO

LATI

ON

Gb Industrial Ethernet Interface

FMC

LP

C /

HP

C

DR

IVE

BO

AR

D C

ON

NEC

TOR

Hal

l + D

iffe

ren

tial

Hal

l +

Enco

de

r +

Re

solv

er

Co

nn

ect

ors

RJ4

5

Co

nn

ect

or

Digital I/O SignalsIS

OLA

TIO

N

Vo

ltag

e

Tran

slat

ion

Vo

ltag

e

Tran

slat

ion

Vo

ltag

e

Tran

slat

ion

Vo

ltag

e

Tran

slat

ion

Analog Signals

Analog Signals

XA

DC

C

ON

NEC

TOR

Digital Signals

23

Hardware – Controller Board

24

Hardware – Low Voltage Drive Board

Drives BLDC / PMSM / Brushed

DC / Stepper motors

Drives motors up to 48V @ 18A

Dynamic braking capability

Integrated over current and

reverse voltage protection

Current measurement using

isolated ADCs

PGAs to maximize the current

measurement input range

Bus voltage, phase currents and

total current analog feedback

signals

BEMF zero cross detection for

sensorless control of PMSM or

BLDC motors

LOW VOLTAGE DRIVE BOARD

Overcurrent & Reverse Voltage Protection

Power

DR

IVE

BO

AR

D C

ON

NE

CT

OR

Digital Signals MOSFET Driver ICMOSFET Bridge

Current & Voltage Analog Signals Conditioning

Current Measurement ADCs

Digital Signals

Analog Signals

Digital Signals

External 12V – 48V

Power Supply

MO

TO

R

CO

NN

EC

TO

R

PWM Shunt Resistors

BEMF Detection for Sensorless Control

Digital Signals

25

Hardware – Low Voltage Drive Board

26

FMCMOTCON1 Signal Chain - ADC

AD7401 Isolated Sigma-Delta Modulator

Features High performance isolated ADC

16-bit NMC

ENOB 13.3 bits

SNR 83dB

±2 LSB INL with 16-bit resolution

±250 mV differential analog input

−40°C to +125°C operating temperature range

5 kV rms, isolation rating (per UL 1577)

Maximum continuous working voltages

565 V pk-pk: ac voltage bipolar waveform

891 V: dc (CSA/VDE)

891 V pk-pk: ac voltage unipolar waveform

Applications Ideal for motor control and dc-to-ac inverters

Shunt resistor current feedback sensing

Isolated voltage measurement

27

FMCMOTCON1 Signal Chain - ADC

2 Signal Wires

20 MHz clock input

1 bit digital data stream output

Digital Filter for Data Reconstruction

A SINC3 filter model and HDL implementation

are provided in the datasheet

Typical filter output characteristics

Output code: 16 bit

Sampling rate: 78kHz

The output code resolution and sampling rate can be controlled by changing the filter’s model and decimation

Polyphase interpolation filters are utilized to increase the sampling rate of the system up to 10Msps of real data

28


Overcurrent & Reverse Voltage Protection

Power

DR

IVE

BO

AR

D C

ON

NE

CT

OR

Digital Signals MOSFET Driver ICMOSFET Bridge

Current & Voltage Analog Signals Conditioning

Current Measurement ADCs

Digital Signals

Analog Signals

Digital Signals

External 12V – 48V

Power Supply

MO

TO

R

CO

NN

EC

TO

R

PWM Shunt Resistors

BEMF Detection for Sensorless Control

Digital Signals

FMCMOTCON1 Signal Chain

IA, IB Signal ChainLOW VOLTAGE DRIVE BOARDFPGA CONTROLLER BOARD

Shunt Resistor

AD8207 Difference Amplifier

Gain 20

RC LPF

Cutoff 100kHz

Ip

In

AD8251 PGA

Gain 1 / 2 / 4 / 8

ADA4084-2 Amplifier

Gain 0.1

+/-125mV+/-2.5V+/-2.5V+/-2.5V

AD7401

ΣΔ Modulator

+/- 250mVSINC3 Filter

Data

Clock

RC LPF

Cutoff 76kHz

Data[0..15]

+/- 250mV

20MHz

AD7401 ΣΔ

Modulator

RC LPF

Cutoff 76kHz


Data[0..15]

Data

Clock

20MHz

ISO

LATI

ON

ISO

LATI

ON

IA, IB XADC Signal Chain


FPGA

CONTROLLER BOARD

Shunt Resistor


Gain 20

RC LPF

Cutoff 100kHz

Ip

In

AD8251 PGA

Gain 1 / 2 / 4 / 8

ADA4084-2 Amplifier

Gain 0.1

+/-125mV+/-2.5V+/-2.5V+/-2.5V

AD7401

ΣΔModulator

+/- 250mV

XADC

Digital Bitstream

RC LPF

Cutoff 76kHz

+/- 250mV

Analog

Reconstruction Filter

Sallen Key, Cutoff 100KHz

AD8137

Differential ADC Driver

0 .. 1 V

VP

VN

Unipolar 0 .. 1 VADG759

Multiplexer

VAUX_P

VAUX_N

Analog Isolation

ISO

LATI

ON

29

IT Signal ChainLOW VOLTAGE DRIVE BOARDCONTROLLER BOARD

Shunt Resistor


Gain 48.78

RC LPF

Cutoff 100kHz

Ip

In

AD8251 PGA

Gain 1 / 2 / 4 / 8

ADA4084-2 Amplifier

Gain 0.05

+/-100mV0 .. 5V0 .. 5V0..5V

AD7401

ΣΔ Modulator

0 .. 250mVRC LPF

Cutoff 76kHz

0 .. 250mV

20MHz

FPGA

SINC3 FilterData

[0..15]

AD7401 ΣΔ

Modulator

RC LPF

Cutoff 76kHz


Data

Clock

20MHz

Data

Clock

ISO

LATI

ON

ISO

LATI

ON

IT XADC Signal Chain


FPGA

CONTROLLER BOARD

Shunt Resistor


Gain 48.78

RC LPF

Cutoff 100kHz

Ip

In

AD8251 PGA

Gain 1 / 2 / 4 / 8

ADA4084-2 Amplifier

Gain 0.05

+/-100mV0 .. 5V0 .. 5V0..5V

AD7401

ΣΔModulator

0 .. 250mV

XADC

Digital Bitstream

RC LPF

Cutoff 76kHz

0 .. 250mV

Analog



AD8137


0 .. 1 V

VP

VN


Multiplexer

VAUX_P

VAUX_N

Analog Isolation

ISO

LATI

ON

Vbus Signal Chain

LOW VOLTAGE DRIVE BOARDFPGA CONTROLLER BOARD

Resistive Divider

Gain 1/6.5

Vbus

AD8207 Operational Amplifier

Gain 1/1.85

ADA4084-2

AmplifierGain 0.05

0 .. 5VAD7401 ΣΔ

Modulator

0 .. 250mVSINC3 Filter

Data

Clock

RC LPF

Cutoff 76kHz

Data[0..15]

0 .. 250mV

20MHz ISO

LATI

ON

Vbus XADC Signal Chain

LOW VOLTAGE DRIVE BOARDCONTROLLER BOARD

Resistive Divider

Gain 1/6.5

Vbus

AD8207 Operational Amplifier

Gain 1/1.85

ADA4084-2

AmplifierGain 0.05

0 .. 5VAD7401 ΣΔ

Modulator

0 .. 250mV RC LPF

Cutoff 76kHz

0 .. 250mV

FPGA

XADC

Digital Bitstream

Analog



AD8137


0 .. 1 V

VP

VN


Multiplexer

VAUX_P

VAUX_N

Analog Isolation

ISO

LATI

ON

Hardware - Dynamometer

Two BLDC motors connected by a rigid couple in a dyno setup

Electronically adjustable load

Measurement and display of load motor phase currents

Measurement and display of load motor speed and current

External control using Analog Discovery™ USB oscilloscope (not included) for load signal capture and control directly from MATLAB

30

Dynamometer Drive System30 Pin Connector

Embedded Control Board

3 Phase MOSFET Bridge GIntegrated

Controller

Current & Speed Measurement

Rigid Coupling

Zynq Intelligent Drives Platform

M

Analog Discovery

User Interface (Keys + LCD)

Instrumentation Control Toolbox

Analog Devices

Dynamometer (AD-DYNO1-EBZ)



Reference Designs Contents ISE HDL Project Control and monitoring through Chipscope

Only manual control

Monitoring of system important parameters

Simple to synthetize / understand / utilize

Vivado HDL Project Complex HDL blocks with AXI Lite and

AXI Streaming interfaces

Infrastructure for Linux support

Automatic controllers implemented in HDL

from Simulink models

Linux IIO Drivers

Linux IIO Scope

User-space application for monitoring and control

IIO Server / Client

Real time data acquisition and system control over TCP / UDP

Simulink Controller Models

32

33

ADI Reference Design - Framework

ADI Reference Design – Linux IIO Drivers

The Linux Industrial I/O (IIO) subsystem is intended to provide support for devices that, in some sense, are sampling data converters

ADCs and DACs (like the AD7401A)

Accelerometers, gyros, IMUs

Capacitance-to-Digital converters (CDCs)

Pressure, temperature, and light sensors, etc.

RF Transceivers (like the AD9361)

Developed during 2009, committed Jan 2010, moved out of staging Nov 2011, now in all mainline Linux kernels

The IIO Divers for the motor control solution require the HDL cores to have a specified register map

A DMA interface is set up for high speed data transfer using multiple multiplexed data channels

34

http://upload.wikimedia.org/wikipedia/commons/2/2e/Tux_bg.png

IIO Scope for Real Time Data Visualization

Runs directly on Xilinx Zynq HDMI monitor, USB Keyboard/Mouse

Visualize data:

Frequency simple and complex FFT

Time Domain

Constellation (I vs Q)

Capture data:

Save sequences to file

Supports different formats

Change / read back device configuration

35

ADI Reference Design - Matlab IIO Client

ADI IIO Command Server

Runs on an embedded target under Linux

Manages real-time data exchange over TCP or UDP between the target and a remote client

Data Exchange is based on a simple communication protocol

Matlab IIO Client

Implements the communication protocol with the IIO Server

Based on the UDPReceiver / UDPSender classes from the Mathworks DSP toolbox

Controls the embedded target using specific commands

Acquires real-time data from the embedded target

36

Support Model - Online Customer Support Model

ADI Servo Drive Support Model

ADI parts

Datasheets & Documentation

Design tools and models

Evaluation kits, Symbols and Footprints

Sample & Buy

PCB Schematics, Gerbers, BOM

HDL

Applications and Drivers for Linux and No-OS

Simulink controller models

Online support via EngineerZone

Data Converters Community

Interface and Isolation Community

Power Management Community

FPGA Reference Design Community

Linux and Microcontroller Devices Drivers Community

wiki.analog.com

ez.analog.com

analog.com

http://www.wiki.analog.com/

http://www.ez.analog.com/

http://www.analog.com/

ADI Servo Drive Documentation on Wiki

39

Community Support On EngineerZone

40

Zynq-7000 AP SoC / ADI Intelligent Drives Kit

What’s included

Avnet ZedBoard 7020 baseboard

Xilinx Vivado™ Design Edition voucher

Analog Devices AD-FMCMOTCON1-EBZ Module

8 GB SD card programmed with the ADI Ubuntu Linux image including drivers and applications software

HDL and software source code, reference designs, full schematics and gerbers

Brushless DC motor: 24 V, 4000 RPM, Hall sensors and 1250 CPR indexed encoder

MathWorks Motor Control Design Package (optional)

Dynamometer dynamic load to test Zynq motor control performance with interface to MATLAB® (optional)

41

+(optional)

Next Steps

Go ot wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon1-ebz to learn more about the Analog Devices High Performance Servo Drive and download the hardware design files and reference designs

Go to ez.analog.com to get answers for any questions that you might have related to the ADI High Performance Servo Drive hardware and reference designs

Visit www.em.avnet.com/zynq7000idk to learn more about the Xilinx Zynq / ADI Intelligent Drives Kit and purchase the kit

Visit mathworks.com/zidk to learn about MathWorks support for the Xilinx Zynq / ADI Intelligent Drives Kit and for more information about the MathWorks workflow for Xilinx Zynq-7000 All-Programmable SoCs

Visit www.zedboard.com to view the entire Zynq Motor Control Seminar

42

http://wiki.analog.com/resources/eval/user-guides/ad-fmcmotcon1-ebz









http://www.ez.analog.com/

http://www.em.avnet.com/zynq7000idk

http://www.mathworks.com/zidk


http://www.zedboard.com/

Zynq Intelligent Drives Kit = Full Prototype Platform

● Flexible development platform for high performance

motor control applications on Zynq-7000 AP SoC

● Analog Devices isolated precision signal chain

● ADI Base Reference Design with Desktop Linux UI

43

● Leverages MathWorks

workflow for Zynq

ADI Base Reference Design – concept diagram

44


Cortex™-A9

LINUX

AD-FMCMOTCON1

P

W

M

AX

I In

terc

on

ne

ct

DMA

A

X

I

HDL code C code

Field

Oriented

Controller

User Space GUI

Application

USB 2.0

Power

Inverters

ΣΔ ADC

Encoder

Interface

Iso

lati

on

ADI Base Reference Design – detailed diagram

45


IIO Scope

Cortex™-A9

Desktop

LINUX

Power

Inverters

AD-FMCMOTCON1

ADC (Ia, Ib, Vbus)

P

W

M

User Application A

XI

Inte

rco

nn

ec

t

ΣΔ ADC

Encoder

Interface Encoder

(Position,Speed)

USB 2.0

Ethernet

UART

Iso

lati

on

DMA

DMA

DMA

A

X

I

A

X

I

A

X

I

A

X

I HDMI DMA

HDL code C code

Field

Oriented

Controller

Your

Custom

Controller


46

Simulation

Prototype

Production

Base Reference

Design

Zynq Intelligent

Drives Kit

Motor Control






Agenda

48

Topic








MathWorks Landing Page

www.mathworks.com/avnetmotor

49

http://www.mathworks.com/avnetmotor


50

Simulation

Prototype

Production

Base Reference

Design

Zynq Intelligent

Drives Kit

ARM

Programmable Logic

Some components of a production application

Production

System

Code

AXI Bus

IP1 AXI

Interface

Algorithm

HDL

Linux

Driver

Algorithm

C

IP2

IP3

System Motor

51

ARM

Programmable Logic

From simulation to production

Production Simulation

Simulink

Embedded Coder

HDL Coder

Algorithm

Model

Algorithm

Model

System

Code

AXI Bus

IP1 AXI

Interface

Algorithm

HDL

Linux

Driver

Algorithm

C

IP2

IP3

Motor

Model System Motor

52

From simulation to prototype to production

Production

Prog. Logic

Prototype

ARM

Simulation

Simulink

Embedded Coder

HDL Coder

AXI

Interface

Algorithm

Model

Algorithm

Model

Linux

Driver

AXI Bus

Motor

Model Motor System

ARM

System

Code

Vivado Algorithm

C

Programmable Logic

Vivado Algorithm

HDL

AXI Bus

IP1 AXI

Interface

Algorithm

HDL

Linux

Driver

Algorithm

C

IP2

IP3

Motor

53

DEMO1: Simulate Six-step Controller

Specify tests and

simulate response

with continuous time

solver

Model motor and

load with fidelity to

capture dynamics of

interest

Model control loop

C/HDL components

54

How do I get from simulation to prototype?

Six-Step

Commutation


Velocity Control

AX

I-li

te

Hall

Period

Cortex™-A9

Ethernet

Inverter

Module

Hall

Interface

Motor FMC Card

PWM

Iso

lati

on

Velocity Estimate

Algorithm HDL

Specification Model Algorithm C

Specification Model

Open-source

LINUX

55

Generate a bitstream for programmable logic

AX

I-li

te

Programmable Logic

AX

I-li

te

Zynq Support Package enables you to…

Generate bitstream consisting of algorithmic HDL code from models

and interfaces to FPGA pins and AXI-Bus

Algorithm HDL

Specification Model

56

Generate an executable for ARM

Processing System

AX

I-li

te

Cortex™-A9

AX

I-li

te

Zynq Support Package enables

you to…

Generate ARM executable

consisting of algorithmic C code

from models and interfaces to

AXI-Bus

Algorithm C code executes in the

user space of Linux

AXI4-Lite SW driver is

automatically created and

inserted

Algorithm C

Specification Model

Open-source

LINUX

57

Generate an executable for ARM

Processing System

AX

I-li

te

Cortex™-A9

AX

I-li

te

Zynq Support Package enables

you to…

Generate ARM executable

consisting of algorithmic C code

from models and interfaces to

AXI-Bus

Provides data interface between

Simulink and ARM executable via

Ethernet

Ethernet

Algorithm C

Specification Model

Open-source

LINUX

58

Algorithm

C

Algorithm C

Specification Model

DEMO2: Prototype on Zynq with interactive tests

Inverter

Module

Hall

Interface

Motor FMC Card

Iso

lati

on

Switches and scopes in Simulink model act as an

interface to generated executable running on ARM

Algorithm HDL

Specification Model

60

Simulation Phase

● Models designed for simulation

● Algorithm, stimulus, and analysis run in Simulink

● Motor and plant peripherals are simulated

61

Prototype Phase

● Models designed for code generation

● Test bench stimulus and analysis run in Simulink

● Simulink algorithm is converted to code and runs on Zynq

● Interface to hardware motor and plant peripherals

62

How can models help you prototype on Zynq?

63

Prog. Logic

Prototype

ARM

Simulation

Simulink

Embedded Coder

HDL Coder

AXI

Interface

Algorithm

Model

Algorithm

Model

Linux

Driver

AXI Bus

Motor

Model Motor

Algorithm

C

Algorithm

HDL

Zynq Support Package

● Automates integrating

generated C code with an

ARM “parent project”

● Automates wrapping

generated HDL code into an

IP Core and integrating it

with “parent project” for

programmable logic

● Provides a data interface

between Simulink and ARM

Algorithmic code is reused in production

Production

Prog. Logic

Prototype

ARM

Simulation

Simulink

Embedded Coder

HDL Coder

AXI

Interface

Algorithm

Model

Algorithm

Model

Linux

Driver

AXI Bus

Motor

Model Motor

Algorithm

C

Algorithm

HDL

Algorithm

HDL

Algorithm

C

Generate C and HDL for algorithms

Algorithm C Specification Model Generates C code for the algorithm

(i.e. function call) that you can integrate

into your production project

Algorithm HDL Specification Model Generates HDL code for the algorithm

(i.e. entity) that you can integrate into your

production project

65

How can models help you design a controller for Zynq?

● Simulate on your desktop

o Model controller and plant system dynamics

o Design and debug components at control loop fidelity

o Assemble and verify components at implementation fidelity

● Prototype on hardware

o Generate HDL code and build bitstream

o Generate C code and build ARM executable

o Collect hardware results and verify against simulation

● Generate C/HDL code for production

o Generate and review HDL code report

o Generate and review C code report

o Integrate generated code with production environment

66

Motor Control






Motor Control



Agenda

69

Topic








Let’s Take Breath … What Have We Done?

Six-Step

Commutation


Velocity Control

AX

I-li

te

Hall

Period

Cortex™-A9

Ethernet

Inverter

Module

Hall

Interface

Motor FMC Card

PWM

Iso

lati

on

Velocity Estimate

Algorithm HDL

Specification Model Algorithm C

Specification Model

Open-source

LINUX

70

Automation Comes at a Cost …

● Automated prototyping locks the tool flow and BSP

71

Simulation

Prototype

Production

● Production deployment requires flexible tool flows

ARM

Programmable Logic

Algorithmic Code is Reused in Production

72

Production Simulation

Simulink

Embedded Coder

HDL Coder

Algorithm

Model

Algorithm

Model

System

Code

AXI Bus

IP1 AXI

Interface

Algorithm

HDL

Linux

Driver

Algorithm

C

IP2

IP3

Motor

Model System Motor

Vivado Design Suite Accelerates Productivity

73

• IP and System-centric Integration

• Fast, Hierarchical and Deterministic Closure

Comprehensive SoC Design Software

• IP-XACT for IP packaging & integration

• TCL scripting to automate all details

• XDC / SDC constraints language

Industry standard constraint languages

Tight integration with Xilinx SDK

• Embedded software development and debug

Parallel Development on Zynq AP SoC

74

Software Development

• Standard ARM processor

development

• Design/debug using Xilinx SDK or

other standard SW over JTAG

• Programmable Logic need not be

programmed

Hardware Development

• Standard FPGA development

• Design/debug using Vivado

• Load Programmable Logic via

JTAG without PS during

development phase

SDK Vivado

Vivado IP Packager Enabling Reuse and Delivering Fully Functional IP Subsystems

IP Packager Source (C, RTL, IP)

Simulation models

Documentation

Example Designs

Test bench

Standardized IP-XACT

IP Subsystem

Xilinx IP

3rd Party IP

User IP

Uses multiple plug-and-play forms of IP to

implement functional subsystem

Includes software drivers and API

Accelerates integration and productivity

Vivado IP Integrator

● Accelerates hardware design

productivity through design reuse

o Graphical IP assembly

o Correct-by-construction

o System centric

● Generates IP subsystems

o Supports multiple plug-and-play

IP formats

o Generates software drivers and

APIs

● Board and silicon aware

o Built in support for Xilinx

development baseboards

Page 76

Subsystems Xilinx 3rd Party User

Vivado IP Catalog - Standardized IP-XACT

Demo: FOC Simulink Controller in WebView

77

ADI Base Reference Design – detailed diagram

78


IIO Scope

Cortex™-A9

Desktop

LINUX

Power

Inverters

AD-FMCMOTCON1

ADC (Ia, Ib, Vbus)

P

W

M

Algorithm C A

XI

Inte

rco

nn

ec

t

ΣΔ ADC

Encoder

Interface Encoder

(Position,Speed)

USB 2.0

Ethernet

UART

Iso

lati

on

DMA

DMA

DMA

A

X

I

A

X

I

A

X

I

A

X

I HDMI DMA

HDL code C code

Field

Oriented

Controller

Algorithm

HDL

MathWorks HDL Peripheral with AXI-Lite Interface

● Generate HDL code with AXI-Lite interface

● Includes algorithm plus AXI-Lite register logic

● Integrate within Vivado top-level project

79

AX

I In

terc

on

nect

AX

I In

terc

on

nect

AXI-Lite Wrapper

Algorithm

HDL

Programmable Logic

Add HDL Code as AXI-Lite IP in Vivado Design Suite

80

IP Packager

HDL Code

Vivado Project

Vivado IP Integrator

AX

I In

terc

on

ne

ct Programmable Logic

PL bitstream (.bit)

AXI-Lite Wrapper

Algorithm

HDL

Boot

SD

Card

Add C Code in Xilinx Software Development Kit

81

Xilinx SDK

Boot.bin

C Code

PL bitstream

User Space Application

FSBL + U-Boot

User Application

LINUX

AX

I In

terc

on

ne

ct

DeviceTree (.dtb)

Processing System

Linux Kernel

Root File

System .ELF

SD Card

AXI-Lite Wrapper

SW / HW Integration of Simulink model in Zynq

● Reuse MathWorks generic UIO driver or provide custom

peripheral driver

● Automated build processes are possible with MATLAB

and TCL scripting

82

AX

I In

terc

on

ne

ct

Algorithm

HDL

User Space

Application

LINUX

Algorithm C

AX

I In

terc

on

ne

ct

UIO

Driver

Agenda

83

Topic








Demo 3: Deploying to Zynq with Vivado

● Adding a custom HDL module to Base Reference Design

84

Adding SW to the ADI Base Reference Design

85


IIO Scope

Cortex™-A9

Desktop

LINUX

Power

Inverters

AD-FMCMOTCON1

ADC (Ia, Ib, Vbus)

P

W

M

User Application A

XI

Inte

rco

nn

ec

t

ΣΔ ADC

Encoder

Interface Encoder

(Position,Speed)

USB 2.0

Ethernet

UART

Iso

lati

on

DMA

DMA

A

X

I

A

X

I

A

X

I

A

X

I HDMI DMA

HDL code C code

Field

Oriented

Controller

AXI-Lite Wrapper

Adding SW to the ADI Base Reference Design

● Add custom C code application

● Use MathWorks generic UIO or a custom driver

● Update Device Tree

86

AX

I In

terc

on

ne

ct

Algorithm

HDL

User Space

Application

LINUX

Algorithm C

AX

I In

terc

on

ne

ct

UIO

Driver

What You’ve Seen Today

● Zynq Intelligent Drives Kit is flexible development platform for high performance motor control applications

● Analog Devices production grade Linux reference design with FMCMOTCON1 high performance servo module

● The MathWorks Zynq workflow enables rapid prototype on the Xilinx Zynq®-7000 All Programmable SoC

● Deploying Simulink models into Zynq-based motor control using Xilinx Vivado® Design Suite

87

Next Steps

Purchase the Zynq Intelligent Drives Kit with MathWorks Motor Control Design Package

o em.avnet.com/zynq7000idk

Download Analog Devices Reference Designs

o wiki.analog.com o Full C/HDL/Linux source

Explore Zynq Support Packages and Simulink Motor Control Models

o www.mathworks.com/zidk

88

http://www.wiki.analog.com/


Motor Control Design Package from MathWorks

● Complete turnkey solution for motor control algorithm development, including C and HDL code generation and target support for the Zynq-7000 AP SoC.

● Order with the Zynq Intelligent Drives Kit

● AES-ZIDK-ADI-DYNO-G-MATW-ANUL $19,215 USD

89

Includes

MATLAB,

Simulink and

10 products

THANK YOU!

90

Documents

Motor Control From Concept to Production with Zynq …zedboard.org/sites/default/files/Zynq Motor Design Seminar OnDemand... · Motor Control From Concept to Production with Zynq