View
215
Download
1
Tags:
Embed Size (px)
Citation preview
15 oct 2002 University of Geneva 2
• schematic modifications due to the PDR• JTAG chain• serial impedance adaptation• serializer back lines• fuse on +3.3V for each mezzanine
• water cooling and temperature probes• adding of LED on the front panel• need some feedback about the ORx & GLinks
problems From Nevis or Jingbo Ye
• meeting with LAPP (J.-M. Nappa) about the PCB routing:
• change on the stack-up• try to use the automatic router
General StatusGeneral Status
15 oct 2002 University of Geneva 3
Stack-upStack-up
(specctraquest)m mils Zo trace 125um
Conductor 40 1.57 63.4
FR4 120 4.72Plane 17.5 0.69FR4 300 11.81
Conductor 17.5 0.69 66.0
FR4 300 11.81Plane 17.5 0.69FR4 220 8.66
Conductor 17.5 0.69 66.1
FR4 300 11.81Conductor 17.5 0.69 66.1
FR4 220 8.66Plane 17.5 0.69FR4 300 11.81
Conductor 17.5 0.69 66.0
FR4 300 11.81Plane 17.5 0.69FR4 120 4.72
Conductor 40 1.57 63.4
2400 94.49
Stackup ROD
15 oct 2002 University of Geneva 5
• There is still a lot of things to do.
• We hope to gain time with the automatic router• But before to use it.
• finalise the schematics• place precisely all the components on the board
• resistors• capacitors• jumper
• extract manually lines from the BGA devices
ConclusionConclusion