0: Introduction Slide 1CMOS VLSI Design

Motherboard PCB

0: Introduction Slide 2CMOS VLSI Design

Surface Mount PCB

0: Introduction Slide 3CMOS VLSI Design

Surface Mount Package

0: Introduction Slide 4CMOS VLSI Design

Chip Manufacturing

Single dieWafer

0: Introduction Slide 5CMOS VLSI Design

0: Introduction Slide 6CMOS VLSI Design

Inverter Mask SetTransistors and wires are defined by masksCross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

0: Introduction Slide 7CMOS VLSI Design

Inverter Cross SectionSubstrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky DiodeUse heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+

0: Introduction Slide 8CMOS VLSI Design

Detailed Mask ViewsSix masks– n-well– Polysilicon– n+ diffusion– p+ diffusion– Contact– Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

0: Introduction Slide 9CMOS VLSI Design

LayoutChips are specified with set of masksMinimum dimensions of masks determine transistor size (and hence speed, cost, and power)Feature size f = distance between source and drain– Set by minimum width of polysilicon

Feature size improves 30% every 3 years or soNormalize for feature size when describing design rulesExpress rules in terms of λ = f/2– E.g. λ = 0.3 µm in 0.6 µm process

0: Introduction Slide 10CMOS VLSI Design

Simplified Design RulesConservative rules to get you started

0: Introduction Slide 11CMOS VLSI Design

Inverter LayoutTransistor dimensions specified as Width / Length– Minimum size is 4λ / 2λ, sometimes called 1 unit– In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm

long

0: Introduction Slide 12CMOS VLSI Design

Inverter (2nd example)

0: Introduction Slide 13CMOS VLSI Design

Example: NAND3Horizontal N-diffusion and p-diffusion stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND rail at bottom32 λ by 40 λ

0: Introduction Slide 14CMOS VLSI Design

Stick DiagramsStick diagrams help plan layout quickly– Need not be to scale– Draw with color pencils or dry-erase markers

0: Introduction Slide 15CMOS VLSI Design

Wiring TracksA wiring track is the space required for a wire– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch

Transistors also consume one wiring track

0: Introduction Slide 16CMOS VLSI Design

Well spacingWells must surround transistors by 6 λ– Implies 12 λ between opposite transistor flavors– Leaves room for one wire track

0: Introduction Slide 17CMOS VLSI Design

Example: O3AISketch a stick diagram for O3AI– ( )Y A B C D= + +