MOSFETs-2015-02-23

CHAPTER 3

MOS Field-Effect Transistors

(MOSFETs) MICROELECTRONIC CIRCUITS

Sedra/Smith

Sixth Edition

Oxford University Press

2011

2015/2/23 1 Chih-Wen Lu

In This Chapter You Will Learn

• Device Structure and Physical.

• Current-Voltage Characteristics.

• MOSFET Circuits at DC.

• Applying the MOSFET in Amplifier Design.

• Small-Signal Operation and Models.

• Basic MOSFET Amplifier.

• Biasing in MOS Amplifier Circuits.

• Discrete-Circuit MOS Amplifiers.

• The Body Effect and Other Topics.

2015/2/23 Chih-Wen Lu 2

Introduction

• The voltage between two terminals of the FET controls the current

in the third terminal.

• The FET can be used both as an amplifier and as a switch.

• The current-control mechanism is based on an electric field

established by the voltage applied to the control terminal.

• The current is conducted by only one type of carrier (electrons or

holes).

2015/2/23 Chih-Wen Lu 3

Introduction (cont’d)

2015/2/23 Chih-Wen Lu 4

MOSFET

JFET

FETs

Enhancement-Type MOSFET

Depletion-Type MOSFET

FETs: Field-Effect Transistors

MOSFET: metal-oxide semiconductor field-effect transistor

JFET: Junction field-effect transistor

3.1 Device Structure and Physical Operation

• The enhancement-type MOSFET is the most widely used field-

effect transistor. In this section, we shall study its structure and

physical operation. This will lead to the current-voltage

characteristics of the device, studied in the next section.

2015/2/23 Chih-Wen Lu 5

3.1 Device Structure and Physical Operation (cont’d)

• Physical structure of the enhancement-type NMOS transistor: (a)

perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W =

0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the

range of 2 to 50 nm.

2015/2/23 Chih-Wen Lu 6


• Four terminals: Gate (G), Source (S), Drain (D), and Substrate or

body (B)

• Polysilicon is used to form the gate electrode in the modern

technology.

2015/2/23 Chih-Wen Lu 7


2015/2/23 Chih-Wen Lu 8


2015/2/23 Chih-Wen Lu 9


• The substrate forms pn junctions with the source and drain regions.

• These pn junctions are kept reversed-biased at all times.

• Thus, the substrate will be considered as having no effect on device

operation, and the MOSFET will be treated as a three-terminal

device, with the terminals being the gate, source, and drain.

2015/2/23 Chih-Wen Lu 10


• A voltage applied to the gate controls current flow between source

and drain.

• This current will flow in the longitudinal direction from drain to

source in the region labeled “channel region.”

2015/2/23 Chih-Wen Lu 11


• Operation with No Gate Voltage.

• With no bias voltage applied to the gate, two back-to-back diodes

exit in series between drain and source.

• These back-to-back diodes prevent current conduction from drain

to source when a voltage vDS is applied.

2015/2/23 Chih-Wen Lu 12


• Creating a Channel for Current Flow.

• The enhancement-type NMOS transistor with a positive voltage

applied to the gate. An n channel is induced at the top of the

substrate beneath the gate.

2015/2/23 Chih-Wen Lu 13


• Ground the source and drain and apply a positive voltage to the

gate.

• The positive voltage on the gate causes the free holes to be repelled

from the region of the substrate under the gate (channel region).

• As well, the positive gate voltage attracts electrons from the n+

source and drain regions into the channel region.

2015/2/23 Chih-Wen Lu 14


• When a sufficient number of electrons accumulate near the surface

of substrate under the gate, an n region is in effect created,

connecting the source and drain regions.

2015/2/23 Chih-Wen Lu 15


• Now if a voltage is applied between drain and source, current flows

through this induced n region, carried by the mobile electrons.

Correspondingly, this MOSFET is called an n-channel MOSFET

or, an NMOS transistor.

2015/2/23 Chih-Wen Lu 16


• An n-channel MOSFET is formed in a p-type substrate.

• The channel is created by inverting the substrate surface from p

type to n type.

• Hence the induced channel is also called an inversion layer.

2015/2/23 Chih-Wen Lu 17


• The value of vGS at which a sufficient number of mobile electrons

accumulate in the channel region to form a conducting channel is

called the threshold voltage and is denoted Vt. Vt for an n-channel

FET is positive.

2015/2/23 Chih-Wen Lu 18


• The gate and body of the MOSFET form a parallel-plate capacitor

with the oxide layer acting as the capacitor dielectric.

• The positive gate voltage causes positive charge to accumulate on

the top plate of the capacitor (gate electrode).

2015/2/23 Chih-Wen Lu 19


• The corresponding negative charge on the bottom plate is formed

by the electrons in the induced channel.

• An electric field thus develops in the vertical direction.

• It is the field that controls the amount of charge in the channel, and

thus determines the channel conductivity and the current that will

flow through the channel when a voltage vDS is applied.

2015/2/23 Chih-Wen Lu 20


• Applying a Small vDS

• An NMOS transistor with vGS > Vt and with a small vDS applied.

The device acts as a resistance whose value is determined by vGS.

Specifically, the channel conductance is proportional to vGS – Vt’

and thus iD is proportional to (vGS – Vt) vDS.

2015/2/23 Chih-Wen Lu 21


• Apply a small positive voltage vDS.

• A current in the channel, iD, will flow from drain to source.

• The magnitude of iD depends on the density of electrons in the

channel, which in turn depends on the magnitude of vGS.

2015/2/23 Chih-Wen Lu 22


• For vGS = Vt the channel is just induced and current is still small.

• As vGS exceeds Vt, more electrons are attracted into the channel.

• The result is a channel of increased conductance.

• In fact, the conductance of the channel is proportional to the excess

gate voltage (vGS – Vt). iD is proportional to vGS – Vt and to vDS.

2015/2/23 Chih-Wen Lu 23


• The iD–vDS characteristics of the MOSFET when the voltage

applied between drain and source, vDS, is kept small. The device

operates as a linear resistor whose value is controlled by vGS.

2015/2/23 Chih-Wen Lu 24


• The MOSFET is operating as a linear resistance whose value is

controlled by vGS.

• The resistance is infinite for vGS < Vt, and its value decreases as vGS

exceeds Vt.

2015/2/23 Chih-Wen Lu 25


• Increasing vGS above Vt enhances the channel, hence the names

enhancement-mode operation and enhancement-type MOSFET.

2015/2/23 Chih-Wen Lu 26


• Operation as vDS Is Increased

• Operation of the enhancement NMOS transistor as vDS is

increased. The induced channel acquires a tapered shape, and its

resistance increases as vDS is increased. Here, vGS is kept constant

at a value > Vt.

2015/2/23 Chih-Wen Lu 27


• As vDS is increased.

• The voltage between the gate and points along the channel

decreases from vGS at the source end to vGS – vDS at the drain end.

• The channel will take the tapered form.

• As vDS is more increased, the channel more tapered and its

resistance increases.

2015/2/23 Chih-Wen Lu 28


• Thus iD – vDS curve does not continue as a straight line but bends.

• Eventually, when vDS is increased to the value that reduces the

voltage between gate and drain to Vt, that is, vGS – vDS = Vt or vDS =

vGS – Vt the channel depth at the drain end decreases to almost zero,

and the channel is said to be pinched off.

2015/2/23 Chih-Wen Lu 29

The drain current iD

versus the drain-to-

source voltage vDS

for an enhancement-

type NMOS

transistor operated

with vGS > Vt.


• Increase vDS beyond this value has little effect on the channel

shape, and the current through the channel remains constant at the

value reached for vDS = vGS – Vt

• The drain current thus saturates at this value, and the MOSFET is

said to have entered the saturation region.

2015/2/23 Chih-Wen Lu 30


• The voltage vDS at which saturation occurs is denoted vDSsat, vDSsat =

vGS - Vt

• Obviously, for every value of vGS ≧ Vt, there is a corresponding

value of vDSsat. The device operates in the saturation region if vDS

≧ vDSsat .

• The region of the iD – vDS characteristic obtained for vDS < vDSsat is

called the triode region.

2015/2/23 Chih-Wen Lu 31


• vDS is increased while vGS is kept constant.

• Theoretically, any increase in vDS above vDSsat (which is equal to

vGS - Vt ) has no effect on the channel shape and simply appears

across the depletion region surrounding the channel and the n+

drain region.

2015/2/23 Chih-Wen Lu 32

Increasing vDS causes the channel to acquire a tapered shape.

Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the

drain end. Increasing vDS above vGS – Vt has little effect

(theoretically, no effect) on the channel’s shape.


• Derivation of the iD-vDs Relation

• A voltage vGS is applied between gate and source with vGS > Vt, and

a voltage vDS is applied between drain and source.

• First consider operation in the triode region. i.e. let vDS < vGS – Vt.

• The channel will have the tapered shape illustrated in this figure.

2015/2/23 Chih-Wen Lu 33

Derivation of the iD–vDS

characteristic of the

NMOS transistor.


• In the MOSFET, the gate and the channel region form a

parallelplate capacitor for which the oxide layer serves as a

dielectric. If the capacitance per unit gate area is denoted Cox and

the thickness of the oxide layer is tox, then

• where eox is the permittivity of the silicon oxide,

and tox the thickness of the oxide layer.

2015/2/23 Chih-Wen Lu 34

oxox

ox

Ct

e

12 11

03.9 3.9 8.854 10 3.45 10 F/moxe e


• Consider an infinitesimal portion of the channel of length dx at a

point x from the source.

• The electron charge dq(x) in this infinitesimal portion can be

expressed as

2015/2/23 Chih-Wen Lu 35

( )ox GS tdq x C Wdx v v x V


• The voltage vDS produces an electric field along the channel in the

negative x direction. At point x, this field can be expressed as

2015/2/23 Chih-Wen Lu 36

dv x

E xdx


• The electric field E(x) causes the electron charge dq(x) to drift

toward the drain with a velocity dx/dt

where mn is the electron mobility in the channel.

2015/2/23 Chih-Wen Lu 37

n n

dv xdxE x

dt dxm m


• The resulting drift current

2015/2/23 Chih-Wen Lu 38

ox GS t n

n ox GS t

dq x dv xdq dxi C W v v x V

dt dx dt dx

dv xC W v v x V

dx

m

m


• Although evaluated at a particular point in the channel, the current i

must be constant at all points along the channel, and thus i must be

the negative of the drain-to-source current iD, giving

2015/2/23 Chih-Wen Lu 39

( )

( )

D n ox GS t

D n ox GS t

dv xi i C W v v x V

dx

i dx C W v V v x dv x

m

m


• Integrating both sides of this equation for x = 0 to x = L, and for

v(0) = 0 to v(L) = vDS.

• Gives

• This is the expression for the iD – vDS characteristic in the triode

region.

2015/2/23 Chih-Wen Lu 40

0 0

DSL v

D n ox GS ti dx C W v V v x dv xm

21

2D n ox GS t DS DS

Wi C v V v v

Lm


• The expression for the saturation region can be obtained by

substituting vDS = vGS – Vt, resulting in

2015/2/23 Chih-Wen Lu 41

21

2D n ox GS t

Wi C v V

Lm


• Process transconductance parameter

2015/2/23 Chih-Wen Lu 42

'

n n oxk Cm


• Triode region:

• Saturation region:

where

• The drain current is proportional to the ratio of the channel width

W to the channel length L, known as the aspect ratio of the

MOSFET.

2015/2/23 Chih-Wen Lu 43

2'

2

1DSDStGSnD vvVv

L

Wki

2'

2

1tGSnD Vv

L

Wki

oxnn Ck m'


• Example

• Consider a process technology for which Lmin = 0.4 mm, tox = 8 nm,

mn = 450 cm2/V˙s, and Vt = 0.7 V.

(a) Find Cox and k /

n.

(b) For a MOSFET with W / L = 8 mm/0.8 mm, calculate the values of

VGS and VDSmin needed to operate the transistor in the saturation

region with a dc current ID = 100 mA.

(c) For the device in (b), find the value of VGS required to cause the

device to operate as a 1000-W resistor for very small vDS.

2015/2/23 Chih-Wen Lu 44


• Solution

• (a) Find Cox and k /

n.

2015/2/23 Chih-Wen Lu 45

113 2

9

2

2 2

8 2

-6

2

3.45 104.32 10 F/m

8 10

4.32 fF/ m

450 (cm /V s) 4.32 (fF/ m )

450 10 ( m /V s)

194 10 (F/V s)

194 A/V

oxox

ox

n n ox

Ct

k C

e

m

m m

m

m


• (b) calculate the values of VGS and VDSmin needed to operate the

transistor in the saturation region with a dc current ID = 100 mA.

• For operation in the saturation region,

2015/2/23 Chih-Wen Lu 46

21( )

2D n GS t

Wi k v V

L

21 8100 194 ( 0.7)

2 0.8GSV

0.7 0.32 VGSV

Thus,

which results in

or

and

1.02 VGSV

min 0.32 VDS GS tV V V


• (c) For the device in (b), find the value of VGS required to cause the

device to operate as a 1000-W resistor for very small vDS.

• For the MOSFET in the triode region with vDS very small,

2015/2/23 Chih-Wen Lu 47

( )D n GS t DS

Wi k v V v

L

small

1 ( )

DS

DSDS

D v

n GS t

vr

i

Wk V V

L

6

11000

194 10 10( 0.7)GSV

From which the drain-to-source resistance rDS can be found as

Thus,

which yields

Thus,

0.7 0.52 VGSV

1.22 VGSV


• The p-channel MOSFET

• A p-channel enhancement-type MOSFET (PMOS transistor) is

fabricated on an n-type substrate with p+ regions for the drain and

source, and has holes as charge carriers.

• The device operates in the same manner as the n-channel device

except that vGS and vDS are negative and the threshold voltage Vt is

negative.

• Also, the current iD enters the source terminal and leaves through

the drain terminal.

2015/2/23 Chih-Wen Lu 48


• Complementary MOS or CMOS

• Both PMOS and NMOS transistors are utilized.

• NMOS transistor is implemented directly in the p-type substrate.

• PMOS transistor is fabricated in a specially created n region,

known as n well.

• The two devices are isolated from each other by a thick region of

oxide that functions as an insulator.

2015/2/23 Chih-Wen Lu 49

3.2 Current-Voltage Characteristics

• These characteristics can be measured at dc or at low frequencies

and thus are called static characteristics.

• The dynamic effect that limit the operation of the MOSFET at high

frequencies and high switching speeds will be discussed in Section

3.8.

2015/2/23 Chih-Wen Lu 50

3.2 Current-Voltage Characteristics (cont’d)

• Circuit Symbol

• (a) Circuit symbol for the n-channel enhancement-type MOSFET.

(b) Modified circuit symbol with an arrowhead on the source

terminal to distinguish it from the drain and to indicate device

polarity (i.e., n channel). (c) Simplified circuit symbol to be used

when the source is connected to the body or when the effect of the

body on device operation is unimportant.

2015/2/23 Chih-Wen Lu 51


• The iD – vDS Characteristics

• There are three distinct regions of operation: the cutoff region, the

triode region, and the saturation region.

• The saturation region is used if FET is to operate as an amplifier.

• For operation as a switch, the cutoff and triode regions are utilized.

2015/2/23 Chih-Wen Lu 52


• To operate the MOSFET in the triode region we must first induce a

channel.

• And then keep vDS small enough so that the channel remains

continuous.

• This is achieved by ensuring that the gate-to-drain voltage is

• where kn’ = mnCox is the process transconductance parameter;

2015/2/23 Chih-Wen Lu 53

(Induced channel)GS tv V

' 2

(Continuous channel)

Continuous channel

1

2

GD t

GS DS t

DS GS t

D n GS t DS DS

v V

v v V

v v V

Wi k v V v v

L

DSGS

SDGSGD

vv

vvv


2015/2/23 Chih-Wen Lu 54

If vDS is sufficiently small so that we can neglect the v2DS term.

This linear relationship represents the operation of the MOS transistor

as a linear resistance rDS,

whose value is controlled by vGS.

'

D n GS t DS

Wi k v V v

L

1

'smallDS

GS GS

DSvDS n GS t

Dv V

v Wr k v V

i L


2015/2/23 Chih-Wen Lu 55

It is also useful to express rDS in terms of the gate-to-source overdrive

Voltage,

as

'1DS n OV

Wr k V

L

OV GS tV V V


2015/2/23 Chih-Wen Lu 56

To operate the MOSFET in the saturation, a channel must be induced,

and pinched off at the drain end by raising vDS to a value that results

in the gate-to-drain voltage falling below Vt,

This condition can be expressed explicitly in terms of vDS as

Induced channelGS tv V

Pinched off channelGD tv V

Pinched off channelDS GS tv v V


2015/2/23 Chih-Wen Lu 57

The boundary between the triode region and the saturation region is

characterized by

BoundaryDS GS tv v V


2015/2/23 Chih-Wen Lu 58

Substituting the value of vDS into

Gives the saturation value of the current iD as

Thus in saturation the MOSFET

provides a drain current whose

value is independent of the drain

voltage vDS and is determined

by the gate voltage vGS according

to the square-law relationship.

2'1

2D n GS t

Wi k v V

L

' 21

2D n GS t DS DS

Wi k v V v v

L


2015/2/23 Chih-Wen Lu 59

2'1

2D n GS t

Wi k v V

L

Figure The iD–vGS

characteristic for an

enhancement-type NMOS

transistor in saturation (Vt = 1

V, k’n W/L = 1.0 mA/V2).


2015/2/23 Chih-Wen Lu 60

Figure Large-signal equivalent-circuit model of an n-channel MOSFET

operating in the saturation region.


2015/2/23 Chih-Wen Lu 61

Referring back to the iD-vDS characteristics, we note

that the boundary between the triode and the saturation regions is

shown as a broken-line curve. Since this curve is characterized by

vDS = vGS – Vt, its equation can be found by substituting for vGS – Vt

by in either the triode-region equation or the saturation-

region equation.

This result is

' 21

2D n DS

Wi k v

L


2015/2/23 Chih-Wen Lu 62

The relative levels of the terminal voltages of the enhancement

NMOS transistor for operation in the triode region and in the

saturation region.

Figure The relative levels of

the terminal voltages of the

enhancement NMOS

transistor for operation in the

triode region and in the

saturation region.


• Finite Output Resistance in Saturation

2015/2/23 Chih-Wen Lu 63

Figure Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL).

• Note, however, that (with depletion-layer widening) the channel

length is in effect reduced, from L to L-ΔL, a phenomenon known

as channel-length modulation.


2015/2/23 Chih-Wen Lu 64

2

2

2

1( )

2

1 1( )

2 1 ( / )

11 ( )

2

D n GS t

n GS t

n GS t

Wi k v V

L L

Wk v V

L L L

W Lk v V

L L


2015/2/23 Chih-Wen Lu 65

where we have assumed that ( / ) 1, if we

assume that is proportional to ,

where is a process-technology parameter with the

dimension of m/V, we obtain for

1

,

12

DS

D

Ds

D

n DS

L v

Wi k v

L

L L

L v

L

i

m

2

Usually, / is denot

( )

ed ,

GS tv V

L

L


2015/2/23 Chih-Wen Lu 66

2'1

12

D n GS t DS

Wi k v V v

L


2015/2/23 Chih-Wen Lu 67

2'1

12

D n GS t DS

Wi k v V v

L

Figure Effect of vDS on iD in

the saturation region. The

MOSFET parameter VA

depends on the process

technology and, for a given

process, is proportional to the

channel length L.


2015/2/23 Chih-Wen Lu 68

• From this figure we observe that when the straight-line iD-vDS

characteristics are extrapolated they intercept the vDS-axis at the

point vDS = -VA, where VA is a positive voltage.

1AV


2015/2/23 Chih-Wen Lu 69

A AV V L

where V /

A is entirely process-technology dependent with the

dimensions of V/m m.

1

constantGS

Do

DS v

ir

v

1

'2

2

no GS t

k Wr V V

L

1 Ao

D D

Vr

I I

Thus the output resistance is inversely

proportional to the dc bias current ID.


2015/2/23 Chih-Wen Lu 70

Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation,

incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS

and is given by Eq. (4.22).


• Characteristics of the p-Channel MOSFET

2015/2/23 Chih-Wen Lu 71

Figure (a) Circuit symbol for the p-

channel enhancement-type

MOSFET. (b) Modified symbol with

an arrowhead on the source lead. (c)

Simplified circuit symbol for the

case where the source is connected to

the body. (d) The MOSFET with

voltages applied and the directions of

current flow indicated. Note that vGS

and vDS are negative and iD flows out

of the drain terminal.


2015/2/23 Chih-Wen Lu 72

To induce a channel

where the threshold voltage Vt is negative.

or, equivalently,

To operate in the triode region vDS must satisfy

Induced-channelGS tv V

Continuous channelDS GS tv v V

SG tv V


2015/2/23 Chih-Wen Lu 73

Current (triode region)

where vGS, Vt, and vDS are negative and the transconductance

parameter kp’ is given by

where mp is the mobility of holes in the induced p-channel.

' 21

2D p GS t DS DS

Wi k v V v v

L

'

p p OXk Cm


2015/2/23 Chih-Wen Lu 74

To operate in saturation, vDS must satisfy the relationship.

Current

where vGS, Vt, , and vDS are all negative.

Pinched off channelDS GS tv v V

2'1

12

D p GS t DS

Wi k v V v

L


• Relative levels of the terminal voltage of the enhancement-type

PMOS transistor for operation in the triode region and in the

saturation region.

2015/2/23 Chih-Wen Lu 75

Figure The relative levels of the

terminal voltages of the

enhancement-type PMOS

transistor for operation in the

triode region and in the saturation

region.


• The Role of the Substrate —The body Effect

• In many applications the substrate terminal is connected to the

source terminal, which results in the pn junction between the

substrate and the induced channel having a constant zero bias.

• In such a case the substrate does not play any role in circuit

operation and its existence can be ignored altogether.

2015/2/23 Chih-Wen Lu 76


• In integrated circuits, the substrate is usually connected to the most

negative power supply in an NMOS circuit.

• The resulting reverse-bias voltage between source and body (VSB)

in an n-channel device) will have an effect on device operation.

2015/2/23 Chih-Wen Lu 77


2015/2/23 Chih-Wen Lu 78

• The reverse bias voltage will widen the depletion region.

• The effect of VSB on the channel can be most conveniently

represented as a change in the threshold voltage Vt.

• Increasing VSB results in an inverse in Vt according to the relationship

where Vt0 is the threshold voltage for VSB = 0; ff is a physical

parameter with (2 ff) typically 0.6; g is a fabrication-process parameter

given by

where NA is the doping concentration of the p-type substrate, and es

is the permittivity of silicon.

0 2 2t t f SB fV V Vg f f

2 A s

OX

qN

C

eg

3.3 MOSFET Circuits at DC

• Having studied the current-voltage characteristics of MOSFETs,

we now consider circuits in which only dc voltages and currents

are of concern.

2015/2/23 Chih-Wen Lu 79

3.3 MOSFET Circuits at DC (cont’d)

• Example

• Design the circuit so that the transistor

operates at ID = 0.4 mA and VD = +0.5 V.

The NMOS transistor has Vt = 0.7 V, mnCox =

100 m A/V2, L = 1 m m, and W = 32 m m.

Neglect the channel-length modulation effect

(i.e., assume that = 0).

2015/2/23 Chih-Wen Lu 80


• Solution

• Since VD = 0.5 V is greater than VG, this means the NMOS

transistor is operating in the saturation region, and we use the

saturation-region expression of iD to determine the required value

of iD to determine the required value of VGS,

2015/2/23 Chih-Wen Lu 81

21 32400 100

2 1

which results in

0.5 V

Thus,

0.7 0.5 1.2 V

OV

OV

GS t OV

V

V

V V V

21( )

2D n ox GS t

WI C V V

Lm


2015/2/23 Chih-Wen Lu 82

1.2 ( 2.5)3.25 k

0.4

S SSS

D

V VR

I

W

The gate is at ground potential. Thus the source must be at -1.2V, and

the required value of RS can be determined from

To establish a dc voltage of +0.5 V at the drain,

we must select RD as follows:

2.5 0.55 k

0.4

DD DD

D

V VR

I

W


• Example

• Design the circuit in this figure to obtain a current ID of 80 m A.

Find the value required for R, and find the dc voltage VD. Let the

NMOS transistor have Vt = 0.6 V, mnCox = 200 m A/V2, L = 0.8 m m,

and W = 4 m m. Neglect the channel-length modulation effect (i.e.,

assume = 0).

2015/2/23 Chih-Wen Lu 83


2015/2/23 Chih-Wen Lu 84

Solution:

2

2

1( )

2

1

2

D n ox GS t

n ox OV

WI C V V

L

WC V

L

m

m

2

( / )

2 800.4 V

200 (4 / 0.8)

0.6 0.4 1 V

1 V

3 125 k

0.080

DOV

n ox

GS t OV

D G

DD D

D

IV

C W L

V V V

V V

V VR

I

m

W


• Example

• Design the circuit in this figure to establish a drain voltage of 0.1 V.

What is the effective resistance between drain and source at this

operating point? Let Vt = 1 V and k /

n ( W / L ) = 1 mA/V2.

2015/2/23 Chih-Wen Lu 85


2015/2/23 Chih-Wen Lu 86

Solution:

21( )

2

11 (5 1) 0.1 0.01 0.395 mA

2

5 0.112.4 k

0.395

D n GS t DS DS

D

DD DD

D

WI k V V V V

L

I

V VR

I

W

Since the drain voltage is lower than the gate voltage by 4.9 V and Vt =

1 V, the MOSFET is operating in the triode region. Thus the current ID

is given by

0.1253

0.395

DSDS

D

Vr

I W

Since the transistor is operating in the triode region with a small VDS,

the effective drain-to-source resistance can be determined as follows:


• Example

• Analyze the circuit shown in this figure to determine the voltages at

all nodes and the currents through all branches. Let Vt = 1 V and k /

n

( W / L ) = 1 mA/V2. Neglect the channel-length modulation effect

(i.e., assume = 0).

2015/2/23 Chih-Wen Lu 87


• Solution

• Since the gate current is zero, the voltage at the gate is simply

determined by the voltage divider formed by the two 10-MW

resistors,

2015/2/23 Chih-Wen Lu 88

2

2 1

1010 5 V

10 10

GG DD

G G

RV V

R R


2015/2/23 Chih-Wen Lu 89

which this positive voltage at the gate, the NMOS transistor will be

turned on. We do not know, however, whether the transistor will be

operating in the saturation region or in the triode region. We shall

assume saturation-region operation, solve the problem, and then check

the validity of our assumption. Obviously, if our assumption turns out

not to be valid, we will have to solve the problem again for triode-

region operation. Refer to the previous figure. Since the voltage at the

gate is 5 V and the voltage at the source is ID (mA) X 6 (kW) = 6 ID, we

have

Thus ID is given by

2

2

1( )

2

11 (5 6 1)

2

D n GS t

D

WI k V V

L

I

5 6GS DV I


2015/2/23 Chih-Wen Lu 90

which results in the following quadratic equation in ID:

This equation yields two values for ID : 0.89 mA and 0.5 mA. The first

value results in a source voltage of 6 X 0.89 = 5.34, which is greater

than the gate voltage and does not make physical sense as it would

imply that the NMOS transistor is cut off. Thus,

Since VD > VG – Vt, the transistor is

operating in saturation, as initially assumed.

0.5 mA

0.5 6 3 V

5 3 2 V

10 6 0.5 7 V

D

S

GS

D

I

V

V

V

218 25 8 0D DI I


• Example

• Design the circuit of this figure so that the transistor operates in

saturation with ID = 0.5 mA and VD = +3 V. Let the enhancement-

type PMOS transistor have Vt = -1 V and k /

n ( W / L ) = 1 mA/V2 .

Assume = 0. What is the largest value that RD can have while

maintaining saturation- region operation?

2015/2/23 Chih-Wen Lu 91


2015/2/23 Chih-Wen Lu 92

Since the MOSFET is to be in saturation, we can write

Substituting ID : 0.5 mA and k /

p W / L = 1 mA/V2 and recalling that for

a PMOS transistor VOV is negative, we obtain

and

Since the source is at +5 V, the gate voltage must be set to +3 V. Thus

can be achieved by the appropriate selection of the values of RG1 and

RG2. and possible selection is RG1 = 2 MW and RG2 = 3 MW.

1VOVV

2

21( )

2

1

2

D p GS t

p OV

WI k V V

L

Wk V

L

1 1 2 VGS t OVV V V


2015/2/23 Chih-Wen Lu 93

The value of RD can be found from

Saturation-mode operation will be maintained up to the point that VD

exceeds VG by |Vt|; that is, until

This value of drain voltage is obtain with RD given by

max 3 1 4 VDV

36 k

0.5

DD

D

VR

I W

48 k

0.5DR W


• Example

• The NMOS and PMOS transistors in the circuit of Fig. 4.25(a) are

matched with k /

n ( Wn / Ln ) = k /

p ( Wp / Lp ) = 1 mA/V2 and Vtn = -

Vtp = 1 V. Assuming = 0 for both devices, find the drain currents

iDN and iDP, as well as the voltage vO, for vI = 0 V, +2.5 V, and -2.5

V.

2015/2/23 Chih-Wen Lu 94


• Solution

2015/2/23 Chih-Wen Lu 95

The circuit for the case vI = 0 V. We note that since QN and QP are

perfectly matched and are operating at equal |VGS| (2.5 V), the circuit is

symmetrical, which dictates that vO = 0 V. Thus both QN and QP are

operating with |VDG| = 0 and, hence, in saturation. The drain currents

can be found from

211 (2.5 1)

2

1.125 mA

DP DNI I


2015/2/23 Chih-Wen Lu 96

Next, we consider the circuit with vI = +2.5 V. Transistor QP will have

a VGS of zero and thus will be cut off, reducing the circuit to that shown

here. We note that vO will be negative, and thus vGD will be greater than

Vt, causing QN to operate in the triode region. For simplicity we shall

assume that vDS is small and thus use

From the circuit diagram shown in Fig. 4.25(c),

we can also write

( / )( )

1[2.5 ( 2.5) 1][ ( 2.5)]

DN n n n GS t DS

O

I k W L V V V

v

0(mA)

10 (k )

ODN

vI

W


2015/2/23 Chih-Wen Lu 97

These two equations can be solved simultaneously to yield

Note that VDS = -2.44 – (-2.5) = 0.06 V. Which is small as assumed.

Finally, the situation for the case vI = -2.5 V will be the exact

complement of the case vI = +2.5 V: Transistor QN will be cut off. Thus

IDN = 0, QP will be operating in the triode region with IDP = 2.44 mA

and vO = +2.44 V.

0.244 mA -2.44 VDN OI v

3.4 The MOSFET as an Amplifier and as a Switch

• In this section we begin our study of the use of MOSFETs in the

design of amplifier circuits. The basis for this important MOSFET

application is that when operated in the saturation region, the

MOSFET acts as a voltage-controlled current source: Change in the

gate-to-source voltage vGS give rise to changes in the drain current

iD. Thus the saturated MOSFET can be used to implement a

transconductance amplifier.

• We will study the total or large-signal operation of a MOSFET

amplifier. We will do this by deriving the voltage transfer

characteristic of a commonly used MOSFET amplifier circuit.

From the voltage transfer characteristic we will be able to clearly

see the region over which the transistor can be biased to operate as

a small-signal amplifier as well as those regions where it can be

operated as a switch.

2015/2/23 Chih-Wen Lu 98

3.4 The MOSFET as an Amplifier and as a Switch (cont’d)

• Large-Signal Operation-The Transfer Characteristic

2015/2/23 Chih-Wen Lu 99

Figure (a) Basic structure of the common-source amplifier. (b) Graphical construction to

determine the transfer characteristic of the amplifier in (a).


2015/2/23 Chih-Wen Lu 100

O DS DD D Dv v V R i


• Graphical Derivation of the Transfer Characteristic

2015/2/23 Chih-Wen Lu 101

1

DS DD D D

DDD DS

D D

v V R i

Vi v

R R

The straight line intersects

the -axis at [since

at 0]

and has a slope of -1/

DS DD

DS DD D

D

v V

v V i

R


2015/2/23 Chih-Wen Lu 102

The graphical construction

can now be used to determine (equal to

) for each given value of ( ).

, , cut off, 0, and

. Operate at point A.

exceed , turn on, inc

O

DS I GS I

GS I I t D

O DS DD

I t D

v

v v v v

v v v V i

v v V

v V i

reases, and

decreases, operate at saturation region,

from A to B.

A particular point :Q. and has

the coordinates and .

O

GS IQ

OQ DSQ DQ

v

V V

V V I


2015/2/23 Chih-Wen Lu 103

Saturation-region operation continues

until decreases to the point that it

is below by volts. ,

enters triode region, point B.

, deeper in to triode region,

output volta

O

IB t DS GS t

I IB

OB IB tV V

v

v V v

V

v V

v V

ge decreases slowly

towards zero.

Point C, I DDv V


2015/2/23 Chih-Wen Lu 104

Figure (Continued) (c) Transfer

characteristic showing operation as an

amplifier biased at point Q.

• When the MOSFET is used as a switch, it is operated at the extreme points of the transfer curve.

• Specifically, the device is turned off by keeping vI < Vt resulting in operation somewhere on segment XA with vO = VDD.

• The switch is turned on by applying a voltage close to VDD, resulting in operation close to point C with vO very small ( at C, vO = VOC ).


• Operation as a linear

Amplifier

2015/2/23 Chih-Wen Lu 105

I IQ

Ov

I v V

dvA

dv


2015/2/23 Chih-Wen Lu 106

Figure Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for

positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the

triode region and might not allow for sufficient negative signal swing.


• Analytical Expressions for the Transfer Characteristic

2015/2/23 Chih-Wen Lu 107

• The Cutoff-Region Segment, XA , vI ≦ Vt, and vO = VDD.

• The Saturation-Region Segment, AQB , vI ≧ Vt, and vO ≧ vI -

Vt . Neglecting channel-length modulation and substituting for

iD from

into

gives

21( ) ( )

2D n ox I t

Wi C v V

Lm

O DD D Dv V R i

21( )

2O DD D n ox I t

Wv V R C V V

Lm


2015/2/23 Chih-Wen Lu 108

The end point of the saturation-region segment

is characteri

( )

2( ) 2

zed by

I IQ

Ov

I v V

v D n ox IQ t

IQ t OV

DD OQ RDv

OV OV

RD DO OQ

OB IB t

dvA

dv

WA R C V V

L

V V V

V V VA

V V

V V V

V V V

m


2015/2/23 Chih-Wen Lu 109

• The Triode-Region Segment, BC, vI ≧ Vt, and vO ≦ vI

- Vt .

2

2

The portion of this segment for wh

1( )

2

1

ich is small is given aproximately by

which reduces to

( )2

( )

O

D n ox I t O O

O DD D D

O DD D n ox I t O O

O DD D n ox I t O

O DD

Wi C v V v v

L

v V R i

Wv V R C v V v v

L

Wv V R C v V v

v

v

L

V

m

m

m

1 ( )D n ox I t

WR C v V

Lm


2015/2/23 Chih-Wen Lu 110

1 ( )DS n ox I t

DSO DD

DS D

DS D

DSO DD

D

Wr C v V

L

rv V

r R

r R

rv V

R

m


• Example

• To make the above analysis more

concrete we consider a numerical

example. Specifically, consider the CS

circuit for the case k /

n ( W / L ) = 1 mA/V2

, Vt = 1 V, RD = 18 kW, and VDD = 10 V.

2015/2/23 Chih-Wen Lu 111


• Solution

2015/2/23 Chih-Wen Lu 112

1I IB OB t OBv V V V V

First, we determine the coordinates of important points on the transfer

curve.

(a) Point X:

(b) Point A:

(c) Point B: Substituting

1V, 10 VI Ov v

0 V, 10 VI Ov v

29 10 0

1 V

1 1 2 V

O OB

OB OB

OB

IB

v V

V V

V

V


2015/2/23 Chih-Wen Lu 113

100.061 V

1 18 1 (10 1)OCV

(d) Point C:

Next, we bias the amplifier to operate at an appropriate point on the

saturation-region segment. Since this segment extends from vO = 1 V

to 10 V, we choose to operate at VOQ = 4 V.

10 40.333 mA

18

DD OQ

D

D

V VI

R


2015/2/23 Chih-Wen Lu 114

We can find the required overdrive voltage VOV from

Thus, we must operate the MOSFET at a dc gate-to-source voltage

The voltage-gain of the amplifier at this bias point:

21

2

2 0.3330.816 V

1

D n OV

OV

WI k V

L

V

18 1 (1.816 1)

14.7 V/V

VA

1.816 VGSQ t OVV V V


2015/2/23 Chih-Wen Lu 115

212

212

212

At 1.741 V, 1 (1.741-1) 0.275 mA

At 1.816 V, 1 (1.816-1) 0.333 mA

At 1.891 V, 1 (1.891-1) 0.397 mA

At 1.741 V, 0.275 mA, and 10 0.275 18 5.05 V

At 1.891 V, 0.

GS D

GS D

GS D

GS D O

GS D

v i

v i

v i

v i v

v i

397 mA, and 10 0.397 18 2.85 V Ov


2015/2/23 Chih-Wen Lu 116


• A Final Remark on Biasing

• In the above example, the MOSFET was assumed to be biased at a

constant vGS of 1.816 V. Although it is possible to generate a

constant bias voltage using an appropriate voltage-divider network

across the power supply VDD or across another reference voltage

that may be available in the system, fixing the value of vGS is not a

good biasing technique.

2015/2/23 Chih-Wen Lu 117

3.5 Biasing in MOS Amplifier Circuit

• As mentioned in the previous section, an essential step in the

design of a MOSFET amplifier circuit is the establishment of an

appropriate dc operating point for the transistor. This is the step

known as biasing or bias design. An appropriate dc operating point

or bias point is characterized by a stable and predictable dc drain

current ID and by a dc drain-to-source voltage VDS that ensures

operation in the saturation region for all expected input-signal

levels.

2015/2/23 Chih-Wen Lu 118

3.5 Biasing in MOS Amplifier Circuit (cont’d)

• Biasing by Fixing VGS

2015/2/23 Chih-Wen Lu 119

21( )

2D n ox GS t

WI C V V

Lm

Figure The use of

fixed bias (constant

VGS) can result in a

large variability in the

value of ID. Devices 1

and 2 represent

extremes among units

of the same type.


• Biasing by Fixing VG and Connecting a Resistance in the Source

2015/2/23 Chih-Wen Lu 120

Figure Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic

arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply;

G GS S DV V R I


2015/2/23 Chih-Wen Lu 121

Figure (c) practical implementation using a single supply; (d) coupling of a signal source to

the gate using a capacitor CC1; (e) practical implementation using two supplies.


• Example

• It is required to design the circuit to establish a

dc drain current ID = 0.5 mA. The MOSFET is

specified to have Vt = 1 V and k /

n W / L = 1 mA/V2 .

For simplicity, neglect the channel-length modulation

effect (i.e., assume = 0). Use a power-supply VDD = 15

V. Calculate the percentage change in the value of ID

obtained when the MOSFET is replaced with another unit

having the same k /

n W / L but Vt = 1.5 V.

2015/2/23 Chih-Wen Lu 122


• Solution

2015/2/23 Chih-Wen Lu 123

212

212

For 15 V, this choice makes

10 V and 5 V.

15 1010 k

0.5

510 k

0.5

( / )

0.5 1

1 V

1 1 2 V

5 2 7 V

DD

D S

DD DD

D

SD

S

D n OV

OV

OV

GS t OV

G S GS

V

V V

V VR

I

VR

R

I k W L V

V

V

V V V

V V V

W

W

Figure 4.31 Circuit for Example 4.9.


2015/2/23 Chih-Wen Lu 124

1 2We may select 8 M and 7 M .

The dc voltage at the drain (+10 V) allows for

a positive signal swing of +5 V (up to ) and

a negative signal swing of -4 V [down to ( )]

If the NMOS transistor

G G

DD

G t

R R

V

V V

W W

212

is replaced with another

having 1.5 V:

1 ( 1.5)

7 10

0.455 mA

0.455 0.5 0.045 mA

0.045which is 100 9% change.

0.5

t

D GS

G GS D S

GS D

D

D

V

I V

V V I R

V I

I

I


• Biasing Using a Drain-to-Gate Feedback Resistor

2015/2/23 Chih-Wen Lu 125

GS DS DD D D

DD GS D D

V V V R I

V V R I

Figure Biasing the MOSFET using a large

drain-to-gate feedback resistance, RG.


• Biasing Using a Constant-Current Source

2015/2/23 Chih-Wen Lu 126

Figure (a) Biasing the MOSFET using a constant-

current source I. (b) Implementation of the constant-

current source I using a current mirror.

2

1

1

1

1

The heart of the circuit is transistor ,

whose drain is shorted to its gate and

thus is operating in the saturation

region, such that

assume 0. The drain current of

is

1( )

2

sup

D n GS t

WI k V V

Q

Q

L

REF

plied by through resistor .

Since the gate current are zero,

DD

D

GS

D

SSD

V V VI

V R

IR


2015/2/23 Chih-Wen Lu 127

2

2

2

Now consider transistor :

It has the same as :thus if we

assume that it is operating in

saturation, its drain current,

which is the desired current

of the current source, will b

1(

2

e

D n

WV

Q

I I kL

2

2R EF

1

)

( / )

( / )

GS tV

W LI I

W L


• A Final remark

• The bias circuit studied in this section are intended for discrete-

circuit application. The only exception is the current mirror circuit

which, as mentioned above, is extensively used in IC design.

2015/2/23 Chih-Wen Lu 128

3.6 Small-Signal Operation and Models

• In our study of the large-signal operation of the common-source

MOSFET amplifier in Section 3.4 we learned that linear

amplification can be obtained by biasing the MOSFET to operate

in the saturation region and by keeping the input signal small.

Having studied methods for biasing the MOS transistor in the

previous section, we now turn our attention to exploring small-

signal operation in some detail.

2015/2/23 Chih-Wen Lu 129

3.6 Small-Signal Operation and Models (cont’d)

• Here the MOS transistor is biased by applying a dc voltage VGS, a

clearly impractical arrangement but one that is simple and useful

for our purposes. The input signal to be amplified, vgs, is shown

superimposed on the dc bias voltage VGS. The output voltage is

taken at the drain.

2015/2/23 Chih-Wen Lu 130

Figure Conceptual circuit

utilized to study the operation

of the MOSFET as a small-

signal amplifier.


• The DC Bias Point

2015/2/23 Chih-Wen Lu 131

2

Set the to zero, thus

0, or simply (since is grounded), will be

To ensure saturation-region operation, we

1(

must

)2

have

D n GS t

D DD D D

D G t

gs

DS D

S

WI k V V

L

V V R I

V V V

v

V V S


• The Signal Current in the Drain Terminal

2015/2/23 Chih-Wen Lu 132

2

2 2

is applied, the total instantaneous gate-to-source voltage:

total instantaneous drain current:

To reduce th

1( )

2

1 1( )

e nonlinear

( )2 2

GS GS gs

D n GS gs t

n GS t n GS t gs n g

s

s

g

v V v

Wi k V v V

L

W W Wk V V k V V v k v

L L L

v

2

distortion, the input signal should be

kept small so that

or, equivalently,

1( )

2

2( ) 2

n gs n GS t gs

gs GS t gs OV

W Wk v k V V v

L L

v V V v V


2015/2/23 Chih-Wen Lu 133

If the small-signal condition is satisfied,

where

in terms of the overdrive voltage ,

( )

( )

D D d

d n GS t gs

dm n GS t

gs

O

OV

m n V

i I i

Wi k V V v

L

i Wg k V V

v L

Wg k V

L

V


2015/2/23 Chih-Wen Lu 134

GS GS

Dm

GS v V

ig

v

Figure Small-signal operation of the

enhancement MOSFET amplifier.


• The Voltage Gain

2015/2/23 Chih-Wen Lu 135

( )

D DD D D

D DD D D D

D D D d

d d D m gs D

dv m D

gs

v V R i

v V R I i

v V R i

v i R g v R

vA g R

v


2015/2/23 Chih-Wen Lu 136

dv m D

gs

vA g R

v


• Separating the DC Analysis and the Signal Analysis

• From the preceding analysis, we see that under the small-signal

approximation, signal quantities are superimposed on dc quantities.

• It follows that the analysis and design can be greatly simplified by

separating dc or bias calculations from small-signal calculation.

2015/2/23 Chih-Wen Lu 137


• Small-Signal Equivalent-Circuit Models

2015/2/23 Chih-Wen Lu 138

A

o

D

Vr

I

Figure Small-signal models for the MOSFET: (a) neglecting the dependence

of iD on vDS in saturation (the channel-length modulation effect); and (b)

including the effect of channel-length modulation, modeled by output

resistance ro = |VA| /ID.

21( )

2

A do D n OV v m D o

D gs

V vWr I k V A g R r

I L v


• The Transconductance gm

2015/2/23 Chih-Wen Lu 139

substitute ( ) by 2 /( ( / ))

This expression shows that

1. For a given MOSFET, is proportional to the square

root of the dc bias current.

2.

( / )( ) ( / )

2 /

At a

m n GS t n

GS t n

D

D

m

OV

m n

g k W L V V k W

V V I k

L V

g k W L I

W L

g

2

given bias current, is proportional to / .

Another useful expression for , substitute ( / )

b (

2

2 /

2

y )

m

m n

D GS t

D Dm

GS t OV

I

g W L

g k W L

I V V

Ig

V V V


• Example: We wish to analyze this amplifier circuit to determine its

small-signal voltage gain, its input resistance, and the largest

allowable input signal. The transistor has Vt = 1.5, k /

n ( W / L ) =

0.25 mA/V2 , and VA = 50 V. Assume the coupling capacitors to be

sufficiently large so as to act as short circuits at the signal

frequencies of interest.

2015/2/23 Chih-Wen Lu 140


• Solution

2015/2/23 Chih-Wen Lu 141

212

2

0.25( 1.5)

0.125( 1.5)

15 15 10

1.06 mA and 4.4 V

( )

0.25(4.4 1.5) 0.725 mA/V

5047 k

1.06

D GS

GS D

D D

D D D D

D D

m n GS t

Ao

D

I V

V V

I V

V R I I

I V

Wg k V V

L

Vr

I

W


2015/2/23 Chih-Wen Lu 142

( )

( )

0.725(10 10 47) 3.3 V/V

( ) /

1

4.3[1 ( 3.3)]

10Thus, 2.33 M

4.3 4.3

o m gs D L o

gs i

ov m D L o

i

i i o G

i o

G i

i i

G G

i Gin

i

v g v R R r

v v

vA g R R r

v

i v v R

v v

R v

v v

R R

v RR

i

W


2015/2/23 Chih-Wen Lu 143

ˆThe largest allowable input signal is determined by the need

to keep the MOSFET in saturation at all times; that is

Enforcing this condition, with equality, at the point is maximum

and

i

DS GS t

GS

v

v v V

v

min max

min

is correspondingly minimum, we write

which results in

ˆ 0.34 V

In that in the negative direction, this input signal amplitude results in

4.4 0.34 4.06 V

the maximum allowable

DS

DS GS t

i

GS

v

v v V

v

v

input signal peak is 0.34 V.


• The T Equivalent-Circuit Model

2015/2/23 Chih-Wen Lu 144

Figure Development of the T

equivalent-circuit model for

the MOSFET. For simplicity,

ro has been omitted but can be

added between D and S in the

T model of (d).


2015/2/23 Chih-Wen Lu 145

Figure (a) The T model of the MOSFET augmented with the drain-to-source

resistance ro. (b) An alternative representation of the T model.


• Modeling the Body Effect

• The signal vbs gives rise to a drain-current component, which we

shall write as gmbvbs, where gmb is the body transconductance,

defined as

2015/2/23 Chih-Wen Lu 146

constantconstant

GS

DS

Dmb

BSv

v

ig

v


2015/2/23 Chih-Wen Lu 147

where

2 2

mb m

t

SB f SB

g g

V

V V

g

f

Figure Small-signal equivalent-circuit

model of a MOSFET in which the source

is not connected to the body.

3.7 Single-Stage MOS Amplifiers

• Having studied MOS amplifier biasing and the small-signal

operation and models of the MOSFET amplifier , we are now ready

to consider the various configuration utilized in the design of MOS

amplifiers.

• Discrete MOS amplifiers are easier to understand than their IC

counterparts for two main reasons: The separation between dc and

signal quantities is more obvious in discrete circuits, and discrete

circuits utilize resistors as amplifier load.

2015/2/23 Chih-Wen Lu 148

3.7 Single-Stage MOS Amplifiers (cont’d)

• The Basic Structure

2015/2/23 Chih-Wen Lu 149

Figure Basic structure of the circuit used

to realize single-stage discrete-circuit

MOS amplifier configurations.


• The Common-Source (CS) Amplifier

2015/2/23 Chih-Wen Lu 150


2015/2/23 Chih-Wen Lu 151

sig sig

in gs

insig

in sig sig

0

( )

g G i

G i

Gi o m gs o D L

G

i R R v v

R R v v

RRv v v g v r R R

R R R R

Figure (b) Equivalent circuit of the

amplifier for small-signal analysis.


2015/2/23 Chih-Wen Lu 152

in

in sig sig

out

( )

( )

( )

v m o D L

vo m o D

Gv v m o D L

G

o D

A g r R R

A g r R

RRG A g r R R

R R R R

R r R


2015/2/23 Chih-Wen Lu 153

Figure (c) Small-signal analysis performed directly on the amplifier circuit with the

MOSFET model implicitly utilized.


• The Common-Source Amplifier with a Source Resistance

2015/2/23 Chih-Wen Lu 154

Figure (a) Common-source amplifier with a

resistance RS in the source lead.


2015/2/23 Chih-Wen Lu 155

Figure (b) Small-signal equivalent

circuit with ro neglected.


2015/2/23 Chih-Wen Lu 156

in

sig

sigsig

1

1 1

i G

G m ii gs i

G m s

m

R R R

R g vv v v v

R R g RR

g


2015/2/23 Chih-Wen Lu 157

sig

( )

1 1 1

( )

( )

1 1

(

i m i m D Ld v

m s m sS

m

o d D L

m D L m Dvo

m s m s

G m Dv

G

v g v g R Ri i A

g R g RR

g

v i R R

g R R g RA

g R g R

R g R RG

R R

)

1

L

m sg R


• The Common-Gate (CG) Amplifier

2015/2/23 Chih-Wen Lu 158


2015/2/23 Chih-Wen Lu 159

Figure (b) A small-signal equivalent circuit

of the amplifier in (a).


2015/2/23 Chih-Wen Lu 160

in

insig

in sig

sig sig

sigsig

1

1

1

1 1

m

i

mi

m

m

Rg

Rv v

R R

gv v v

g RR

g


2015/2/23 Chih-Wen Lu 161

insig

in sig sigsig

in sig

1

1

1 1

( )

1/ 1

m vv v v

m m

m

i i m D Li m i v

m m

d i m i

g ARR G A A

g R R g RR

g

v v g R Ri g v G

R g g R

i i i g v

out

( ) ( )

( )

o d d D L m D L i o D

v m D L

vo m D

v v i R R g R R v R R R

A g R R

A g R


2015/2/23 Chih-Wen Lu 162

Figure (c) The common-gate amplifier

fed with a current-signal input.

sig sig

sig sig

sig insig

sig

sig

1

Normally, 1/

i

m

m

i

R Ri i i

R RR

g

R g

i i


• The Common-Drain or Source-Follower Amplifier

2015/2/23 Chih-Wen Lu 163

Figure (a) A common-drain or source-follower amplifier.


2015/2/23 Chih-Wen Lu 164

Figure (b) Small-signal equivalent-circuit model.

in

insig sig

in sig sig

sig

G

Gi

G

i

R R

RRv v v

R R R R

v v


2015/2/23 Chih-Wen Lu 165

Normally 1/ , 1. Also, in many

discrete-circuit

1( )

1(

application, ,

)

1

1

o m v

L oo i

L o

m

L ov

L o

m

ovo

o

m

Lv

L

m

o

o L

r g A

R rv v

R rg

R rA

R rg

rA

rg

RA

g

r R

R


2015/2/23 Chih-Wen Lu 166

sig

sig

which approaches unity

1( )

,

r

/ , .

o

1

f

G L ov

GL o

m

G o m o L

R R rG

R RR r

g

R R r g and r R


2015/2/23 Chih-Wen Lu 167

Figure (c) Small-signal analysis performed directly on the circuit.


2015/2/23 Chih-Wen Lu 168

Figure (d) Circuit for determining the output

resistance Rout of the source follower.

ou

ut

u

t

o

o t

1

Normally, 1/ , reducing to

1

m

m

o

o

m

r g

R rg

Rg

R

3.8 The MOSFET Internal Capacitances and High-Frequency Model

• There are basically two types of internal capacitances in the MOSFET:

1. The gate capacitive effect: The gate electrode (polysilicon) forms a parallel-plate capacitor with the channel, with the oxide layer serving as the capacitor dielectric.

2. The source-body and drain-body depletion-layer capacitances: These are the capacitances of the reverse-biased pn junction formed by the n+ source region (also called the source diffusion) and the p-type substrate and by the n+ drain region (the drain diffusion) and the substrate.

2015/2/23 Chih-Wen Lu 169

3.8 The MOSFET Internal Capacitances and High-Frequency Model (cont’d)

• The Gate Capacitive Effect

2015/2/23 Chih-Wen Lu 170


• The Junction Capacitances

2015/2/23 Chih-Wen Lu 171

0

0

For the source diffusion, we have the source-body capacitance:

For the drain diffusion, we have the drain-body capacitanc

1

e:

sbsb

SB

CC

V

V

0

0

1

dbdb

DB

CC

V

V


• The High-Frequency MOSFET Model

2015/2/23 Chih-Wen Lu 172

Figure (a) High-frequency equivalent

circuit model for the MOSFET.

(b) The equivalent circuit for the case in which

the source is connected to the substrate (body).


2015/2/23 Chih-Wen Lu 173

Figure (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis).


• The MOSFET Unity-Gain Frequency (fT)

2015/2/23 Chih-Wen Lu 174

Figure 4.48 Determining the short-circuit current gain Io /Ii.

( )

/( )

/ ( ) 2 ( )

o mo m gs gd gs

i gs gd

o m gs T m gs gd

mgs i gs gd T

gs gd

I gI g V sC V

I s C C

I g V g C C

gV I s C C f

C C

3.9 The CMOS Digital Logic Inverter

• The basic CMOS inverter utilizes two matched enhancement-type

MOSFETs: one, QN, with an n channel and the other, QP, with a p

channel. The body of each device is connected to its source and

thus no body effect arises.

2015/2/23 Chih-Wen Lu 175

3.9 The CMOS Digital Logic Inverter (cont’d)

• Circuit Operation

2015/2/23 Chih-Wen Lu 176

Figure Operation of the CMOS

inverter when vI is high: (a) circuit

with vI = VDD (logic-1 level, or VOH);

(b) graphical construction to determine

the operating point; (c) equivalent

circuit.


2015/2/23 Chih-Wen Lu 177

provides a low-resistance path between the

output terminal and ground, with the resistance

obtained

using Eq. (4.13) as

Fig 5.54(c)

1 (

shows the eq va

)

ui

DSN n DD tn

n

N

Wr k V V

L

Q

lent circuit of the

inverter when the input is high. This circuit

confirms that 0 V and that the power

dissipation in the inverter is zero.

O OLv V


2015/2/23 Chih-Wen Lu 178

Figure Operation of the CMOS inverter when vI is low:

(a) circuit with vI = 0 V (logic-0 level, or VOL); (b)

graphical construction to determine the operating point;

(c) equivalent circuit.

2015/2/23 Chih-Wen Lu 179

Fig. 4.55(c) shows the equivalent circuit of the

inverter when the input is low. Here we see that

provides a low-resistance path between the

output terminal and the dc supply , with the

resistance g

P

DD

Q

V

iven by

The equivalent circuit confirms that in this case

and that the power dissipation in

th

e inverter i

1 ( )

s zero.

O O

DSP p DD tp

p

H DD

Wr k V V

L

v V V


• The Voltage Transfer Characteristic

2015/2/23 Chih-Wen Lu 180

Figure The voltage transfer characteristic of the CMOS inverter.


2015/2/23 Chih-Wen Lu 181

' 2

2'

2'

1 for

2

1 for

2

1

2

For ,

For

,

DN n I tn O O O I tn

n

DN n I tn O I tn

n

DP p DD I tp D

P

D O DD O

N

p

Q

Wi k v V v v v v V

L

Wi k v V v v V

L

Wi k V v V V v V v

L

Q

2

'

for

1

2

for

O I tp

DP p DD I tp

p

O I tp

v v V

Wi k V v V

L

v v V


• The CMOS inverter is usually designed to have

2015/2/23 Chih-Wen Lu 182

' '

tn tp

n p

n p

p n

n p

V V

W Wk k

L L

W

W

m

m


2015/2/23 Chih-Wen Lu 183

Determine VIH

QN: triode region

QP: saturation region

' 2

2'

22

1

2

1

2

1 1

2 2

DN n I tn O O

n

DP p DD I tp

p

DN DP

I t O O DD I t

Wi k v V v v

L

Wi k V v V

L

i i

v V v v V v V


2015/2/23 Chih-Wen Lu 184

O OI tn O O

I I

DD I t

dv dvv V v v

dv dv

V v V

221 1

2 2I t O O DD I tv V v v V v V

2

15 2

8

DDO IH

IH DD t

Vv V

V V V

Differentiating both sides relative to vI

Substituting vI = VIH

and dvO/d vI = -1


2015/2/23 Chih-Wen Lu 185

VIL can be determined in a manner similar to that used to find VIH.

Alternatively, we can use the

symmetry relationship

2 2

13 2

8

DD DDIH IL

IL DD t

V VV V

V V V


2015/2/23 Chih-Wen Lu 186

The noise margins

15 2

8

13 2

8

13 2 0

8

13 2

8

H OH IH

DD DD t

DD t

L IL OL

DD t

DD t

NM V V

V V V

V V

NM V V

V V

V V


• Dynamic Operation

2015/2/23 Chih-Wen Lu 187

Dynamic Operation

Figure Dynamic

operation of a

capacitively loaded

CMOS inverter: (a)

circuit; (b) input and

output waveforms; (c)

trajectory of the

operating point as the

input goes high and C

discharges through

QN; (d) equivalent

circuit during the

capacitor discharge.


2015/2/23 Chih-Wen Lu 188

tPHL = tPHL1 + tPHL2

tPHL1:

vO = VDD ~ (VDD – Vt)

Qn: saturation region

tPHL2 :

vO = (VDD – Vt) ~ VDD/2)

Qn: triode region

2'1

constant2

DN n DD t

n

Wi k V V

L

' 21

2DN n DD t O O

n

Wi k V V v v

L


2015/2/23 Chih-Wen Lu 189

Calculate tPHL1

1

1

0

2'

0

2'

1

2'

1

12' '

1

1 1

2

1 1

2

1 1

2

1 1

2 2

PHL

PHL

t t

O DN DD

t

t t

n DD t DD

nt

n DD t PHL DD

n

DD t n DD t PHL DD

n

DD DD t tPHL

n DD t n

n

v i dt VC

Wk V V dt V

C L

Wk V V t V

C L

WV V k V V t V

C L

C V V V CVt

W Wk V V k

L L

2

DD t

n

V V


2015/2/23 Chih-Wen Lu 190

Calculate tPHL2

' 2

'

2

1

2

1

12 2

2

ODN

DN O

n DD t O O O

n

n n O

DD tO O

DD t

dvi C

dt

i dt Cdv

Wk V V v v dt Cdv

L

k W L dvdt

C V Vv v

V V


2015/2/23 Chih-Wen Lu 191

2

'

2

'2

02

'2

22

2

2 '

1

12 2

2

1

12 2

2

1

12 2

2

1ln 1

ln

PHL O DD

O DD t

O DD

O DD t

n n O

DD tO O

DD t

t t v Vn n O

t v V VDD t

O O

DD t

v Vn n OPHL

v V VDD t

O O

DD t

PHL

n DD tn

k W L dvdt

C V Vv v

V V

k W L dvdt

C V Vv v

V V

k W L dvt

C V Vv v

V V

dx

ax x ax

Ct

k W L V V

3 4DD t

DD

V V

V


2015/2/23 Chih-Wen Lu 192

1 2

'

3 42 1ln

2

PHL PHL PHL

t DD t

n DD t DD t DDn

t t t

V V VC

k W L V V V V V

'

1.6PHL

n DDn

Ct

k W L V

For the usual case of Vt = 0.2 VDD, this equation reduces to


• Current Flow and Power Dissipation

2015/2/23 Chih-Wen Lu 193

FigureThe current in the CMOS inverter versus the input

voltage.


2015/2/23 Chih-Wen Lu 194

At t = 0-, vO = VDD

Energy stored on the capacitor is 0.5CVDD2

At t = 0, vI goes high to VDD, the capacitor voltage is reduced to zero

During the discharge interval, energy of 0.5CVDD2 is removed from C

and dissipated in Qn.


2015/2/23 Chih-Wen Lu 195

When vI goes low to zero, QN turns off, and QP conducts and

charges the capacitor.

The energy drawn from the power supplied to the capacitor:

Thus the energy drawn from the supply during the charging interval

is CVDD2.

DD

DDDDDD

CVQ

QVidtVidtV

capacitor; the tosupplied charge theis Q where


2015/2/23 Chih-Wen Lu 196

At the end of the charging interval, the capacitor voltage will be

VDD, and thus the energy stored in it will be 0.5CVDD2 .

It follows that during the charging interval, half of the energy

drawn from the supply, 0.5CVDD2 , is dissipated in QP.

In every cycle, 0.5CVDD2 of energy is dissipated in QN and

0.5CVDD2 dissipated in QP, for a total energy dissipation in the

inverter of CVDD2 .


2015/2/23 Chih-Wen Lu 197

If the inverter is switched at the rate of f cycles per second, the

dynamic power dissipation in it will be

A figure of merit or a quality measure of the particular circuit

technology is the delay-power product (DP),

2

2

DDD

DD

CVP

T

fCV

D PDP P t

Documents

MOSFETs-2015-02-23