Mosfet n an p type

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ENEE 313, Fall 08Supplement IV

An Example Problem on the NMOSand A PMOS IntroductionZeynep Dilli, Dec. 2008

This is a supplement presenting an example question on MOSFET operation and reviews the MOSFETconcepts during the solution. Later three sections summarize, once again, the band-energy diagrams of anNMOS under di ff erent bias conditions, then present the structure of a PMOS and give summaries of itsband-energy diagrams under di ff erent bias conditions and its IV curve.

1 Device Structure

An n-channel silicon MOSFET (NMOS) has the following construction: The p-type substrate doping isN A = 5 1016 1/cm 3 . The n-type polysilicon gate is doped at N D = 10 19 1/cm 3 . The gate length is0.5 m. The oxide thickness tox =20 nm. The device width is 20 m. The source and drain are dopeddegenerately (very highly) at N D = 10 20 cm. The source and drain regions are each 1 m wide and 0.25m deep. The p-type bulk (substrate) is 100 m deep.

Relevant constants: Silicon dioxide and silicon permittivities are ox = 3 .9 8.9 10 14 F/cm andSi = 11 .7 8.9 10 14 F/cm. ni = 1 .45 1010 1/cm 3 . n = 500 cm 2 /V.sec. 1 nm=0.001 m. Assume

room temperature, so that kT/q =0.026 V.

2 Device Analysis

Question: Sketch the two-dimensional cross-section of this device. The thickness/depth dimension does not have to be to scale.

Answer:Question: Draw the band diagram with no bias applied to the substrate. Then calculate

the threshold voltage V thr under that condition.The gate is not metal, but polysilicon, so instead of the work function of a metal M we have to use the

work function of the polysilicon gate while aligning the Fermi levels of the polysilicon and silicon along withthe vacuum energy level. Lets denote the work function of the polysilicon gate with poly and that of thesilicon substrate with Si . Polysilicon and silicon both have the same electron a ffinity, Si = E 0 E C,Siwhere E 0 is the vacuum energy level, and the same bandgap, E g,Si . So when separate, the band energydiagrams of our gate and body materials will look as in Figure 2:

As can be seen from the gure, when the materials are put together, and at equilibrium the Fermilevels align, the work function di ff erence Si poly will cause band-bending. Here is the situation shownin Figure 3, with the oxide layer in the polysilicon/oxide/silicon system inserted:

To nd the threshold voltage, we need to use the expression

V thr = V ox + 2 |b| + V F B ; (1)

where V ox is the potential drop across the oxide (which charges up the depletion region capacitance), b isthe body potential (more about it later) and thus 2 |b| is the potential needed to draw enough electrons

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Figure 1: The NMOS device described in this supplement.

Figure 2: Band energy diagrams for the n-type polysilicon (metal) gate and the p-type silicon body.

Figure 3: Band diagram of the MOS system formed by the polysilicon and silicon as described in the textand the oxide layer of thickness tox in between.

to the surface of this p-type substrate to invert it, and V F B is the calibration factor of the at-bandvoltage. Well start by calculating V F B .

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As can be tracked from Figure 3, the total band-bending is | Si poly | = ( Si + E g / 2+( E i,Si E F )) ( Si + E g / 2 (E F E i,poly ) = ( E i,Si E F ) + ( E F E i,poly ). Or, if we write the body potential of thesilicon substrate far from the interface as |b| = |(E i,Si E F )/q | and the potential of the n-type polysilicon

gate as |n | = |(E i,Si

E F )/q | , we can write the magnitude of the total band-bending in units of energyas q (b + n ). So the magnitude of V F B , the potential that should be applied between the metal (herepolysilicon) gate and the silicon substrate to cancel the band-bending, is b + n .

By denition, the at-band potential is measured as applied between the gate and the substrate (body):V F B = V G V B , where V B is any potential applied to the body. Here, looking at the band energy diagram,obviously we need to raise the gate side to create the at-band condition. Therefore, the potentialapplied between the gate and the substrate needs to be negative (i.e. the gate put to a more negativepotential than the substrate). Then, for this problem

V F B = (b + n ) = (kT q

ln (N A,body

n i) +

kT q

ln (N D,poly

n i))

=

0.026(ln ( 5 1019

1.45 1010 ) + ln ( 5 1019

1.45 1010 )) =

0.026

(15.05 + 20.35) =

0.94 V.When this potential is applied between the gate and the body, the material reaches at-band condition,

as in Figure 4:

Figure 4: The MOS system described here at at band condition. Note that the Fermi level in thepolysilicon (metal) gate is higher than that in the silicon body now. To achieve this, a negative potentialneeds to be applied between the gate and the body.

As for the other terms in the threshold voltage expression, V ox , the potential drop across the oxide, isgiven by

V ox = tox

oxq 2qN A,Si 2|b| Si

= 20 10 7 cm3.45 10 13 F/ cmp 4 1.6 10 19 5 1016 0.3914 1.035 10 12 = 0 .66 V.

Once again, this is the potential required, starting from the atband condition, to create a depletionregion under the gate oxide where the holes have been pushed away, so that although the substratematerial is p-type, there are not many holes near the surface any more. Then there is the extra potentialrequired to draw enough electrons to the surface and create the inversion layer, which is 2 |b| = 2 V thermal ln(N A,substrate /n i ) = 2 0.026 15.05 = 2 0.39 = 0.78 V at the onset of strong inversion bydenition. Then the threshold voltage for this n-channel MOSFET is

V thr = V ox + 2 |b| + V F B = 0 .66 + 0 .78 0.92 = 0 .52 V. (2)

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Note that the initial doping levels of the polysilicon gate and silicon body happened to set a situationvery close to surface depletion already (as could be seen in Figure 2). So in this case, the atband voltageactually works to bring the threshold voltage down. At di ff erent doping levels, the situation would be

diff

erent.The band diagram at the onset of strong inversion is as in Figure 5.

Figure 5: The described MOS system at strong inversion. The gate is at a higher potential than thesubstrate, as shown by the lower Fermi level at the gate. At this potential level, V thr , the magnitude of thesurface potential |s | is equal to the magnitude of the body potential |b; in other words, the total bandbending in the silicon is 2|b| , which is the origin of that term in the threshold voltage expression Eqn. 1.

Question: What happens if the body is not grounded initially, but held at a voltage V B ? The eff ect of a body voltage is to change the depletion region growth as a potential is applied to the

gate. Therefore, it changes the V ox component of the threshold voltage as follows:

V ox = tox

oxq 2qN A,Si 2|(b V B )| Si (3)

So for instance, if the body voltage is set at -1 V for this transistor, the new threshold voltage wouldbe

V thr = V ox + 2 |b| + V F B

= 20 10 7 cm3.45 10 13 F/ cmp 4 1.6 10 19 5 1016 (0.3914 ( 1)) 1.035 10 12 + 0 .78 0.92

= 1 .24 + 0 .78 0.92 = 1 .1 V

In normal digital operation, we typically ground the p-type body of the NMOS transistors and connectthe n-type body of PMOS transistors to the highest potential in the circuit. But during integrated circuitoperation, stray currents in the common substrate shared by all transistors can create di ff ering potentiallevels for diff erent transistors substrates, and as shown above, this can cause transistors that should havebeen identical to have di ff erent threshold voltages and thus di ff erent operating characteristics. This body e ff ect (or substrate bias e ff ect ) is then unwanted.

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Question: What is the operation region of this MOSFET for this MOSFET at the follow-ing bias conditions, and what is the drain current? Assume the body potential is 0.

1. V DS

=0.5 V, V GS

=2.0 V

2. V DS =3.0 V, V GS =2.0 V

3. V DS =0.5 V, V GS =3.0 V

4. V DS =3.0 V, V GS =3.0 V

5. V DS =0.5 V, V GS =4.0 V

6. V DS =3.0 V, V GS =4.0 V

First, for all these cases V GS > V thr , so the transistor is not in cut-o ff : Its either in linear (triode) regionor saturation region of operation. To see which, we compare the drain-source voltage V DS to V GS V thr :How much the gate potential is exceeding the threshold voltage. As the body potential is set to be zero,we will use the rst threshold voltage we calculated:

In cases 1. and 2.: V GS V thr = 2 0.52 = 1.48 V. Then for case 1, V DS = 0 .5 V < V GS V thr , andthe transistor is in the linear region. Then the drain-source current is given by

I DS,lin = n C 0

oxW L

[(V GS V thr )V DS V 2DS

2 ] (4)

Here, C 0ox is the oxide capacitance of this transistor per unit area:

C 0ox = oxtox

(5)

Then for our particular transistor, with the given width ( W = 1 m) and length ( L = 0 .5 m) in thedevice description, the drain-source current in the linear region with V GS = 2 .0 V and V DS = 0 .5 V will be

I DS = 5003.54 10 13

20 10 7200.5

[(2 0.52)0.5 0.52

2 ] = 2.1 10 3 A

For case 2, V DS = 3 .0 V > V GS V thr , so the transistor is in the saturation region. Then, ignoringchannel-length modulation, the drain-source current is given by

I DS,sat = n C 0

oxW 2L

(V GS V thr )2 (6)

and for our particular transistor, the drain-source current in the saturation region with V GS = 2 .0 Vand V DS = 0 .5 V will be

I DS = 5003.54 10 13

20 10 720

2 0.5(2 0.52)2 = 3 .8 10 3 A.

Similarly, in case 3 the transistor is in linear region, case 4, saturation region, case 5, linear region. Incase 6, note that the transistor is still in linear region: V DS = 3 .0 V < V GS V thr = 4 .0 0.52 V.

The IV curves for this transistor for the three gate biases are given in Figure 6.

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Figure 6: IV curves for this NMOS.

Question: If the transistor has a channel-length modulation parameter = 0 .01 V 1 , what does this change in the IV curves?

A non-zero channel-length modulation parameter changes the saturation region current:

I DS,sat = n C 0

oxW 2L

(V GS V thr )2 (1 + V DS ) (7)

This is the result of the e ff ective channel length actually changing with V DS . The eff ect on the IV curveat saturation is shown in Figure 7 for V GS = 2 V.

Question: What about the cut-o ff region of operation? The transistor is in cut-o ff when V GS < V thr ; in this case, when gate-to-source bias is lower than 0.52

V. In that case, we call the transistor to be in the sub-threshold regime. Remember that the thresholdpoint is dened at the onset of strong inversion, that is, the surface potential s is equal in magnitude tothe body potential b. But the intrinsic Fermi level at the surface rises above the Fermi level at the surfaceat lower applied gate-to-source potentials than that. The MOSFET is then in weak inversion, with some electrons having been drawn to the surface to form a lightly-populated channel. There is still some (small)current owing.

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Figure 7: IV curves for this NMOS with channel-length modulation considered.

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3 NMOS Band-Energy Diagrams

Here is a summary table of the situation in an NMOS for no bias, at-band, accumulation, depletion,weak inversion, and onset of strong inversion. As described in the sections above, the no-bias situation isset by the doping levels of the polysilicon gate and the silicon substrate (by the di ff erence of their workfunctions). The rest follows.

Band-energy diagram Condition and notes

No bias.Band-bending is set by Si and poly diference.

Flat-band condition.Requires applying a negative potential togate with respect to the body.

Accumulation condition.The substrate is p-type. Holes are themajority. Accumulation is dened wherethere is an even higher density of major-ity carriers accumulated at the surfacethan there are in the body. The gureshows this is the caseFermi level is farther from intrinsic Fermi level near thesubstrate surface.Requires applying an higher negative po-tential to the gate with respect to the

body than the case for at-band condi-tion.

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Depletion.Requires applying a small positive po-tential to the gate with respect to thebody. The positively-charged holes arebeing pushed away from the surfaceunder the e ff ect of this gate potentiaand a depletion region, with exposednegatively-charged acceptor ions, is be-ing formed under the gate.

Weak inversion.Requires applying a higher positive po-tential to the gate with respect to thebody. When electron-hole pairs are gen-erated in the depletion region near thesurface, now the electric-eld created bythe gate potential is separating them be-fore they can recombine and pulling thenegatively-charged electrons to the sur-face. E i has crossed E F and the surfaclooks like weakly n-type now.

Onset of strong inversion.By denition, this happens at the poten-tial level where E i and E F are separatedas much in the surface as they are deepin the substrate, but in the opposite way.In other words, the surface looks as muchn-type as the deep substrate is p-type.Requires applying a high positive poten-tial to the gate with respect to the body.

4 The PMOS

The p-channel MOSFET, or the PMOS, is the complementary device to the NMOS. All its regions havethe opposite doping to their NMOS counterparts. A sketch of the PMOS is given in Figure 4.

For this device to have a conductive channel between the source and the drain, rst the majorityelectrons of the n-type substrate must be depleted from under the gate, then an inversion layer must beformed by holes being drawn to the surface. This requires applying a negative potential to the gate withrespect to the source to turn on the PMOS. In other words, the PMOS threshold voltage is negative.Another way to think about it is to consider the PMOS threshold voltage positive, but measure the biasefrom the source to the gate instead of the other way around, and write V SG > V thr for the boundary-of-cuto ff condition.

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Figure 8: A p-channel MOSFET, or a PMOS.

Below, we summarize the band-energy diagram of a PMOS under no bias, then demonstrate theaccumulation and strong inversion conditions. Instead of a polysilicon gate, this PMOS is shown to havea metal gate. All the calculations for the polysilicon gate still apply, using the workfunction of the metalinstead of the workfunction of the polysilicon.

Band-energy diagram Condition and notes

No bias.Band-bending is set by Si and metadiff erence.

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Accumulation condition.Requires applying a positive potential togate with respect to the body.

Onset of strong inversion.The substrate is n-type. Electrons arethe majority. At this potential condi-tion, the surface looks as much p-type asthe deep substrate is n-type.Requires applying a high negative poten-tial to the gate with respect to the body.

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Mosfet n an p type