MOSFET Modeling for Low Temperature Analog Circuit Design

1EKV 2.6 Users’ Meeting, EPFL, Lausanne, Nov. 4, 2004

MOSFET Modeling for Low Temperature Analog Circuit Design

Patrick MARTIN

CEA-LETI

Grenoble, France

E-mail: [email protected]


Acknowledgements

• Christian Enz• Pioneering work of F. Théodoloz (EPFL)• Matthias Bucher• Analog designers from LETI : J.L. Martin, F. Rothan , …• Ch. Chancel for experimental support• French Ministry of Defense and CEA


Outline of presentation

• Why CMOS at low temperature ?• Some studied CMOS processes at LT• Compact MOSFET model for analog circuit design• Examples of simulation• Low frequency noise• Transistor matching• Summary and conclusion

Keywords: analog MOSFET, weak & moderate inversion, low temperature, low frequency noise, transistor matching


Why CMOS at LT ? Higher saturation drain current ?

Idsat 77 K / Idsat 293 K vs. drawn length

⇒ Velocity saturation is the main effect limitingshort-channel devices performance at LT

1.0

1.5

2.0

2.5

3.0

3.5

0.1 1 10 100

Ldrawn (µm)

Idsat (77 K

) / Idsat (293 K

)NMOS0.35 µm CMOS

PMOS

0.21 µm CMOS

Vds=Vgs=3.3 or 2.5 V

X 1.2 ∼∼∼∼ 1.3

X 3

X 1.9


Saturation drain current

(((( ))))

(((( ))))VtVgvWCI:EE

VtVgL

WCµ

2

1I:EE

satOXsat,dcrit

2

OXsat,dcrit

−−−−====>>>>

−−−−====<<<<

Ecrit ≈≈≈≈ 5 x 103 V/cm at 300 Kvsat ≈≈≈≈ 107 cm/s at 300 Kvsat 77 K / v sat 300 K ≈≈≈≈ 1.2-1.3


So why CMOS at LT ?

• Design of infrared image sensors [ high performance ,high complexity (1 Mpixel), 77 K – 200 K ]• Simulation of hybrid CMOS analog read-out circuits• No SPICE parameters at LT from CMOS foundries• Validity of BSIM3v3 (Berkeley), EKV 2.6 (EPFL), MM9(Philips) at T <<<< 200 K ?• Importance of weak - moderate inversion regimes• Need to develop a specific analog model and extractDC, AC, 1/f noise and matching parameters


Herschel /PACS 0.3 K

IRCMOS 77 K

IRCMOS circuits designed at CEA-LETI

1024 x 1024 pitch 15 µm

Hybridisation by indium bumps


CEA-LETI 1024 x 1024 MW-IRFPA p=15 µm T=77 K


Studied CMOS processes (1/2)

� 0.7 µm - 5 V standard CMOS process:• Single gate process (N + poly-Si ):

NMOS: surface channel (TCV_N ≈≈≈≈ 1 mV/K)PMOS: buried channel (TCV_P ≈≈≈≈ 2 mV/K)

• AeroSense, SPIE Symposium (Orlando 2001)

� 0.5 µm - 3.3 V standard CMOS process:• Single gate process (N + poly-Si )


Studied CMOS processes (2/2)

� 0.35 µm - 3.3 V standard CMOS process:• Single gate process (N + poly-Si ):

NMOS: surface channel (TCV_N ≈≈≈≈ 1 mV/K)PMOS: buried channel (TCV_P ≈≈≈≈ 2 mV/K)

• WOLTE-5 (Grenoble 2002)

� 0.21 µm - 1.8 V std. process:• Dual gate process: NMOS & PMOS surf. channels only(TCV_N ≈≈≈≈ TCV_P ≈≈≈≈ 1 mV/K) + Pocket implants• MIXDES (Lodz 2003) & WOLTE-6 (Noordwijk 2004)


The standard version of the EKV model at LT: main problem

NMOS 77 K Tox=150 nm W/L=20/20 µm Vds=50 mV [1]

EKV 2.3 (THETA)


(From M. Bucher, CMC meeting, June 2004)

The standard version of the EKV model at LT: main problem

µeff vs. Eeff

1/ Coulomb scatt.

2/ Phonon scatt.

3/ SR scatt.

Qi = f(x), x = 0 →→→→ L

Matthiessen


The LT version of the EKV 2.6 model: main improvement

• New charge-based mobility model:

• 5 parameters: µ 0, αααα1, ECO, EPH, ESR• Local mobility →→→→ global mobility through integrationalong the channel

(((( ))))Si

bieff

2

eff31

eff1-

eff

0 QQqEwith

ESRE

EPHE

ECOE

++++====

++++

++++

====


Freeze-out effects at LT

-130 °C ∼∼∼∼ 140 K


Freeze-out effects at LT

1. Freeze-out effects in substrate (T ≤≤≤≤ 10 K)

2. Freeze-out effects in buried channel PMOS

3. Freeze-out effects in LDD zones


1. Freeze-out effects at very LT

T = 4.2 K (L4He) : kink effect + hysteresis

Ids(Vds)

Gds(Vds)



Subthreshold swing in 0.5 µm CMOSwith single N+ poly-Si gate

0

25

50

75

100

0 50 100 150 200 250 300

T (K)

S (mV/dec)

PMOS

NMOS

2.3 kT/q



• Degradation of the weak inversion slope (T < 200 K)

• New parameter: NUO (1st-order estimation)

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0.5 0.75 1 1.25 1.5 1.75 2

- Vgs [V]

- Id [A]

W/L=20/20 Vds=- 50 mV

Vbs=0 Vbs=3 V

NUO=2.6

NUO=1

Meas.

0.35 µm CMOS with single N+ poly-Si gate

T = 77 K



• Less important degradation of the weak inversion sl ope

• Parameter NUO still needed: NUO=1.9 PMOS, NUO=1.5 N MOS

0.21 µm CMOS with dual poly-Si gate: no buried channel

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

- Vgs (V)

- Id (A)

W/L=20/20 Vds=-50 mV Vbs=0 V

NU0 = 1

optim. NU0 > 1

exp. T = 77 K


3. Freeze-out effects in LDD zones: NMOS 77 K

0.35 µm CMOS process 0.21 µm CMOS process

No freeze-out effects in 0.21 µm tech.Influence of pockets ?

Strong influence on Gds at T ≤≤≤≤ 150 K in prev. processes

0.0E+00

5.0E-03

1.0E-02

1.5E-02

0 0.2 0.4 0.6 0.8

Vds (V)

Gds (S)

Vgs = 3 V

1 V

2 V

W/L=20/0.35

0.0E+00

2.0E-02

4.0E-02

0 0.2 0.4 0.6 0.8

Vds (V)

Gds (S)

Vgs=2.5 V

1 V

W/L=20/0.21

Not modelised


Some examples of simulation

• ELDO circuit simulator (Mentor Graphics)

+ UDM/CMPI (User Defined Model)

• UTMOST (Silvaco) for parameter extraction & optimiza tion

� On 0.21 µm CMOS process

� After parameter optimisation: Lmin<L<20µm ; Wmin<W<2 0 µm ;weak/moderate/strong inversion


Drain current Id Gate transconductance Gm

Linear (ohmic) regime Vds = 50 mV

Ex: NMOS transfer characteristics at 77 K (1/2)

Negative transconductance Gm

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

0 0.5 1 1.5 2 2.5

Vgs (V)

Id (A)

0E+00

2E-05

4E-05

6E-05

8E-05W/L=20/20 Vds=50 mV Vbs=0 to -2 V step -0.5 V

NMOS 77 K

-2E-05

0E+00

2E-05

4E-05

6E-05

8E-05

1E-04

0 0.5 1 1.5 2 2.5

Vgs (V)Gm (S)

W/L=20/20 Vds=50 mV Vbs=0 to -2 V step 0.5V

meas.

sim.


Drain current Id Gate transconductance Gm

Saturation Vds = 2.5 V

Ex: NMOS transfer characteristics at 77 K (2/2)

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

0 0.5 1 1.5 2 2.5

Vgs (V)

Id (A)

0.0E+00

4.0E-04

8.0E-04

1.2E-03

1.6E-03W/L=20/20 Vds=2.5 V Vbs=0 to -2 V step -0.5 V

NMOS 77 K

0.0E+00

2.5E-04

5.0E-04

7.5E-04

1.0E-03

0 0.5 1 1.5 2 2.5

Vgs (V)Gm (S)

meas.

sim.


Linear regime Vds = - 50 mV Saturation Vds = - 2.5 V

Ex: PMOS transfer characteristics at 77 K

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

0 0.5 1 1.5 2 2.5

- Vgs (V)

- Id (A)

0.0E+00

4.0E-06

8.0E-06

1.2E-05W/L=20/20 Vds=-50 mV Vbs=0 to 2 V step 0.5 V

0.0E+00

5.0E-05

1.0E-04

1.5E-04

0 0.5 1 1.5 2 2.5

Vgs (V)

Gm (S)

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

0 0.5 1 1.5 2 2.5

- Vgs (V)

- Id (A)

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04W/L=20/20 Vds=-2.5 V Vbs=0 to 2 V step 0.5 V

0E+00

5E-06

1E-05

0 0.5 1 1.5 2 2.5

-Vgs (V)

Gm (S)

meas.

sim

.


Ex: Short-channel PMOS at 77 K

W/L=20/0.32

Id(Vd)Id(Vg) Lin & Log

0E+00

2E-03

4E-03

6E-03

8E-03

0 0.5 1 1.5 2 2.5

- Vds (V)- Id (A)

-Vgs=1 to 2.5 V step 0.5 V

1E-12

1E-10

1E-08

1E-06

1E-04

1E-02

0 0.5 1 1.5 2 2.5

- Vgs (V)

- Id (A)

0E+00

2E-03

4E-03

6E-03

8E-03Vds=-2.5 V Vbs=0 to 2 V step 1 V


NMOS output characteristics

77 K

Drain current Id

Drain conductance Gds

Ex: Long-channel NMOS 0.35 µm CMOS

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

0 0.5 1 1.5 2 2.5 3 3.5

Vds [V]

Id [A]

W/L=1µm/20 µm Vbs=0 V Vgs=1.1 V

Vgs=0.7 V

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0 0.5 1 1.5 2 2.5 3 3.5

Vds [V]

Gds [S]

Vgs=0.6 V

Vgs=1.1 V

exp

sim


NMOS drain conductance 77 K long-channel (L = 20 µm )

Pocket implants & long channel MOSFETs

• Important degradation of Gds in saturation ( ≈≈≈≈ 1 decade)

• Effect not specific to LT; same problem at RT

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

0 0.5 1 1.5 2 2.5

Vds (V)

Gds (S)

Id = 1 µA

Id = 65 µA

0.21 µm CMOS process (with pockets)

0.35 µm CMOS process (w/o pockets)


AC parameters vs. temperature

CJ (T) CJSW (T)

MJ & MJSW

5.0E-04

1.0E-03

1.5E-03

50 100 150 200 250 300 350

T (K)

CJ (F/m

2)

P+/N

N+/P

0E+00

1E-10

2E-10

3E-10

50 100 150 200 250 300 350

T(K)

CJSW

(F/m

)

P+/N

N+/P

0.0

0.1

0.2

0.3

0.4

0.5

0.6

50 100 150 200 250 300 350

T (K)

MJ, MJSW

P+/N

N+/P

P+/N

N+/P

MJ

MJSW


Low frequency noise at LT

(((( ))))AF

ox

2

m2

IdfCLW

GKFHz/AS ====

1/f noise model in std. EKV 2.6 :


LF noise and evolution with temperature

After optimization in weak & moderate inversion

NMOS

1E-26

1E-25

1E-24

50 100 150 200 250 300

Temperature (K)

KF (V

2 F)

dKF/dT=-4.6E-3 V2F/K

dKF/dT=-4.0E-3 V2F/K

0.21 µm process

0.35 µm process

1E-26

1E-25

1E-24

50 100 150 200 250 300

Temperature (K)

KF (V

2 F)

dKF/dT=3.9E-3 V2F/K

dKF/dT=5.1E-3 V2F/K

0.21 µm process

0.35 µm process

PMOS


NMOS T = 77 Kf = 1 Hz

|Vds| = 1.8 or 3.3 VWmin < W < 20 µmLmin < L < 20 µm

LFN model: test from weak to strong inversion

• Better agreement:

• For 0.5, 0.35 & 0.21 µm CMOS, single & dual gateprocesses, RT & LT: 1.8 < EF < 2.3 (tech. dependent )

AF

ox

EF

m

IdfCLW

GKFS ====

Normalized noise spectral density

1E-41

1E-39

1E-37

1E-35

1E-33

1E-31

1E-29

1E-27

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

Gm (S)

W L Cox SId (A

2 F/H

z)

0.21 µm process

0.35 µm process


PMOS T = 77 Kf = 1 Hz

|Vds| = 1.8 or 3.3 VWmin < W < 20 µmLmin < L < 20 µm

LFN model: test from weak to strong inversion

Normalized noise spectral density

1E-41

1E-39

1E-37

1E-35

1E-33

1E-31

1E-29

1E-27

1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

Gm (S)

W L Cox SId (A

2 F/H

z)

0.21 µm process

0.35 µm process


Pelgrom model (1989)

LW

AP)(

2

P2 ====∆∆∆∆σσσσ

22

P

2

P2DS

LW

AP)( ++++====∆∆∆∆σσσσ

D

M1 M2

M2

(P = VTO, ββββ, γγγγ)

MOSFET matching at low temperature


Transistor matching: parameter extraction

• NMOS & PMOS modules (21 transistors ; 6 different s izes : WxL = 12.6x12.6, … 0.5x0.35 µm 2 ; D = 14 µm)

• P = VTO (threshold voltage), KP (current factor), G AMMA (substrate coefficient)

• Extracted parameters: AVTO, AKP, AGAMMA• Measurements in linear regime at RT, 200 K & 77 K• Matching data at LT: very scarce in literature


Transistor matching: results on a 0.35 µm CMOS process with single N + poly-Si gate

0

2

4

6

8

10

12

50 100 150 200 250 300

Temperature [K]

AVTO [mV µm]

NMOS

PMOS

0

0.5

1

1.5

2

2.5

3

50 100 150 200 250 300

Temperature [K]

AKP [%

µm]

NMOS

PMOS

0E+00

1E-03

2E-03

3E-03

4E-03

5E-03

6E-03

7E-03

50 100 150 200 250 300

Temperature [K]

AGAMMA [V

1/2µm]

NMOS

PMOS

Tox = 7.5 nm

Threshold voltage

Current factor

Substrate coeff.


Transistor matching: results

• In general, poorer matching at LT• Notable exception : threshold voltage of PMOS with buried

channel ; AVTO extremely small at 77 K (same behavi or on PMOS 0.7 µm N+ gate process)


(((( )))) (((( )))) (((( ))))(((( ))))2thGS

2

2

2

d

d

VV

VTO4

I

I

−−−−∆∆∆∆σσσσ++++

ββββββββ∆∆∆∆σσσσ====∆∆∆∆σσσσ

(((( )))) (((( ))))VTOVn

1

I

I

td

d ∆∆∆∆σσσσ====∆∆∆∆σσσσWeak inversion :

Strong inversion :

σσσσ(∆∆∆∆Id) / Id (%) vs. Id

MOSFET matching parameters: verification in saturation

NMOS 77 K Vds=3.3 V Vbs=0 V

0.1

1

10

100

1000

1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 1E-02

Id (A)

SDId / Id (%

)

12.6/12.6

0.49/0.35

1.75/1.75

Monte Carlo


MOSFET matching parameters: implementation in ELDO ?

EKV 2.6 Model Equations:


Summary and conclusion

• Specific model based on std. EKV 2.6• 2 main improvements: mobility, weak inv. slope degr ad.• Only 6 additional parameters• 0.7 - 0.5 - 0.35 and 0.21 µm CMOS std. bulk processes• EKV-LT model implemented in ELDO and UTMOST• Still compact and continuous charge-based model• Additional results on LF noise and transistor match ingevolution with temperature• Excellent tool for analog IC design at LT


References

[1] F. Théodoloz, C. Enz, M. Bucher, Charge Based MOS Transistor Mobility Modelling Applicable at Low Temperature, unpublishe d EPFL Technical Report

[2] P. Martin, M. Bucher and C. Enz, MOSFET Modelin g and Parameter Extraction for Low Temperature Analog Circuit Desig n, 5th European Workshop on Low Temperature Electronic (WOLTE-5), G renoble, June 2002

[3] P. Martin and M. Bucher, MOSFET Modeling for Lo w Temperature (77 K –200 K) Analog Circuit Design, MIXDES-03, Lodz, Pola nd, June 2003

[4] P. Martin and M. Bucher, Comparison of 0.35 and 0.21 µm CMOS Technologies for Low Temperature Operation (77 K – 2 00 K) and Analog Circuit Design, 6 th European Workshop on Low Temperature Electronic (WOLTE-6), ESTEC, Noordwijk, The Netherlands, June 2004

Documents

MOSFET Modeling for Low Temperature Analog Circuit Design