More on Programmable Logic Devices (Class 7.2 – 10/11/12)

CSE 2441 – Introduction to Digital Logic

Fall 2012

Instructor – Bill Carroll, Professor of CSE

Today’s Topics

• More programmable logic devices

– Programmable Read-Only Memory (PROM)

– Programmable Array Logic (PAL)

• Cyclone II Field Programmable Gate Arrays (FPGAs)

• Preview of Lab 6

Basic Programmable Device Organization

Figure 5.15

InputsProduct

terms Outputs

ANDarray

I1

I2

IK

P1

P2

PN

O1

O2

OM

Feedback terms

FM

F1

Sumterms

OR

array

S1

S2

SM

OUTPUToptions

.

. .....

.

.

. ..

.

.

.

.

.

.

Overview of Programmable Logic Devices

• PLA – AND array and OR array are programmable

• PROM – AND array fixed, OR programmable

• PAL – AND array programmable, OR array fixed

• FPGA – programmable array of logic elements

Programmable Read-only Memory

• A PROM comprises a fixed AND array and a programmable OR array, as illustrated in Fig. 5.21.

The AND array generates all 2n possible minterm products of its n inputs and therefore often referred to as an n-to-2n decoder.

The OR array allows any combination of product terms to be included in each sum term. The canonical sum of products form of any function can be realized directly from its truth table or minterm list.

• Figure 5.22 illustrates the organization of most typical commercial PROMs.

Programmable Read-only Memory (PROM)

Figure 5.21

I0

I1

I2

m0

m1

m2 m

3m

4 m5 m

6m

7

Ok

O1

O2

Fixed

AND

array

Minterms

Programmable

OR array.

.

.

General Configuration of a Commercial PROM

Figure 5.22

A0

A1

AN-1

CE

P0 P

1 P2N-1

OMO

1 O2

ANDarray

Outputs

Productterms

Outputdrivers

Chip enable

.

Inputs

.

ORarray

.

.

..

.. .

Realizing Logic Functions with PROMs

• Each output of a PROM is capable of realizing any arbitrary switching function by connecting that output to the minterms of the function.

To realize a given switching function with a PROM, first express the function in canonical SOP form or else derive the truth table of the function.

Then, each of the minterms of the function is connected to the desired OR term to produce the canonical SOP form.

• It should be noted that the use of a commercially available PROM would be very inefficient when only a small number of minterms is needed, unless minimizing chip count is the primary goal.

PROM Realization -- Example 5.6

Realize the following 3 switching functions with a 3-input, 3-output PROM.

f1(A, B, C) = AB + B’C

f2(A, B, C) = (A + B’ + C)(A’ + B)

f3(A, B, C) = A + BC

First, convert each function to canonical SOP form.

f1(A, B, C) = ABC’ + ABC + A’B’C + AB’C

= m(1, 5, 6, 7)

f2(A, B, C) = (A + B’ + C)(A’ + B + C’)(A’ + B + C)

= M(2, 4, 5) = ∑m(0, 1, 3, 6, 7)

f3(A, B, C) = AB’C’ + ABC’ + AB’C + ABC + A’BC

= m(3, 4, 5, 6, 7)

PROM Realization for Example 5.6

Figure 5.23

PROM Realization of a Binary to Gray-Code Decoder Example 5.8

• Design a binary to Gray code converter using a 4-input, 4-output PROM.

The truth table of the code converter is given in Table 5.4.

Note that 15 of the 16 possible minterms are present in the output (only minterm 0 is not contained in any of the 4 outputs).

The truth table is mapped onto a PROM as illustrated in Fig. 5.25.

Binary-to-Gray Code Truth Table Table 5.4

Decimal Binary Gray Code Number B3B2B1B0 G3G2G1G0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000

PROM Realization of the Binary-to-gray Code Converter

Figure 5.25

Lookup Tables (LUT)

• A common application of PROMs is the lookup table, in which a function is stored in tabular form with its arguments used as an index into the table to retrieve the value of the function for those arguments.

• Since truth tables can be readily realized by PROMs, lookup tables are implemented by writing them in truth table format and then realizing the truth table with a PROM.

Programmable Array Logic (PAL)

Example 5.10 – PAL Design Example

Realize the following functions with a PAL

fα(A,B,C,D) = A’B’D’ + B’CD’ + A’BCD

fβ(A,B,C,D) = A’B + B’CD’

fγ(A,B,C,D) = A’B’D’ + B’C’D’ + A’BCD

Example 5.10 -- PAL Realization

Cyclone II FPGA*

*From Cyclone II Device Family Data Sheet

LAB – Logic Array Block, PLL – Phase Locked Loop, IOEs – I/O Elements

Cyclone II FPGA Family Features*

*From Cyclone II Device Family Data Sheet

Cyclone II Package Options*

*From Cyclone II Device Family Data Sheet

Cyclone II Device Resources*

*From Cyclone II Device Family Data Sheet

Cyclone II Logic Element Architecture*

*From Cyclone II Device Family Data Sheet

Cyclone II Logic Element in Normal Mode*

*From Cyclone II Device Family Data Sheet

Cyclone II Logic Element in Arithmetic Mode*

*From Cyclone II Device Family Data Sheet

Preview of Lab 6

• Tutorial on the use of the Altera DE1 board. – Guided Tour Exercise – Do-It-Yourself Exercise

• DE1 features – Cyclone II EP2C20F484C7 field programmable gate array – Ten data switches (SW0-SW9) – Four debounced pushbutton switches (KEY0-KEY3) – Ten red LED displays (LEDR0-LEDR9) – Eight green LED displays (LEDG0-LEDG7) – Four 7-segment LED displays (HEX0-HEX3) – RUN/PROG switch – ON/OFF switch – Power port – USB/MIC/LINE-IN/LINE-OUT/VGA/RS-232/PS2/BNC I/O ports – Two header blocks – SD memory card slot – SDRAM/SRAM/Flash on-board memory chips

Altera DE1 Layout

Basic Operation of the DE1

• Run the Power-On test that is preprogrammed in to the on-board Cyclone II FPGA – Plug the power supply in to an AC outlet and then in to the DE1 power port. – Connect the DE1 to your laboratory computer using a USB cable. – Place the RUN/PROM switch in the RUN position. – Press the red Power button to turn on the DE1. – A correctly functioning DE1 will now be displaying the following.

• Observe – Blue Power LED will be on – The hexadecimal characters will be cycling over and over on the 7-segment displays – The red and green LEDs will be flashing.

• This test will run every time the DE1 is powered on unless the test program has been erased.

• The Cyclone II FPGA must be configured or “programmed” before it can perform or implement the desired functionality. Programming an FPGA is the equivalent of interconnecting gates and flip flops with wires or a printed circuit. But, as you will learn, much easier and faster.

Programming the DE1 Cyclone II FPGA

1. Capture, or enter, your circuit design using Quartus II. This can be a circuit diagram or HDL (VHDL or Verilog) code.

2. Compile your design. 3. Verify your design using Qsim or another simulator. 4. Assign the input/output nodes of your design to specific pins on

the FPGA. This can be done using the Quartus II Assignment Editor.

5. Recompile your design so that the input/output assignments will be incorporated.

6. Download or program the Cyclone II with your design using the Quartus II Programmer tool.

7. Test your design using the DE1 input switches and output LEDs.

Guided Tour Circuit

Pin Assignments

A (SW3) -> PIN_V12

B (SW2) -> PIN_M22

C (SW1) -> PIN_L21

D (SW0) -> PIN_L22

f (LEDG0 -> PIN_U22

DE1 Guided Tour

Demonstration