MonolithIC 3D Inc. Patents Pending 1 Monolithic 3D Integrated Circuits Deepak C. Sekar, Paul Lim, Brian Cronquist, Israel Beinglass and Zvi Or-Bach MonolithIC

MonolithIC 3D Inc. Patents Pending 1 Monolithic 3D Integrated Circuits Deepak C. Sekar, Paul Lim, Brian Cronquist, Israel Beinglass and Zvi Or-Bach MonolithIC 3D Inc. Presentation at TU Munchen, 12 th May 2011

Outline Introduction Paths to Monolithic 3D IntSim+3D: A 2D/3D-IC Simulator Conclusions MonolithIC 3D Inc. Patents Pending 2

Introduction MonolithIC 3D Inc. Patents Pending 4 Transistors improve with scaling, interconnects do not Even with repeaters, 1mm wire delay ~50x gate delay at 22nm node

The repeater solution consumes power and area Repeater count increases exponentially At 45nm, repeaters >50% of total leakage power of chip [IBM]. Future chip power, area could be dominated by interconnect repeaters [P. Saxena, et al. (Intel), IEEE J. for CAD of Circuits and Systems, 2004] MonolithIC 3D Inc. Patents Pending 5 130nm 90nm 65nm 45nm Repeater count Source: IBM POWER processors R. Puri, et al., SRC Interconnect Forum, 2006

We have a serious interconnect problem Whats the solution? MonolithIC 3D Inc. Patents Pending 6 Arrange components in the form of a 3D cube short wires James Early, ISSCC 1960

MonolithIC 3D Inc. Patents Pending 7 3D with TSV Technology TSV size typically >1um: Limited by alignment accuracy and silicon thickness Processed Top Wafer Processed Bottom Wafer Align and bond

Industry Roadmap for 3D with TSV Technology MonolithIC 3D Inc. Patents Pending 8 TSV size ~ 1um, on-chip wire size ~ 20nm 50x diameter ratio, 2500x area ratio!!! Cannot move many wires to the 3rd dimension TSV: Good for stacking DRAM atop processors, but doesnt help on-chip wires much ITRS 2010

Can we get Monolithic 3D? Requires sub-50nm vertical and horizontal connections Focus of this talk MonolithIC 3D Inc. Patents Pending 9

Getting sub-50nm vertical connections Build transistors with c-Si films above copper/low k Avoids alignment issues of bonding pre-fabricated wafers Need

Layer Transfer Technology (or Smart-Cut) Defect-free c-Si films formed @

Sub-400 o C Transistors MonolithIC 3D Inc. Patents Pending 13 Junction Activation: Key barrier to getting sub-400 o C transistors Transistor partProcessTemperature Crystalline Si for 3D layerBonding, layer-transferSub-400 o C Gate oxideALD high kSub-400 o C Metal gateALDSub-400 o C JunctionsImplant, RTA for activation >400 o C In next few slides, will show 2 solutions to this problem both under development. For other techniques to get 3D-compatible transistors, check out www.monolithic3d.com

One path to solving the dopant activation problem: Recessed Channel Transistors with Activation before Layer Transfer MonolithIC 3D Inc. Patents Pending 14 p- Si wafer Idea 1: Do high temp. steps (eg. Activate) before layer transfer Oxide H Idea 2: Use low-temp. processes like etch and deposition to define (novel) recessed channel transistors Note: All steps after Next Layer attached to Previous Layer are @ < 400 o C! n+ p p- Si wafer p n+ n+ Si p Si n+ p p Idea 3: Silicon layer very thin (

IntSim+3D: A Simulator for 2D or 3D-ICs MonolithIC 3D Inc. Patents Pending 20 IntSim+3D Stochastic signal interconnect models contains Energy-Delay Product repeater insertion Models Power models Logic gate model Inputs Gate count Die area Frequency Rents parameters Number of strata (1 if 2D, >=2 for 3D) Chip power Metal level count Wire pitches Outputs Power, Clock, Thermal Interconnect models Via blockage

IntSim+3D: Uses a novel algorithm to combine many models MonolithIC 3D Inc. Patents Pending 21 Global interconnect levels Shared among all strata Model [D. C. Sekar, J. D. Meindl, et al., IITC 2006] Local and semi-global interconnect levels Each stratum has its own Models PhD dissertations of A. Rahman (MIT), R. Venkatesan, D. Sekar, J. Davis, R. Sarvari (Georgia Tech) Logic gates Critical path model developed by K. Bowman (Georgia Tech)

Stochastic Signal Wire Length Distribution Model Models from J. Davis, A. Rahman, J. Meindl, R. Reif, et al. [A. Rahman, PhD Thesis, MIT 2001] [J. Davis, PhD Thesis, Georgia Tech, 1999] 2D model fits experimental data reasonably well [J. Davis, PhD Thesis, GT, 1999] 3D model same methodology MonolithIC 3D Inc. Patents Pending 22 Number of wires of length l = Function(Number of gates, die size, strata, feature size, Rents constants) Number of wires of length between l and l+dl = idf(l) dl

Logic gate model MonolithIC 3D Inc. Patents Pending 23 Two input NAND gates with average wire length, fan-out user defined...... Find W for a certain performance target

Global interconnect model Results match well with commercial processors [D. C. Sekar, et al., IITC 2006] MonolithIC 3D Inc. Patents Pending 24 Global wire pitch obtained based on two conditions: (1)Signal bandwidth maximized with power grid IR drop requirement being reached (2)Wire pitch big enough to drive a clock H tree of a certain length

Local and semi-global interconnect model MonolithIC 3D Inc. Patents Pending 25 Condition 1: Wiring area available = Wiring needed for routing the stochastic wiring distribution Condition 2: RC delay of longest signal wire in each wiring pair = fraction of clock period For wires with repeaters, new Energy-Delay Product repeater insertion model used Condition 3: Wire efficiency ( e w ) = 1 fraction of wiring area lost to power wiring, via blockage [Sarvari, et al. - IITC07] [Q. Chen, et al. IITC00]

Thermal model MonolithIC 3D Inc. Patents Pending 26 Idea: Use V DD /V SS contacts of each stacked gate to remove heat from it. Design standard cell library to have low temp. drop within each stacked gate. Low (thermal) resistance V DD and V SS distribution networks ensure low temp. drop between heat sink and logic gate IntSim+3D: Computes temp. rise of 3D stacked layers using models. contact

Algorithm used to combine together all these models Iterative process used for designing chip MonolithIC 3D Inc. Patents Pending 27 1.User inputs parameters 2.Logic gate sizing 3.Select rough initial power estimate 4.Design multilevel interconnect network (including power distribution) for 3D chip with this power estimate 5.Find power predicted by IntSim+3D 6.Is predicted power = initial power? If yes, this is the final interconnect network. If no, choose new initial power estimate = average of previous initial power estimate and IntSim+3D estimate. Go to step 4. 7.Output data

Demo MonolithIC 3D Inc. Patents Pending 28 Utility of IntSim+3D: Pre-silicon optimization and estimation of frequency, power, die size, supply voltage, threshold voltage and multilevel interconnect pitches Study scaling trends and estimate benefits of different technology and design modifications Undergraduate and graduate courses in universities for intuitive understanding of how a VLSI chip works IntSim+3D App

IntSim+3D the next generation version of a CAD Tool called IntSim IntSim: Developed at Georgia Tech by Deepak C. Sekar, Ragu Venkatesan, Reza Sarvari, Jeff Davis and James Meindl. Described in [D. C. Sekar, et al., Proc. ICCAD 2007] Used and referenced by multiple researchers at Georgia Tech, UC Davis, Stanford, U. of Illinois at Chicago, Sandia, etc. MonolithIC 3D Inc. Patents Pending 29 IntSim 2D IntSim+3D 2D+3D

Compare 2D and 3D-ICs 3D with 2 strata 2x power reduction, ~2x active silicon area reduction vs. 2D MonolithIC 3D Inc. Patents Pending 30 22nm node2D-IC3D-IC 2 Device Layers Comments Frequency600MHz Metal Levels10 Average Wire Length6um3.1um Av. Gate Size6 W/L3 W/LSince less wire cap. to drive Die Size (active silicon area)50mm 2 24mm 2 3D-IC footprint 12mm 2 PowerLogic = 0.21WLogic = 0.1WDue to smaller Gate Size Reps. = 0.17WReps. = 0.04WDue to shorter wires Wires = 0.87WWires = 0.44WDue to shorter wires Clock = 0.33WClock = 0.19WDue to less wire cap. to drive Total = 1.6WTotal = 0.8W

Scaling with 3D or conventional 0.7x scaling? 3D can give you similar benefits vis--vis a generation of scaling! Without the need for costly lithography upgrades!!! Lets understand this better Analysis with 3DSim Same blocked scaled 2D-IC @22nm 2D-IC @ 15nm 3D-IC 2 Device Layers @ 22nm Frequency600MHz Metal Levels101210 Die Size (Active silicon area)50mm 2 25mm 2 24mm 2 Average Wire Length6um4.2um3.1um Av. Gate Size6 W/L4 W/L3 W/L Power1.6W0.7W0.8W

Theory: 2D Scaling vs. 3D Scaling MonolithIC 3D Inc. Patents Pending 32 Similarities: Wire length, wire capacitance 2D scaling scores: Gate capacitance 3D scaling scores: Wire resistance, driver resistance 2D Scaling (0.7x Dennard scaling)Monolithic 3D Scaling (2 device layers) Ideal Today, V dd scales slower Chip Footprint2x reduction 0.7x reduction Wire capacitance0.7x reduction Wire resistance>0.7x increase 0.7x reduction Gate Capacitance 0.7x reductionSame Driver (Gate) Resistance (Vdd/Idsat) Same IncreasesSame Overall benefits seen with IntSim+3D have basis in theory

Conclusions Monolithic 3D Technology possible and practical: - Recessed Channel Transistors - Dopant segregated Schottky transistors - Other techniques Discussed IntSim+3D, a CAD tool to simulate 2D and 3D-ICs - Useful for architecture exploration, technology predictions and teaching - Open source tool, anyone can contribute! 3D scaling benefits similar to 2D scaling, but without costly litho upgrades MonolithIC 3D Inc. Patents Pending 34

Acknowledgements Prof. Franz Kreupl For hosting me at Munich Prof. James Meindl IntSims 2D version was developed when I was doing my Ph.D. with him Past colleagues at Georgia Tech such as Ragu Venkatesan, Keith Bowman, Jeff Davis, Reza Sarvari, Azad Naeemi Bin Yang for helpful discussions on Schottky FETs MonolithIC 3D Inc. Patents Pending 35

Backup slides MonolithIC 3D Inc. Patents Pending 36

MonolithIC 3D Inc. Patents Pending 37 Monolithic 3D: A Much Sought-After Goal Tremendous benefits when vertical connectivity ~ horizontal connectivity. 3x reduction in silicon area compared to a 2D implementation, even @ 180nm node! From J. Davis, J. Meindl, et al., Proc. IEEE, 2001 Frequency = 450MHz, 180nm node, ASIC-like chip

MonolithIC 3D Inc. Patents Pending 38 Benefits of Monolithic 3D : [ICCD 2007]

MonolithIC 3D Inc. Patents Pending 39 Benefits of Monolithic 3D: Synopsys

MonolithIC 3D Inc. Patents Pending 40 The Monolithic 3D Challenge A process on top of copper interconnect should not exceed 400 o C How to bring mono-crystallized silicon on top below 400 o C How to fabricate advanced transistors below 400 o C Misalignment of pre-processed wafer to wafer bonding step is ~1 How to achieve 100nm or better connection pitch How to fabricate thin enough layer for inter-layer vias of ~50nm

MonolithIC 3D Inc. Patents Pending 41 3D-ICs: The Heat Removal Question Sub-1W smartphones, cellphones and tablets the wave of the future Heat removal not a key issue there can 3D stack. Also, shorter wires net power reduced.

MonolithIC 3D Inc. Patents Pending 42 Escalating Cost of Litho to Dominate Fab and Device Cost

MonolithIC 3D Inc. Patents Pending 43 Courtesy: GlobalFoundries

MonolithIC 3D Inc. Patents Pending 44 Severe Reduction in Number of Fabs (Source: IHS iSuppli)

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MonolithIC 3D Inc. Patents Pending 1 Monolithic 3D Integrated Circuits Deepak C. Sekar, Paul Lim, Brian Cronquist, Israel Beinglass and Zvi Or-Bach MonolithIC