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module dct1(sel,y);

input [2:0]sel;

output reg [15:0]y;

wire [15:0]y0,y1,y2,y3,y4,y5,y6,y;

wire [:0]p0,p1,p2,p3,p10,p11,p100,m0,m1,m2,m3,m10,m11,m100; wire [15:0]n0,n1,n2,n3,!0,!1,!2,!3;

wire [:0]"0,"1,"2,"3,"4,"5,"6,";

## pre decl$red

p$r$meter c1%&'11111011;

p$r$meter c2%&'11101100;

p$r$meter c3%&'11010100;

p$r$meter c4%&'10110101;

p$r$meter c5%&'10001110;p$r$meter c6%&'01100001;

p$r$meter c%&'00110001;

## pre decl$red

$ssign "0%&'10110;

$ssign "1%&'1001;

$ssign "2%&'101;

$ssign "3%&'1111;

$ssign "4%&'1011;

$ssign "5%&'10;

$ssign "6%&'100;

$ssign "%&'10010;

##utter *ly +t$ges

##st$ge1

ly1 s11("0,",p0,m0);

ly1 s12("3,"4,p1,m1);

ly1 s13("1,"6,p2,m2);

ly1 s14("2,"5,p3,m3);

##st$ge2

ly2 s21(m0,m1,c1,c,n0,!0);

ly2 s22(m2,m3,c3,c5,n1,!1);

ly2 s23(m0,m1,c5,c3,n2,!2);

ly2 s24(m2,m3,c,c1,n3,!3);

ly1 s15(p0,p1,p10,m10);

ly1 s16(p2,p3,p11,m11);##st$ge3

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ly2 s31(m10,m11,c2,c6,y2,y6);

ly1 s32(p10,p11,p100,m100);

$ssign y1%n0-n1;

$ssign y%!0-(.!1-1);$ssign y5%n2-(.!3-1);

$ssign y3%!2-(.n3-1);

$ssign y0%p100/c4;

$ssign y4%m100/c4;

$lw$ys(sel)c$se(sel)

0:egin y%y0; end

1:egin y%y1; end

2:egin y%y2; end

3:egin y%y3; end

4:egin y%y4; end

5:egin y%y5; end

6:egin y%y6; end

:egin y%y; end

endc$se

endmodule

module ly1(",y,p,m);

input [:0]",y;

output[:0]p,m;

$ssign p%"-y;

$ssign m%"-(.y-1);

endmodule

module ly2(",y,c",cy,s",sy);

input [:0]",y,c",cy;

output [15:0]s",sy;

$ssign s"%("/c")-(y/cy);

$ssign sy%("/cy)-(.(y/c")-1);

endmodule