Modular networks for direct processing ofdelta-modulated signals

G.B. Lockhart

Indexing terms: Signal processing, Delta modulation, Digital filters, Digital arithmetic

Abstract: Modular networks for arithmetic signal processing are described for operation with delta-modulatedinput and output signals. It is shown that designs based on the concept of the digital delta-modulationencoder provides a flexible approach to implementation of arithmetic units using full adders and flip-flopsencompassing both serial and parallel forms. Schemes for the elementary operations of addition and multi-plication by a constant coefficient are presented and maximum quantisation error is determined. The effectof input errors when the elementary unit is embedded in a larger network is also discussed including idlingsequences introduced at the inputs as approximations to zero. Networks for signal mixing and digital filteringare developed by combining elementary units and the complexity and maximum quantisation error of each aredetermined. It is shown that in most cases greater economies in hardware and/or less quantisation error canbe achieved in comparison with existing techniques.

1 Introduction

Delta-modulation1 (d.m.) is a simple encoding techniquewhich is becoming common as an alternative to pulse-codemodulation (p.cm.). In applications where low cost takesprecedence over bandwidth considerations, direct signalprocessing of d.m. encoded signals can be an attractiveproposition and the use of d.m. to realise very simpleprocesses (e.g. pure delay via binary-shift registers) has longbeen established. Further possibilities for d.m. as a vehiclefor more sophisticated arithmetic processes such as digitalfiltering has aroused considerable interest and techniqueswhich parallel those based on p.cm. are beginning toemerge.2"9

Early work in this area1"3 was concerned with hybridanalogue/digital techniques, but later approaches4"8

consider digital networks retaining all the well-knownadvantages of digital signal processing. It has been shown5

that d.m. of a digital rather than an analogue signal is auseful concept in designing such networks, and this hasbeen applied7 to the implementation of simple adders anddigital filters operating with binary coefficients. A stimu-lating paper by Kouvaras8 introduces the 'delta full adder',consisting of a full adder (f.a.) and flip-flop (f.f.) pair andshows that modular networks for parallel addition, multi-plication and digital filtering with multibit coefficients maybe constructed using delta full adders as building blocks.The techniques which will be described also lead tomodular networks of f.a. and f.f, but are derived from theconcept of the digital encoder. This provides a more generaland flexible approach encompassing both serial and parallelforms and in most cases leads to greater economy of hard-ware and/or less quantisation error in comparision withKouvaras networks based on the delta adder. It also circum-vents the need for specialised mathematical approachformulated by Kouvaras.

2 Delta modulation of digital inputs

A digital equivalent of a simple d.m. encoder is illustratedin Fig. 1. The circuit is clocked every Ts in synchronismwith input and output samples which are digitally encoded•and have successive values given by n = 0, 1 , 2 , . . . . The

Paper T462 C, first received 8th May and in revised form 20thSeptember 1979Dr. Lockhart is with the Department of Electrical & ElectronicEngineering, University of Leeds, Leeds LS2 9JT, England

binary output bn = ± 1 depends on the sign of the error(Xn — yn_j) where Yn is the locally encoded output. bn ismultiplied by the step height 5 and fed to the register withfeedback which operates as a digital accumulator, equiv-alent to the ideal integrator of the simple analogue d.m.The decoder output Yn will track the input Xn, providedthe slope of Xn is such that

W < 6 (1)

The notation of capitals for signal samples and lower casefor incremental samples is adopted, i.e. xn= Xn — Xn-i.

Provided this inequality is satisfied, it can be shown5 thatthe d.m. process of Fig. 1 reduces to that of Fig. 2 in whichthe incremental input xn replaces Xn. In this case theregister operates modulo 25, so that the maximum value itcan represent without overflow is (26 — 1). Overflowbeyond this value effectively subtracts 25 from the accumu-lated sum. The process can be usefully interpreted as one ofslope bias, accumulation and overflow detection. This isapparent by adding a 'ramp' nb~ to Xn while adding a con-stant 5 to yn so that the overall operation of the encoder isundisturbed. The accumulator and sign detector then act as

clock

Fig. 1 Direct digital equivalent of analogue d.m. encoder

overflowdetector

u (modulo 26)

register

Fig. 2 Simplified digital equivalent of analogue d.m. encoder

COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6 237

0140-1335/79/060237 + 07 $01-50/0

a linear quantiser with step 25, input (Xn + nd) and output(y n _! 4- nd). Since the incremental output bn is requiredrather than {Yn_x 4- n8), this quantiser can be implemen-ted digitally by a modulo 25 accumulator, provided eachoverflow is detected to determine bn and the inequality,eqn. 1, is respected to avoid ambiguities. If the incrementalinput xn is available rather than Xn, then the initial slopebias is performed by forming the input (xn 4- 5) as in Fig.2.

The process is described by the following equations:

gn)

gn = xn 4- 5

un ~ On-l ±gn)-Q{Un-

50+*„) = Q(un.x+gn)

where Q(-) is a quantisation function defined by

Q(v) =0,

25

v<28

v>28

gn in eqn. 2 represents the input signal with a slope bias of6 units. If the slope overload constraint of eqn. 1 is satisfiedthen

( ) < # „ < 25

and the slope of

is always nonnegative. Modulo 25 accumulation is rep-resented in eqn. 3 and overflow detection is representedin eqn. 4 since the binary output bn = 1 only when(«„_! 4- gn) > 25, coinciding with register overflow.

The decoded output

yn = t «**will therefore rise by 5 units only when the slope-biasedinput Gn crosses the boundaries 25, 45, 65, . . . . Thisinterpretation of a d.m. process is illustrated in Fig. 3 for aparticular input sequence and 5 = 5. A continuous line hasbeen drawn through the sample points of Xn for clarityalthough this is strictly a digital representation of a sampledsignal. The scale of Gn is compressed by a factor of 4 sothat transitions of Gn beyond the boundaries 0, 2-5, 5,7-5, . . . on the main scale result in increases in Yn of 5units.

0

-5

-10

3 5 7 9 11 13 15 17 19 2>v23 25 27 29 ,

sample number no o . o

The quantisation error, en, is given by

n n

= Z yk - Z xk

(5)

(2)

(3)

(4)

and

<

and

e

from

' n =

from

eqns. 2 andn

fe = l

eqn. 3n

Z "fc-i -fe=l

4

+ gk)~gk

uk

Since o < un < 25, it follows that:

uo - 25 < en < uo

The number un represented by the register is thereforea measure of the encoding error. To minimise the errorthe initial register value should be set to the step height(i.e. uo — 5) in which case \en\ < 5 .

If uo =£ 5, a constant component of mean value (uo — 6)will be effectively added to the output Yn. This will oftenbe tolerated, but in some cases, e.g. subsequent filteringwith high gain at zero frequency, it may be necessary toinitialise un.

3 Multiplication schemes

If an input Dn is digitally multiplied by a constant K andpassed to a digital d.m. encoder, then, by setting KDn = Xn

in eqn. 5, the decoded output is given by

therefore

= KD

8bk = KDn + e

= MDn + a (6)therefore

where M = Kd~l and an = en5~l

Thus Bn, the signal obtained by decoding the d.m. out-put bn = ± 1 without prior multiplication by 5, representsMDn within an error an. Assuming uo = 6 so that |en | < 5,then |o:n| < 1. If Dn itself is a d.m. encoded signal thendn = ± 1 and

xn = Kdn = ± K

To satisfy eqn. 1

\xn\ = \Kdn\ = \K\ < 5

from which it follows that multiplication by a constantgreater than unity cannot be achieved by this method since

With dn = ±\ implementation of a d.m. multiplier maybe achieved by feeding ± K, according to the sign of dn, tothe digital d.m. encoder of Fig. 2. Implementation is con-siderably simplified if 5 is a power of 2 leading to the net-work of f.a. and f.f. illustrated in Fig. 4. Primes are used todenote the logic representation of d.m. encoded signals, e.g.

Fig. 3 Derivation of a d.m. encoded signal Ynfrom Gn = Xn + n8

238 COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6

Let 5 = 2P, p = 1, 2, 3,. . . . If K is expressed in termsof its p binary digits (KO,KU. . . Kp.^ then, for K<2P

M = K2~p = Y Kr2r~p (8)

r=0and from eqns. 2 and 7 the biased input gn = Kdn + 2P.gn can then be expressed as one of two binary numbersdepending on the sign of dn, i.e.

f o r p = l , 2 , 3 , . . then eqn. 8 applies directly.

gn =+ 1 x 2 dn = 1

Kp.l2P~

+ 1 x 2P, dn = -1 (9)

where Kr denotes the logical complement of Kr. In Fig. 4,gn is generated by a series of EX-NOR gates and added tothe register contents, un~x, by the f.a. which form a paralleladder. The binary digits of the sum un appear on outputsSo to Sp with overflow greater than or equal to 25 = 2P + 1

neglected as required by eqn. 3. The output according toeqn. 4 is generated by the most significant carry output Cp.When the next clock pulse is applied, un appears at the f.f.outputs as un-x, and the process repeats forgn+1. It shouldbe noted from eqn. 9 that f.a.O could be eliminated fromFig. 4 by using simple logic to feed either the idlingsequence /^ = 0, 1,0, 1 , . . . to the carry input of f.a.i ifKQ=\ or a constant logic 1 if AT0 = 0. In general, sincecarries propagate from the least to the most significant sideof the network, the same network can be considered ter-minated at any carry output and a range of multipliersgiven by eqn. 8 may be selected by taking the output via Cp

output

f.f.(p)£lOCk

Fig. 4 Parallel multiplier for d.m. inputs

d'

clock

clockGo 'G o 'G

Fig. 5 Serial multiplier for d.m. inputs

If Kp — 0 then the most significant input is inverted effec-tively, replacing K by K — 2P in eqns. 8 and 9 in which case

M = (K-2P)2~P

(10)r=0

A multiplication scheme proposed by Kouvaras8 similar tothat of Fig. 4 achieves the same result by connecting dn toall f.a. inputs and implementing multiplier changes byappropriate inversion of carry outputs Cx, C2,. .. . Sincea carry output represents a d.m. signal, the inverted outputrepresents the negated signal and passing this to the nextf.a. achieves the same result as inverting Ko, Kx,... for allpreceding f.a. It is therefore possible to determine whethera carry output should be inverted or not for a given value ofK and Kouvaras8 has given a practical method of findingthe correct pattern of connections. There is, however, nohardware advantage over the direct method in Fig. 4.

A serial equivalent of Fig. 4 is illustrated in Fig. 5,Accumulation is performed by a single serial adder clockedby a fast clock G at (p + 1) times the d.m. clock rate. Thebits of K are continually recirculated in s.r.l and the multi-plication Kdn and formation of gn according to eqn. 9 isachieved by a single EX-NOR gate. The bits of wn_,,initially held in s.r.2 at the beginning of the /;th d.m. clockperiod, are progressively replaced by the bits of un accord-ing to eqn. 3. At the end of the d.m. clock period, the finalcarry generated by f.a. will identify with Cp. The clockinput Go switches the carry input Q of f.a. from the out-put of f.f.l to d^ only for the duration of the fast clockpulse coinciding with the beginning of a d.m. clock period.This ensures that d'n is added while Ko is processed by theEX-NOR gate according to eqn. 9. The output Cp is heldfor Ts duration by clocking f.f.2 with the last fast clockpulse Gp (preceding Go). If required, carry outputs corre-sponding to smaller values of pare also available by clockingf.f.2 with intermediate pulses of the fast clock. It should benoted that the serial multiplier can be simply multiplexedby increasing the fast clock rate and shift register lengths(including f.f.2) by a factor of N, so that N multiplicationsmay be performed with respect to A independent signal andcoefficient pairs every Ts.

4 Addition schemes

The delta-modulated average R signals represented bytheir d.m. bit streams, din,d2n, • • -dRn (dm + ± 1) can beachieved by conventional addition, followed by digital d.m.as illustrated in Fig. 6 for R = 4. Binary powers associatedwith adder inputs and outputs are indicated. In this case,the bias input is derived by assigning the values 0 or 1 tothe d.m. inputs, rather than ± 1, i.e. c/r'n = (1 + drn)/2thus

</rn)/2

L r=l

COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6 239

and comparing with eqn. 2:

and ••?It is apparent from eqns. 2, 3 and 4 that the adder operatesas a digital d.m. encoder on half the input sum with a stepheight of R/2. It then follows from eqn. 6 that the decodedoutput Bn is given by

11n = - I

where

(11)

A modular development of Fig. 6 leads to the scheme ofFig. 7 which will average R d.m. inputs via the outputs h'Rfor R = 16, 8, 4 or 2. For /? < 16, unused inputs mustbe reset, e.g. with outputs via /zg, set d'rn = 0 for r > 8 .Further development is possible for R = 32, 64, . . . orwhen R is not a power of 2. In general, for R a power of 2,log2/? f.f. and (/? — 1) f.a. will be required.

Again, a significant reduction in complexity results ifserial techniques are used, and it has been showns that asingle log2/? bit counter may be used to average R d.m.signals. Such a network is functionally equivalent to thatof Fig. 6 or 7, but is clocked at R times the d.m. clock rate.

<*1n *

d2n W

inputs

°3n m

ri' -.

\ adder section

1

i

1 1 1

1

R=4)

1

2

\

2 2

2 4

f.f. 0 :k f.f. 1

* "0

pa(0)

* -»i

po(,,

^ h'

dooutputck

f.a.Os c

L

~1f.a.1s c

I L

7 - -

2

"12

f.a.ks c

<4

k

,k.\

pa(k)

5 Quantisation error

The multiplication and addition schemes which have beendescribed involve linear arithmetic processing of inputsfollowed by digital d.m. encoding. The latter introduces amaximum quantisation error of one unit to the decodedoutput, but this will be in addition to any error contributedby input signals. In general, if a linear combination of Rinputs is formed, each in error by j3rn units, then from eqn.6 the decoded output after digital d.m. will be given by

r = l

-l +ar

where (/Tj, K2,. . .) are a set of weighting constants

Bn = KrDrn ~l

in which the first term represents the required output andthe second term the total decoded output error after digitald.m. encoding. For the case of the multiplier, R = 1 andthe output error is

(Mpln+an) where M = Kxb~l

If I f l i n K / W a n d w i t n \M\<\ and | a n | < l then Eo,the output error magnitude, will'satisfy:

0 (($ (12)

Similarly, with M = R5~l it can be shown that this ex-pression also applies to the R-input adder with each inputin error by a maximum of (imax units. The results above canbe usefully applied to schemes utilising idling sequences toapproximate decoded inputs of zero. For example, the net-work of Fig. 8 is designed to multiply by g. In this case, thebiased incremental input

Sn = dn+in+2in+4in

dibn df1nd,2n d .a

1 adder 1section(R=Z) 2

' 1 2 4

d5nP.O.©

d 9n

1 1 11 2

48 p a . (2)

13n

p.a.(0) 1 1 11 2

d)6n

pa.(Q)

f.f.O f.f.1 f.f.2 f.f.3

-•ha

pa(1)

pa.(3)

—•hie

I I IS05 ,S2S3

Fig. 6 Parallel adder for 4 d.m. inputs

240

Fig. 7 Parallel adder for 16 d.m. inputs

COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6

Table 1: Comparison of d.m. multipliers (M = §•) with and withoutthe use of iding sequences

samplenumber

123456789

10111213141516171819202122232425

decodedinput

12345678989

109

109

109

109876543

method of

decodedoutput

1010101010121212121010101

Fig. 4

error

0875-0-250

0625- 0 5 0 0

0-375-0-750

0-125- 1 0 0 0- 0 1 2 5- 1 0 0 0- 0 1 2 5

0750- 0 1 2 5

0750-0-125

0750-0-125

0750- 0 1 2 5- 1 0 0 0

0-125-0750

0-375- 0 5 0 0

0625

method of

decodedoutput

- 10101

0121212121212121010

- 1

Fig. 8

error

-1-125-0-250-1-375- 0 5 0 0- 1 6 2 5- 0 7 5 0

0-1251000

-0-1251000

-01250-750

-01250750

- 0 1 2 50750

-0-1250-750

- 0 1 2 510000125

-0-750-1-625- 0 5 0 0-1-375

input

1 1 1

1

2 2

2

f.f.Oclock

irA A

A 8

f.f. 1clock

pa.(2)

f.f. 2

output

clock

where in is the idling sequence 1 , - 1 , 1 , — 1 , . . . .By comparison with eqn. 2 it follows that Fig. 8 is a

digital d.m. encoder with a decoded input

Xn=J+7-J and 5 = 4

The output is therefore the result of delta modulating, witha step height of 4 units, half the sum of a desired d.m.signal input and an approximately zero input which fluc-tuates by 7 units every Ts. Setting ftmax = 7 and M = | ineqn. 12 then gives Eo < 15/8. This error is almost doublethe 1 unit maximum obtainable by the method of Fig. 4,and since it is apparent from Table 1 that maximum pre-dicted errors are approached in both schemes, utilisation ofidling sequences in this way is not to be recommended. Itshould be noted,however, that errors would be significantly£educed by appropriate use of the complementary sequencein to achieve input error cancellation.

Networks which combine incremental signals afterseparately accumulating inputs of the same weight will alsointroduce greater errors. Consider, for example, the 2-leveladdition network of Fig. 9. It is known from eqn. 11 thatthe error at each input of the 2-input adder will not exceed1 unit (i.e. @max = 1) and from eqn. 12 with M= 1 itfollows that £ ' 0 < 2 . This compares unfavourably withEo < 1 obtainable by replacing the network of Fig. 9 witha single R-input adder. This result can be extended to applyto the general case of an R-input, 2-level adder decomposedas L adders, each with R/L inputs feeding a single Z-inputadder. It should be noted from Table 2 that such a decom-position confers no hardware advantage since a larger

output

1

inputs

1

R -input2adder

B.-input

adder

2- input

adder

Fig. 8 Parallel multiplier (M — y using idling sequences Fig. 9 2-level parallel adder for R d.m. inputs

Table 2: Comparison of some d.m. signal-processing networks (all variables are positive integers, L and R are powers of 2)

network f.a. required f.f. requiredmaximumquantisation error

p-bit multiplier (Fig. 4)

/?-input adder (Figs. 6 and 7)

/?-input adderas L R/L-\nput adders feedingan L-input adder (Fig. 9)/?-input signal mixer withp-bit weights (Fig. 10)

Above realised as /? p-bitmultipliers feeding one /?-input adder

Mixer (Fig. 10) as /?-tapnonrecursive filter with p-bitcoefficients and x ff per unit delay

p-bit tree multiplier (Fig. 11)

Above as /?-tap nonrecursive filter(p-bit coefficients and x ff per unitdelay) feeding /?-input adder

p + 1

ft-1

ft-1

ft(p

ft(p

ft(p

2P-

2P +

+ 2)

+ 2)

+ 2)

1

ft-

- 1

- 1

-1

2

P + 1log, ft

/.log.

(P +

ft(p

ft

T +

D +

+ D

log2JL

log2ft

+ log,ft

(p + 1) + log2ft + ( / ? - 1)x

2 P - 1

- 1 + log2ft+ - ( f t - 1 ) x2

1 unit

1 unit

2 unit

1 unit

< 2 unit

1 unit

1 unit

< 2 unit

COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6 241

number of f.f. are required in comparison with a singleR-input adder. Similar conclusions may be applied to multi-level addition networks of R inputs of which a modularscheme of 2-input adders proposed by Kouvaras8 is aspecial case. Although the same number of f.a. is requiredas a single R-input adder, the number of f.f. and the maxi-mum quantisation error is greater.

6 Applications

A diversity of digital signal processors operating with d.m.inputs and outputs may be realised by combining the multi-pliers and adders which have been discussed. The salientfeatures of several such networks including the basic multi-plier and adder units are compared in Table 2. For example,the signal mixer illustrated in Fig. 10 forms a sum of R = 4d.m. encoded inputs, each of which is weighted by P= 3bit digitally-selectable coefficients. Each input is weightedand biased as for the single multiplier of Fig. 4 and allproducts are added before digital d.m. The total biasedinput is given by

R

*„ = I (Krdrn + 2P)

= I Krdrn+R2p

where Kr < 1 is the rth weighting coefficient andA'r0, Krl, . . . in Fig. 10 are the binary digits of Kr. In thiscase R = 4 and p — 3 and by comparison with eqns. 2 and 6the mixer output is given by

KrDrn + an where |a|

K10 Kn K12 K20 K21 K22

Mn

p.o{3)

Although the mixer will never overload, the proportion ofany one signal in the output cannot rise above R'1. In thesecircumstances, where the mixer is effectively required tooperate with less than R inputs, additional output gain maybe obtained by selecting intermediate carry outputs fromthe final parallel adder. If this is done, provision must bemade to isolate the unused inputs. The network may beextended in a modular fashion for a larger number of coef-ficient bits by additional combinations of parallel adders.An alternative mixer may be realised as a 2-level networkwhich performs multiplications in R separate p-bit d.m.multipliers and combines their output in an R-input d.m.adder. It is apparent from Table 2 that this approach againrequires a larger number of f.f. and can generate greaterquantisation errors.

Networks designed for mixing d.m. signals can also beapplied to digital filtering, but since delayed versions of thesame signal are frequently required in this application, analternative approach8 is to generate all weighted versions ofa signal before delay, rather than all delayed versions beforeweighting. For example, the tree multiplier of Fig. 11generates the 8 d.m. signals possible with respect to 3-bitweighting coefficients. Outputs in Fig. 11 are designated bytheir associated binary weights and negation of anydecoded output can be achieved by logical inversion. Such amultiplier develops all products according to the method ofFig. 4, but a significant reduction in hardware is gained byusing common f.a. and f.f. elements. If JC f.f. are requiredfor unit delay, then an /?-tap nonrecursive filter can beformed by using a total of(R/2)(R — \)xff. to generate allrequired delayed signals from a single-tree multiplier. Thefilter output is then formed by an R-input adder. Becausethis is a 2-level network, the maximum quantisation error isdoubled in comparison with the d.m. mixer of Fig. 10, butit is apparent from Table 2 that for R>2P the number off.a. increases in proportion to R rather that Rp. The treemethod requires a greater number of f.f., but since the unitcost of f.f. can be made significantly less than that of f.a.,this scheme has much to recommend it.

7 Conclusions

A number of modular networks based on f.a. and f.f. havebeen described which perform arithmetic operations withd.m. encoded output and input signals. These networks can

fLJr1000

0-000

0100

MM 11S S S 5 SMMSQ S, S2 53

multiplierelement

(me.)

-0 010

Fig. 10 Signal mixer for four d.m. inputs with 3-bit coefficients Fig. 11 3-bit tree multiplier

242 COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 19 79, Vol. 2, No. 6

be extended in a straightforward manner to cope with alarger number of inputs, to achieve greater processingaccuracy, or may be incorporated as building blocks in moresophisticated signal processors, such as digital filters. Bothparallel and serial forms or a combination of both arepossible and, with hardware multiplexing, ? wide choice ofrealisations becomes available according to the speed/com-plexity tradeoffs operative in a given application.

The approach to design which has been adopted is basedon the simple concept of the digital d.m. encoder, realisedin the basic form of Fig. 2. It becomes unnecessary tofollow Kouvaras8 in formulating a specialised mathematicalapproach since conventional arithmetic operations mayalways be applied to incrementally encoded signals ofwhich d.m. is a special case. Conventional arithmetic pro-cessing followed by digital d.m. encoding therefore providesa general approach which permits the basic design of a d.m.signal processor to be formulated and then examined interms of available technology for simplification and hard-ware economies. The networks listed in Table 2 are theresult of applying this methodology using f.a. and f.f. asunit elements, and it has been shown that in most casesgreater economy in hardware and/or less quantisation errorresult in comparison with Kouvaras networks8 based on thedelta adder.

Statistical aspects of d.m. signal processing have notbeen examined, but advantages are to be gained by recog-nising the statistical properties of the d.m. signals processedin a particular application. For example, in the case of amixer or nonrecursive digital-filter structure, it may beknown that the total incremental input to a final adder isunlikely to rise to the maximum theoretical magnitude.Eliminating the final f.a ./f.f. pair of the output adder willreduce the step height by a factor of 2, thereby increasingthe gain and signal/quantisation-noise ratio, but the

probability of gross error due to violation of the slope-overload constraint of eqn. 1 must be acceptably low. Also,for more sophisticated d.m. processors, theoretically maxi-mum errors are unlikely and statistical estimates of mean-square noise become a more useful index of performance. Ifthe mean-square value of quantisation noise introduced byeach d.m. process within a network is estimated,1 then thenoise performance of the network as a whole may be estab-lished using techniques of linear analysis which are wellknown in the statistical theory of quantisation noise.10- u

8 References

1 STEELE, R.: 'Delta modulation systems' (Pcntcch Press,London,1975)

2 LOCKHART, G.B.: 'Digital encoding and filtering using deltamodulation', Radio & Electron. Eng., 1972,42, pp. 547 551

3 FRANKS, L.E.: 'Hybrid implementation of digital filters',IEEE Circuit Design Conference, London, July 1974

4 PELED, A., and LIU, B.: 'A new approach to the realisation ofnon-recursive digital filter', IEEE Trans., 1973, AU-21, pp.477-484

5 LOCKHART, G.B.: implementation of delta modulators fordigital inputs', ibid., 1974, ASSP-22, pp. 453-456

6 LO CICERO, J.P., SCHILLING, J.L., and GARODNICK, J.,'Direct arithmetic processing of delta modulation encodedsignals', National Telemetry Conference, 1974, pp. 392 397

7 LOCKHART, G.B.: 'A recursive section for filtering delta modu-lated signals', Proceedings of the Florence Conference on digitalsignal processing, 1975, pp. 213-221

8 KOUVARAS, N.: 'Operations on delta-modulated signals andtheir application in the realisation of digital filters', Radio andElectron. Eng., 1978, 48, pp. 431-438

9 LOCKHART, G.B.: 'Design and application of binary sequenceswith optimised lowpass properties', IEE J. Comput. & DigitalTech., 1978, l,pp. 197-204

10 BOGNER, R.E., and CONSTANTINIDES, A.C.: introductionto digital filtering' (Wiley, 1975)

11 RABINER, L.R., and GOLD, B.: 'Theory and application ofdigital signal processing' (Prentice-Hall, 1975)

COMPUTERS AND DIGITAL TECHNIQUES, DECEMBER 1979, Vol. 2, No. 6 243