Modern VLSI Design A S Y S T E M S A P P R O A C H

Wayne Wolf

Prentice-Hall International, Inc.

Table of Contents

Preface xi

Chapter 1 Digital Systems and VLSI 1

1.1 Why build integrated circuits? 1

1.2 Integrated circuit manufacturing 4

1.2.1 Technology 4 1.2.2 Economics 6

1.3 CMOS technology 9

1.4 Design and testability 10

1.5 Integrated circuit design techniques 12 1.5.1 Hierarchical design 13 1.5.2 Design abstraction 15 1.5.3 Computer-aided design 20

1.6 A look ahead 22

1.7 Summary 25

1.8 References 25

1.9 Problems 25

Chapter 2 Fabrication and Layout 27

2.1 Introduction 27

2.2 Components 28 2.2.1 Transistors 29 2.2.2 Wires and vias 34 2.2.3 Parasitic elements 35 2.2.4 Process parameters and variations 39

2.3 Fabrication processes 42 2.3.1 Fabrication steps 42 2.3.2 Tub ties and latchup 46

2.4 Design rules 49 2.4.1 Fabrication errors 49 2.4.2 Scalable design rules 52 2.4.3 SCMOS design rules 54 2.4.4 Technology trends 57

2.5 Layout design and tools 59

2.5.1 Layouts for circuits 59

2.5.2 Stick diagrams 63 2.5.3 Hierarchical stick diagrams 65 2.5.4 Layout design and analysis tools 70 2.5.5 Automatic layout 74

2.6 References 77

2.7 Problems 78

Chapter 3 Combinational Logic 83

3.1 Introduction 83

3.2 Combinational logic functions 83

3.3 Static complementary gates 86

3.3.1 Gate structures 86 3.3.2 Basic gate layouts 91 3.3.3 Simulation 95 3.3.4 Logic levels 99 3.3.5 Delay 102 3.3.6 Power consumption 108 3.3.7 Layout and parasitics 112 3.3.8 Driving large loads 115 3.3.9 Advanced wire delay models 116 3.3.10 Advanced transistor characteristics

3.4 Advanced gate circuits 121

3.4.1 Pseudo-nMOS logic 122 3.4.2 Domino logic 124

3.5 Combinational logic networks 126 3.5.1 Switch logic 126 3.5.2 Combinational network delay 131 3.5.3 Automated logic optimization 138

3.6 Combinational logic testing 138 3.6.1 Gate testing 138 3.6.2 Combinational network testing 141

3.7 References 143

3.8 Problems 144

Chapter 4 Sequential Machines 149

4.1 Introduction 149

4.2 Latches and flip-flops 149 4.2.1 Categories of memory elements 149 4.2.2 Latches 151 4.2.3 Flip-flops 157

4.3 Sequential systems and clocking disciplines 158

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4.3.1 One-phase systems for flip-flops 161 4.3.2 Two-phase systems for latches 161 4.3.3 Clock period 170 4.3.4 Clock generation 171 4.3.5 Advanced performance analysis 172

4.4 Sequential system design 176 4.4.1 Structural specification of sequential machines 176 4.4.2 State transition graphs and tables 178 4.4.3 State assignment 187

4.5 Design validation 193 4.6 Sequential testing 195 4.7 References 203 4.8 Problems 203

Chapter 5 Subsystems 207 5.1 Introduction 207 5.2 Layout design methods 208

5.2.1 Single-row layout design 209 5.2.2 Standard cell layout design 218

5.3 Combinational shifters 221 5.4 Adders 223 5.5 ALUs 228 5.6 Multipliers 231 5.7 High-density memory 239

5.7.1 ROM 241 5.7.2 Static RAM 241 5.7.3 The three-transistor DRAM 245

5.8 Data path design 246 5.9 Programmable logic arrays 249

5.10 References 253 5.11 Problems 253

Chapter 6 Р1ооф1апгпп§ 257 6.1 Introduction 257 6.2 Floorplanning methods 257

6.2.1 Block placement and channel definition 261 6.2.2 Global routing 266 6.2.3 Switchbox routing 268 6.2.4 Power distribution 269

6.2.5 Clock distribution 271 6.2.6 Floorplanning tips 275 6.2.7 Design validation 276

6.3 Off-chip connections 277

6.3.1 Packages 277 6.3.2 The I / O architecture 281 6.3.3 Pad design 282

6.4 References 286

6.5 Problems 287

Chapter 7 Architecture Design 293 7.1 Introduction 293

7.2 Register-transfer design 294 7.2.1 Register-transfer simulation programs 295 7.2.2 Data path-controller architectures 297 7.2.3 ASM chart design 298

7.3 High-level synthesis 307 7.3.1 Functional modeling programs 308 7.3.2 Data 309 7.3.3 Control 320 7.3.4 Data and control 326

7.4 Architecture testing 328

7.5 References 332

7.6 Problems 333

Chapter 8 Chip Design 337

8.1 Introduction 337

8.2 Kitchen timer chip 338

8.2.1 Timer specification and architecture 338 8.2.2 Architecture design 340 8.2.3 Logic and layout design 347 8.2.4 Design validation 353

8.3 PDP-8 data path 356 8.3.1 PDP-8 instruction set 356 8.3.2 Register-transfer design 361 8.3.3 Clocking and bus design 364 8.3.4 Logic and layout design 365

8.4 References 369

8.5 Problems 370

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Chapter 9 Analysis and Synthesis Algorithms 373 9.1 Introduction 373 9.2 CAD systems 374 9.3 Simulation 375

9.3.1 Event-driven simulation 375 9.3.2 Switch simulation 377

9.4 Layout synthesis 379 9.4.1 Placement 380 9.4.2 Global routing 383 9.4.3 Detailed routing 385

9.5 Layout analysis 387 9.6 Timing analysis and optimization 389 9.7 Logic synthesis 394

9.7.1 Technology independent logic optimization 395 9.7.2 Technology-dependent logic optimizations 403

9.8 Test generation 405 9.9 Sequential machine optimizations 408

9.10 Scheduling and binding 409 9.11 References 411 9.12 Problems 412

Appendix A A Chip Designer's Lexicon 417

Appendix В Chip Design Projects 421 B.l Class project ideas 421 B.2 Project proposal and specification 423 B.3 Design plan 424 B.4 Design checkpoints and documentation 427

B.4.1 Subsystems check 427 B.4.2 First layout check 427 B.4.3 Project completion 427

Appendix С Design Modeling 429 C.l Introduction 429 C.2 Hardware modeling in VHDL 429 C.3 Hardware modeling in С 435

C.3.1 Simulator 438 C.3.2 Sample execution 443

References 447

Index 459