Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Topics

Wire and via structures. Wire parasitics. Transistor parasitics.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Wires and vias

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Metal migration

Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit.

Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Metal migration problems and solutions

Marginal wires will fail after a small operating period—infant mortality.

Normal wires must be sized to accommodate maximum current flow:Imax = 1.5 mA/m of metal width.

Mainly applies to VDD/VSS lines.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Diffusion wire capacitance

Capacitances formed by p-n junctions:

n+ (ND)

depletion region

substrate (NA)bottomwallcapacitance

sidewallcapacitances

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Depletion region capacitance

Zero-bias depletion capacitance:– Cj0 = si/xd.

Depletion region width:– xd0 = sqrt[(1/NA + 1/ND)2siVbi/q].

Junction capacitance is function of voltage across junction:– Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Poly/metal wire capacitance

Two components:– parallel plate;– fringe.

plate

fringe

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Metal coupling capacitances

Can couple to adjacent wires on same layer, wires on above/below layers:

metal 2

metal 1 metal 1

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Example: parasitic capacitance measurement

n-diffusion: bottomwall=2 fF, sidewall=2 fF.

metal: plate=0.15 fF, fringe=0.72 fF.

3 m

0.75 m 1 m

1.5 m

2.5 m

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Wire resistance

Resistance of any size square is constant:

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Mean-time-to-failure

MTF for metal wires = time required for 50% of wires to fail.

Depends on current density:– proportional to j-n e Q/kT – j is current density– n is constant between 1 and 3– Q is diffusion activation energy

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Skin effect

At low frequencies, most of copper conductor’s cross section carries current.

As frequency increases, current moves to skin of conductor.– Back EMF induces counter-current in body of

conductor. Skin effect most important at gigahertz

frequencies.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Skin effect, cont’d

Isolated conductor: Conductor and ground:

Low frequency

High frequency

Low frequency

High frequency

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Skin depth

Skin depth is depth at which conductor’s current is reduced to 1/3 = 37% of surface value: = 1/sqrt(f)– f = signal frequency = magnetic permeability = wire conducitvity

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Effect on resistance

Low frequency resistance of wire:– Rdc = 1/ wt

High frequency resistance with skin effect:– Rhf = 1/2 (w + t)

Resistance per unit length:– Rac = sqrt(Rdc 2 + Rhf2

Typically = 1.2.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Transistor gate parasitics

Gate-source/drain overlap capacitance:

gate

source drain

overlap

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Transistor source/drain parasitics

Source/drain have significant capacitance, resistance.

Measured same way as for wires. Source/drain R, C may be included in Spice

model rather than as separate parasitics.