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Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburg Modeling Based Software Testing and Verification Panelists: Fevzi Belli University of Paderborn, Paderborn, Germany Mats Heimdahl University of Minnesota, Minneapolis, USA Ashish Jain Telcordia Technologies, USA T. H. Tse University of Hong Kong, Hong Kong. [Regrets]

Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

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Page 1: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

Moderator: Aditya P. MathurPurdue University, West Lafayette, IN,

USA

Wednesday July 27, 2005. COMPSAC 2005. Edinburgh

Modeling Based Software Testing and Verification

Panelists:

Fevzi BelliUniversity of Paderborn, Paderborn, Germany

Mats HeimdahlUniversity of Minnesota, Minneapolis, USA

Ashish JainTelcordia Technologies, USA

T. H. TseUniversity of Hong Kong, Hong Kong. [Regrets]

Page 2: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

Questions

What is Model based software testing and verification?

What models are used?

Why use models in testing and verification?

Success stories? Failures?

Training needs for incorporating MBSTV?

Research in MBSTV: Future directions?

What tools are available to assist with MBSTV?

Page 3: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

Model-based Testing and Verification

Requirements

Input domain

Model

Test Generation

Verification ofproperties

Application

Tests

Page 4: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

Models

Set Theory/LogicB, Z, VDM, RMSL, ….

Timed Automata, UPPAL, ..

GraphicalFinite State Machine

State charts

Event Sequence Graphs

UML, etc.

CombinatorialOrthogonal arrays

Mixed-level covering arrays…

Page 5: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

Tools

Set Theory/LogicLEIRIOS Test Generator

Graphical(IBM) Rational Rose

Rhapsody (iLogix)

CombinatorialAETG (Telcordia)

TGV (INRIA + partners)

Page 6: Moderator: Aditya P. Mathur Purdue University, West Lafayette, IN, USA Wednesday July 27, 2005. COMPSAC 2005. Edinburgh Modeling Based Software Testing

What next?

Short presentations by panelists and discussion.