Modeling of Heterogeneous Systems in Metropolis

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Modeling of Heterogeneous Systems Modeling of Heterogeneous Systems in Metropolis in Metropolis

Alberto FerrariAlberto Ferrari

[email protected]@parades.rm.cnr.it

ARTISTII – Summer SchoolARTISTII – Summer School

Nässlingen, Sweden – 29Nässlingen, Sweden – 29thth September, 2005 September, 2005

mailto:[email protected]

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Alberto Ferrari – PARADES EEIG

OutlineOutline

Motivation and Industrial LandscapeMotivation and Industrial Landscape

The Metropolis FrameworkThe Metropolis FrameworkArchitectureArchitecture

The Semantics of the Metropolis MetamodelThe Semantics of the Metropolis Metamodel

A Design ExampleA Design ExampleArchitecture Modeling in MetropolisArchitecture Modeling in Metropolis

ConclusionsConclusions

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Product Specification & Architecture Definition(e.g., determination of Protocols and Communication)

System Partitioning and Subsystem Specification Critical Software Development System Integration

Automotive Supply Chain:Automotive Supply Chain:Car ManufacturersCar Manufacturers

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Technical ContentsTechnical Contents

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GM SAC Vehicular Electronics, Controls and GM SAC Vehicular Electronics, Controls and Software StudySoftware Study

Software content in automobiles could increase by 100 X Software content in automobiles could increase by 100 X

over the next 5-6 years. Challenges will include:over the next 5-6 years. Challenges will include:Software system architectureSoftware system architecture

Partitioning for modularity & system reliabilityPartitioning for modularity & system reliability

ReuseReuse

Standardization of interfacesStandardization of interfaces

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Real-Time and DistributedReal-Time and Distributed

Information

SystemsTele

mati

cs

Fail S

top

Body Electronics B

od

yFu

ncti

on

s

Fail S

afe

Fau

lt F

un

cti

on

al

System Electronics

Dri

vin

g a

nd

Veh

icle

Dyn

am

ic F

un

cti

on

s

Mobile Communications Navigation

FireWall

Access to WWWDAB

GateWay

GateWay

Theft warning

Door Module Light Module

AirConditioning

Shift by

Wire

EngineManageme

nt

ABS

Steer by

Wire

Brake by

Wire

MOSTMOSTFirewireFirewire

CANCANLinLin

CANCANTTCANTTCAN

FlexRayFlexRay

Real Tim

eS

oft

Real

Tim

eH

ard

Real

Tim

e

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Putting it all together….CHALLENGE and Putting it all together….CHALLENGE and Opportunity!Opportunity!

We need an integration platform We need an integration platform To deal with heterogeneity:To deal with heterogeneity:

Where we can deal with Hardware and Software (verification and synthesis)Where we can deal with Hardware and Software (verification and synthesis) Where we can mix digital and analogWhere we can mix digital and analog Where we can assemble internal and external IPsWhere we can assemble internal and external IPs Where we can work at different levels of abstractionWhere we can work at different levels of abstraction

To handle the design chainTo handle the design chain

To support integrationTo support integration e.g. tool integratione.g. tool integration e.g. IP integratione.g. IP integration

The integration platform must subsume the traditional design The integration platform must subsume the traditional design

flow, rather than displacing itflow, rather than displacing it

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Metropolis: an Environment for System-Level Metropolis: an Environment for System-Level DesignDesign MotivationMotivation

Design complexity and the need for verification and time-to-market constraints are increasingDesign complexity and the need for verification and time-to-market constraints are increasing

Semantic link between specification and implementation is necessarySemantic link between specification and implementation is necessary

Platform-Based DesignPlatform-Based Design Meet-in-the-middle approachMeet-in-the-middle approach

Separation of concernsSeparation of concerns Function vs. architectureFunction vs. architecture Capability vs. performanceCapability vs. performance Computation vs. communicationComputation vs. communication

Metropolis FrameworkMetropolis Framework Extensible framework providing simulation, verification, and synthesis capabilitiesExtensible framework providing simulation, verification, and synthesis capabilities

Easily extract relevant design information and interface to external toolsEasily extract relevant design information and interface to external tools

Released Sept. 15Released Sept. 15thth, 2004, 2004

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Platform based DesignPlatform based Design

1. A. Ferrari and A. Sangiovanni-Vincentelli. System design: traditional concepts and new paradigms. In Proceedings 1999 IEEE ICCD: VLSI in Computers and Processors, Los Alamitos, CA, USA, October 1999.

2. A. Sangiovanni-Vincentelli, Defining Platform-based Design, EE Design, March 5, 2002.

3. F. Balarin, et al, Metropolis: an Integrated Electronic System Design Environment, IEEE Computer, Vol. 36, No. 4, April, 2003.

PlatformDesign-Space

Export

PlatformMapping

Architectural Space

Application SpaceApplication Instance

Platform Instance

System

Platform (HW and SW)

Platform Based DesignPlatform Based Design11 is composed of three is composed of three aspects:aspects:

1.1. Top Down Application DevelopmentTop Down Application Development2.2. Platform MappingPlatform Mapping3.3. Bottom Up Design Space ExplorationBottom Up Design Space Exploration

Orthogolization of concernsOrthogolization of concerns22

• Functionality and ArchitectureFunctionality and Architecture• Behavior and Performance IndicesBehavior and Performance Indices• Computation, Communication, and Computation, Communication, and

Coordination.Coordination.

http://www-cad.eecs.berkeley.edu/Respep/Research/asves/trade_magazine/ASV_EEdesign02.pdf

http://www-cad.eecs.berkeley.edu/Respep/Research/asves/journal2003/Balarin_ieee_computer03.pdf

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Metropolis Project Big Picture: Target and GoalsMetropolis Project Big Picture: Target and Goals

Target: Embedded System DesignTarget: Embedded System Design Set-top boxes, cellular phones, automotive controllers, …

Heterogeneity: computation: Analog, ASICs, programmable logic, DSPs, ASIPs, processors communication: Buses, cross-bars, cache, DMAs, SDRAM, … coordination: Synchronous, Asynchronous (event driven, time driven)

Goals:Goals: Design methodologies:

abstraction levels: design capture, mathematics for the semantics design tasks: cache size, address map, SW code generation, RTL generation, …

Tool set: synthesis: data transfer scheduling, memory sizing, interface logic, SW/HW

generation, … verification: property checking, static analysis of performance, equivalence checking,

…

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Embedded System Design ProblemEmbedded System Design Problem

HeterogeneityHeterogeneity and and Concurrency Concurrency (both at function and (both at function and

architecture platform level)architecture platform level)

Design ExplorationDesign Exploration at early stages using models at early stages using models

SynthesisSynthesis (correct by construction, push-button system (correct by construction, push-button system

deployment)deployment)

Multiple levels of abstractionMultiple levels of abstraction to go from concept to to go from concept to

implementationimplementation

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Focusing on the PrinciplesFocusing on the Principles Models of computation with formal semanticsModels of computation with formal semantics

Unambiguously capture specification Unambiguously capture specification Enable verification and synthesisEnable verification and synthesis

Unified frameworksUnified frameworks for composition of models for composition of models Orthogonalization of concernsOrthogonalization of concerns

Function/ArchitectureFunction/Architecture Computation/Communication Computation/Communication

Formal methods for Formal methods for abstractionabstraction and and refinementrefinement Help in defining levels of abstractionsHelp in defining levels of abstractions Link design steps (successive refinement)Link design steps (successive refinement) VerificationVerification

Formal definition of Formal definition of mappingmapping to cross levels of abstractions to cross levels of abstractions Synthesis and compilationSynthesis and compilation

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Software Tools SolutionSoftware Tools Solution

Meta model compiler

Verification tool

Synthesis tool

Front end

Meta model language

Simulator tool

...Back end1

Abstract syntax trees

Back end2 Back endNBack end3

Verification tool

• Metropolis Meta Modeling (MMM) language4 and compiler are the core components.

• Backend tools provide various operations for manipulating designs and performing analysis.

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Metropolis ProjectMetropolis ProjectParticipants:

UC Berkeley (USA): methodologies, modeling, formal methods CMU (USA): formal methods Politecnico di Torino (Italy): modeling, formal methods Universita Politecnica de Catalunya (Spain): modeling, formal methods Cadence Berkeley Labs (USA): methodologies, modeling, formal methods PARADES (Italy): methodologies, modeling, formal methods ST (France-Italy): methodologies, modeling Philips (Netherlands): methodologies (multi-media) Nokia (USA, Finland): methodologies (wireless communication) BWRC (USA): methodologies (wireless communication) Magneti-Marelli (Italy): methodologies (power train control) BMW (USA): methodologies (fault-tolerant automotive controls) Intel (USA): methodologies (microprocessors) Cypress (USA): methodologies (network processors, USB platforms) Honeywell (USA): methodologies (FADEC)

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Design Constraints & Assertions

Function

Specification

Architecture (Platform)

Specification

Metropolis FrameworkMetropolis Framework

Metropolis Infrastructure • Design methodology• Meta model of computation• Base tools - Design imports - Meta model compiler - Simulation

Synthesis/Refinement• Compile-time scheduling of

concurrency• Communication-driven hardware

synthesis• Protocol interface generation

Analysis/Verification• Static timing analysis of reactive

systems• Invariant analysis of sequential

programs• Refinement verification• Formal verification of embedded

software

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Meta Frameworks: MetropolisMeta Frameworks: Metropolis

Tagged Signal Semantics

Process Networks Semantics

Firing Semantics

Stateful Firing SemanticsKahn processnetworks

dataflow

discreteevents

synchronous/reactive

hybrid systems

continuoustime

Metropolis provides a process networks abstract semantics and emphasizes formal description of constraints, communication refinement, and joint modeling of applications and architectures.

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Metropolis Objects (partial)Metropolis Objects (partial)

Metropolis elements adhere to a “separation of concerns” point of view.Metropolis elements adhere to a “separation of concerns” point of view.

Proc1P1 P2

I1 I2Media1

Active ObjectsSequential Executing Thread

Passive ObjectsImplement Interface Services

• Processes (Computation)

• Media (Communication)

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A Producer–Consumer ExampleA Producer–Consumer Example

A process P producing integersA process P producing integers

A process C consuming integersA process C consuming integers

A media M implementing the communication services A media M implementing the communication services

Proc P Proc CMedia M

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package producers_consumer;process P { port IntWriter port_wr; public P(String name) {} void thread() { int w = 0; while (w < 30) { port_wr.writeInt(w); w = w + 1; }}}

package producers_consumer;interface IntWriter extends Port{ update void writeInt(int i); eval int nspace();}

Writer: Process P (Producer)Writer: Process P (Producer)

P.mmm: Process behavior definitionP.mmm: Process behavior definition

Proc P

Writer.mmm: Port (interface) definitionWriter.mmm: Port (interface) definition

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package producers_consumer;process C { port IntReader port_rd; public C(String name) { }; void thread() { int r = 0; while (r < 30) { port_rd.readInt();

}}}

Reader.mmm: Port (Interface) definitionReader.mmm: Port (Interface) definition

C.mmm: Process behavior definitionC.mmm: Process behavior definition

package producers_consumer;interface IntReader extends Port{ update int readInt(); eval int num();}

Reader: Process C (Consumer)Reader: Process C (Consumer)

Proc C

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Media M

package producers_consumer;medium IntM implements IntReader, IntWriter, Semaphore { int_infinite_queue storage;

public IntM(String name) { }

public update void writeInt(int w) { await( true; this.Semaphore; this.Semaphore) {

storage.write(w); } } public update int readInt() { int _retval = 0; await( storage.getN()>0; this.Semaphore; this.Semaphore){

_retval = storage.read(); } return _retval; }}

Media M: Writer servicesMedia M: Writer services

Communication definitionCommunication definition

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Example: producers-consumersExample: producers-consumers

A set of processes “Writer” write data to a FIFOA set of processes “Writer” write data to a FIFO

A set of processes “Reader” read data from a FIFO A set of processes “Reader” read data from a FIFO

An unbounded FIFO is used to store written data and to retrieve read dataAn unbounded FIFO is used to store written data and to retrieve read data

Proc P2 Proc CMedia M

Proc P3

Proc P1

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package producers_consumer;

public netlist IwIr { IntM m; public IwIr(String name) { m = new IntM("InstIntM"); addcomponent(m, this, "MEDIUM");

for (int i = 0; i < 3; i++) { P p = new P("Producer"+i); addcomponent(p, this, "Producer"+i); connect(p, port_wr, m); }

for (int i = 0; i < 1; i++) { C c = new C("Consumer"+i); addcomponent(c, this, "Consumer"+i); connect(c, port_rd, m); } }}

Top level netlist Top level netlist

Media M

Proc P2 Proc C

Proc P3

Proc P1

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Protecting against concurrencyProtecting against concurrency

If more than one process is calling the services, the If more than one process is calling the services, the

services can be executed concurrently, hence the state of services can be executed concurrently, hence the state of

the media must be protected by concurrent accessthe media must be protected by concurrent access

The protection is guaranteed by the await statementThe protection is guaranteed by the await statement

Metropolis supports Metropolis supports Concurrency and CoordinationConcurrency and Coordination

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Media M

public update void writeInt(int w) { await { (true; this.Semaphore; this.Semaphore){ storage.write(w); } }

public update int readInt() { int _retval = 0; await( storage.getN()>0; this.Semaphore; this.Semaphore){

_retval = storage.read(); } return _retval; }

}

Media M: awaitMedia M: await


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AWAITAWAIT

The await statement is used to describe a situation that a process The await statement is used to describe a situation that a process

object waits for a given condition to become true, and once the object waits for a given condition to become true, and once the

condition holds, it continues its execution with the guarantee that condition holds, it continues its execution with the guarantee that

the condition still holdsthe condition still holds

await { await { ( guard, testlist, setlist) statements;( guard, testlist, setlist) statements;}}

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AWAITAWAIT

guardguard is an expression to be evaluated as true or false is an expression to be evaluated as true or false

testlisttestlist is a list of elements, where each element is an is a list of elements, where each element is an

interface. Represents the sections to testinterface. Represents the sections to test

setlistsetlist is a list of elements, where each element is an is a list of elements, where each element is an

interface. Represents the section to setinterface. Represents the section to set

The The awaitawait is enabled if its is enabled if its guardguard is true and no actions in is true and no actions in

testlisttestlist are currently being executed. During the execution are currently being executed. During the execution

no action in no action in setlistsetlist can start can start

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Metropolis Objects: adding quantity managersMetropolis Objects: adding quantity managers

Metropolis elements adhere to a “separation of concerns” point of view.Metropolis elements adhere to a “separation of concerns” point of view.

Proc1P1 P2

I1 I2Media1

QM1

Active ObjectsSequential Executing Thread

Passive ObjectsImplement Interface Services

Schedule access to resources and quantities

• Processes (Computation)

• Media (Communication)

• Quantity Managers (Coordination)

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Producer-Consumer Example: Imperative awaitProducer-Consumer Example: Imperative await

…write(d);…

…d = read( );…


…await(…;…;…){ …};…

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Producer-Consumer Example: DeclarativeProducer-Consumer Example: Declarative

…write(d);…

…d = read( );…


(Given an event e, t.e is its tag)

beg(w)

end(w) end(r)

beg(r)

Constraints:

t.beg(w) < t.end(w)

t.beg(r) < t.end(r)

t.beg(w) < t.beg(r) (in case of simultaneous access)

does not exist t such that t.end(w) > t > t.beg(w) (write atomicity)

does not exist t such that t.end(r) > t > t.beg(r) (read atomicity)

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ConstraintsConstraintsTwo mechanisms are supported to specify constraints:

1. Propositions over temporal orders of states execution is a sequence of states specify constraints using linear temporal logic good for scheduling constraints, e.g.

“if process P starts to execute a statement s1, no other process can start the statement until P reaches a statement s2.”

2. Propositions over instances of transitions between states particular transitions in the current execution: called “actions” annotate actions with quantity, such as time, power. specify constraints over actions with respect to the quantities good for real-time constraints, e.g.

“any successive actions of starting a statement s1 by process P must take place with at most 10ms interval.”

B(P1, P1.s1) < B( P2, P2.run); B(P1, P1.s1) < E(P2, P2.run);

B(P1, P1.s2) < B( P2, P2.run); B(P1, P1.s2) < E(P2, P2.run);

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Logic of ConstraintsLogic of Constraints

A transaction-level quantitative constraint language (e.g. latency, throughput)A transaction-level quantitative constraint language (e.g. latency, throughput)

LOC formulas: Boolean expressions over LOC formulas: Boolean expressions over atomic atomic formulas, i.e. combination of formulas, i.e. combination of termsterms using relational operators using relational operators

LOC terms:LOC terms: ConstantsConstants Integer variable i (the ONLY index variable)Integer variable i (the ONLY index variable) Expressions of the form a(e[n]) whereExpressions of the form a(e[n]) where

nn∈I∈I: index expression, e.g. [2], [i+3]: index expression, e.g. [2], [i+3] Index variable i, the only variable in a formula, e.g. “Display[i-5]” and “Stimuli[i]”Index variable i, the only variable in a formula, e.g. “Display[i-5]” and “Stimuli[i]” e: event name, e.g. “in”, “out”, “Stimuli” or “Display” e: event name, e.g. “in”, “out”, “Stimuli” or “Display” e[n]: instances of events, e.g. “in[2]”, e[n]: instances of events, e.g. “in[2]”,

“Stimuli[0]”, “Display[10]”“Stimuli[0]”, “Display[10]” a: annotation, e.g. “t(Display[5])” a: annotation, e.g. “t(Display[5])”

Combination of the terms above using arithmetic operatorsCombination of the terms above using arithmetic operators Boolean operators: (not), (or), (and) and (imply)Boolean operators: (not), (or), (and) and (imply)

Interpreted over a sequence of events in an execution traceInterpreted over a sequence of events in an execution trace Violated if it evaluates to FALSE for some value of iViolated if it evaluates to FALSE for some value of i

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Throughput: “at least 3 Display events will be produced in any period of 30 time units”.

t (Display[i+3]) – t (Display[i]) <= 30

StimuliFSM

Datapath

FIR

Display

( SystemC2.0 Distribution )

Stimuli : 0 at time 9Display : 0 at time 13Stimuli : 1 at time 19Display : -6 at time 23Stimuli : 2 at time 29Display : -16 at time 33Stimuli : 3 at time 39Display : -13 at time 43 Stimuli : 4 at time 49Display : 6 at time 53

FIR Trace

Examples of LOC ConstraintsExamples of LOC Constraints

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Examples LOC Constraints (cont’d)Examples LOC Constraints (cont’d)

Performance constraints:Rate, e.g. “Display’s are produced every 10 time units”,

t(Display[i+1]) - t(Display[i]) == 10

Latency, e.g. “Display is generated no more than 25 time units after Stimuli”,

t(Display[i]) - t(Stimuli[i]) <= 25

Jitter, e.g. “every Display is no more than 4 time units away from the corresponding tick of the real-time clock with period 10”,

| t(Display[i]) - (i+1) * 10 | <= 4

Functional Constraints:Data consistency, e.g. data(input[i]) = data(output[i])

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Examples LOC Constraints (cont’d)Examples LOC Constraints (cont’d)

Latency, e.g. “Display is generated no more than 25 time units after Stimuli”,

t(Display[i]) - t(Stimuli[i]) <= 25

What if not every stimulus is displayed?

t(Display[i]) - t(Stimuli[cause(Display[i])) <= 25

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Some Remarks on LOC FormulasSome Remarks on LOC Formulas

Time is only one of the possible annotations Time is only one of the possible annotations cause(Display[i]), data(input[i]), power(…), area(…), etc.

Annotations must be provided by the designer, the program, the Annotations must be provided by the designer, the program, the

simulator, the underlying platformsimulator, the underlying platform

Annotations need not be definedAnnotations need not be defined e.g. performance requirements are specified early in the design process but e.g. performance requirements are specified early in the design process but

can be evaluated much latercan be evaluated much later A third logic value A third logic value undefundef is introduced to deal with undefined annotations is introduced to deal with undefined annotations

Indexes of instance of the same event denote their strict order in the Indexes of instance of the same event denote their strict order in the

execution traceexecution trace

Instances of different events have no implied relationshipInstances of different events have no implied relationship

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Producer-Consumer Example: Imperative with QMProducer-Consumer Example: Imperative with QM


Quantity Manager (Scheduler)

Scheduled Netlist

Scheduling Netlist QM

…Lw: {@ write(d) {$

//request code $} @}

…Lr: {@ d = read() {$

//request code $} @}

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Producer-Consumer Example: Semantic (intuitive)Producer-Consumer Example: Semantic (intuitive)



Scheduled Netlist


//Statemedium request functionvoid request(e,rc) { to_qm.request(e,rc); }

request(e,rc)

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Quantity resolutionQuantity resolutionThe 2-step approach to resolve quantities at each state of a netlist being executed:The 2-step approach to resolve quantities at each state of a netlist being executed:

1. 1. quantity requestsquantity requests

for each process for each process PiPi, for each event , for each event ee that that PiPi cancan take, find all the quantity constraints on take, find all the quantity constraints on ee..

In the meta-model, this is done by explicitly requesting quantity annotations at the relevant events, i.e. In the meta-model, this is done by explicitly requesting quantity annotations at the relevant events, i.e.

Quantity.request(event, requested quantities).Quantity.request(event, requested quantities).

2. 2. quantity resolutionquantity resolution

find a vector made of the candidate events and a set of quantities annotated with each of the events, such find a vector made of the candidate events and a set of quantities annotated with each of the events, such

that the annotated quantities satisfy:that the annotated quantities satisfy:

all the quantity requests, andall the quantity requests, and

all the axioms of the Quantity types.all the axioms of the Quantity types.

In the meta-model, this is done by letting each Quantity type implement a resolve() method, and the In the meta-model, this is done by letting each Quantity type implement a resolve() method, and the

methods of relevant Quantity types are iteratively called.methods of relevant Quantity types are iteratively called.

theory of fixed-point computationtheory of fixed-point computation

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Scheduled Netlist


//QM request functionvoid request(e,rc) { pending.add(new r(e,rc)); }

request(e,rc)

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Scheduled Netlist


//Top level resolve function is //invokedvoid resolve() { qm.resolve( ); }

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Scheduled Netlist


//QM resolve functionvoid resolve() { //pick one event per process}

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Scheduled Netlist


//Top level postcondvoid postcond() { qm.postcond( ); }

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Scheduled Netlist


//QM postcondvoid postcond() { //enable/disable events on processes }

setMustDo(e)

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Quantity resolutionQuantity resolution

The 2-step approach is same as how schedulers work, e.g. OS schedulers, BUS The 2-step approach is same as how schedulers work, e.g. OS schedulers, BUS

schedulers, BUS bridge controllers.schedulers, BUS bridge controllers.

Semantically, a scheduler can be considered as one that resolves a quantity called Semantically, a scheduler can be considered as one that resolves a quantity called

execution index.execution index.

Two ways to model schedulers: Two ways to model schedulers:

1. As processes: 1. As processes: explicitly model the scheduling protocols using the meta-model building blocksexplicitly model the scheduling protocols using the meta-model building blocks a good reflection of actual implementationsa good reflection of actual implementations

2. As quantities:2. As quantities: use the built-in request/resolve approach for modeling the scheduling protocolsuse the built-in request/resolve approach for modeling the scheduling protocols more focus on resolution (scheduling) algorithms, than protocols: suitable for higher more focus on resolution (scheduling) algorithms, than protocols: suitable for higher

level abstraction modelslevel abstraction models

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Producer-Consumer ExampleProducer-Consumer Example

…write(d);…

…d = read( );…


…await(…;…;…){ …};…

Metropolis supports Metropolis supports Declarative Coordination Declarative Coordination

(Constraints on Quantities)(Constraints on Quantities)

Metropolis supports Metropolis supports Imperative CoordinationImperative Coordination

(await or QM request)(await or QM request)

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Metropolis Netlists and EventsMetropolis Netlists and Events

Proc1

P1

Media1 QM1

Scheduled Netlist Scheduling Netlist

GlobalTime

Metropolis Architectures are created via two netlists:• Scheduled – generate events1 for services in the scheduled netlist.• Scheduling – allow these events access to the services and annotate events with quantities.

I1

I2

Proc2

P2

Event1 – represents a transition in the action automata of an object. Can be annotated with any number of quantities. This allows performance estimation.

Related Work

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Key Modeling ConceptsKey Modeling Concepts

An An eventevent is the fundamental concept in the framework is the fundamental concept in the frameworkRepresents a transition in the Represents a transition in the action automataaction automata of an objectof an objectAn event is owned by the object that exports itAn event is owned by the object that exports itDuring simulation, generated events are termed as During simulation, generated events are termed as event event

instancesinstances Events can be annotated with any number of quantitiesEvents can be annotated with any number of quantitiesEvents can partially expose the state around them, constraints Events can partially expose the state around them, constraints

can then reference or influence this statecan then reference or influence this state

A A serviceservice corresponds to a set of corresponds to a set of sequences of eventssequences of eventsAll elements in the set have a common begin event and a All elements in the set have a common begin event and a

common end eventcommon end eventA service may be parameterized with argumentsA service may be parameterized with arguments

1. E. Lee and A. Sangiovanni-Vincentelli, A Unified Framework for Comparing Models of Computation, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol. 17, N. 12, pg. 1217-1229, December 1998

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Action AutomataAction Automata

Processes take Processes take actionsactions.. statements and some expressions, e.g.statements and some expressions, e.g.

y = z+port.f();, z+port.f(), port.f(), i < 10, …y = z+port.f();, z+port.f(), port.f(), i < 10, … only calls to media functions are only calls to media functions are observable actionsobservable actions

An An executionexecution of a given netlist is a sequence of vectors of of a given netlist is a sequence of vectors of eventsevents.. event event : the beginning of an action, e.g. : the beginning of an action, e.g. B(B(port.f()port.f())), ,

the end of an action, e.g. the end of an action, e.g. E(E(port.f()port.f())), or null , or null NN the the ii-th component of a vector is an event of the -th component of a vector is an event of the ii-th process-th process

An execution is An execution is legallegal if if it satisfies all coordination constraints, andit satisfies all coordination constraints, and it is accepted by all action automata.it is accepted by all action automata.

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Execution semanticsExecution semantics

Action automaton:Action automaton:one for each action of each processone for each action of each process

defines the set of sequences of events that can happen in executing the actiondefines the set of sequences of events that can happen in executing the action

a transition corresponds to an event:a transition corresponds to an event: it may update shared memory variables:it may update shared memory variables:

process and media member variables values of actions-expressions

it may have guards that depend on states of other action automata and it may have guards that depend on states of other action automata and memory variablesmemory variables

each state has a self-loop transition with the null each state has a self-loop transition with the null NN event. event.

all the automata have their alphabets in common:all the automata have their alphabets in common: transitions must be taken together in different automata, if they correspond to transitions must be taken together in different automata, if they correspond to

the same event.the same event.

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Action AutomataAction Automata

Return

B y=x+1 B x+1 E x+1 E y=x+1y:=Vx+1

B x+1 E x+1 E y=x+1y:=any

* = write y* * *

B x+1 E x+1Vx+1 :=x+1

E x+1Vx+1 :=any

write x

y=x+

1

x+1

y=x+1;y=x+1;

000

B y=x+1 B x+1 E x+1NN N E y=x+1

500

550

100

110

Vx+1yx

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Semantics summarySemantics summary

Processes run sequential code concurrently, each at its own Processes run sequential code concurrently, each at its own

arbitrary pace.arbitrary pace.

Read-Write and Write-Write hazards may cause unpredictable resultsRead-Write and Write-Write hazards may cause unpredictable results atomicity has to be explicitly specified.atomicity has to be explicitly specified.

Progress may block at synchronization pointsProgress may block at synchronization points awaitsawaits function calls and labels to which awaits or constraints refer. function calls and labels to which awaits or constraints refer.

The legal behavior of a netlist is given by a set of sequences of event The legal behavior of a netlist is given by a set of sequences of event

vectors.vectors. multiple sequences reflect the non-determinism of the semantics:multiple sequences reflect the non-determinism of the semantics: concurrency, synchronization (awaits and constraints)concurrency, synchronization (awaits and constraints)

Metropolis Meta ModelMetropolis Meta ModelThe behavior of a concurrent system:

communication

• state• methods to

- store data

- retrieve data

coordination

• constraints on concurrent actions

• algorithms to enforce the constraints

computation

• f: X Z

• firing rule

process medium q-manager (scheduler)

process P1{

port pX, pZ;

thread(){

// condition to read X

// an algorithm for f(X)

// condition to write Z

}

}

medium M{ int[] storage; int space;

void write(int[] z){ ... }

int[] read(){ ... }

}

P1 P2M

S

P1.pZ.write() < P2.pX.read()

pX pZ pX pZ

M’ M’

Metropolis Meta ModelMetropolis Meta Model

Do not commit to the semantics of a particular Model of Computation (MoC)

Define a set of “building blocks”: specifications with many useful MoCs can be described using the building blocks.

unambiguous semantics for each building block.

syntax for each building block a language of the meta model.

Represent behavior at all design phases; mapped or unmapped

Question: What is a good set of building blocks?

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Metropolis Driver: Picture-in-Picture Design Metropolis Driver: Picture-in-Picture Design ExerciseExercise

Evaluate the methodology with formal techniques applied.

• Function– Input: a transport stream for multi-channel video images

– Output: a PiP video stream

- the inner window size and frame color dynamically changeable

DEMUX PARSER

JUGGLER

MPEG RESIZE

MPEG

PIP

USRCONTROL

60 processes with 200 channels

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MyFncNetlist

Meta-model : function netlistMeta-model : function netlist

process P{

port reader X;

port writer Y;

thread(){

while(true){

...

z = f(X.read());

Y.write(z);

}}}

medium M implements reader, writer{

int storage;

int n, space;

void write(int z){

await(space>0; this.writer ; this.writer)

n=1; space=0; storage=z;

}

word read(){ ... }

}

interface reader extends Port{

update int read();

eval int n();

}

interface writer extends Port{

update void write(int i);

eval int space();

}

MP1X Y P2X Y

Env1 Env2

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Multi-Media System: Abstraction LevelsMulti-Media System: Abstraction Levels

DMA

DSP

RAMs RAMd

$

CPU$ $

HW

HWMemFMemS

$

DSP

CPU

HW

HW

• Network of processes with sequential program for each

• Unbounded FIFOs with multi-rate read and write

•Communication refined to bounded FIFOs and shared memories with finer primitives (called TTL API):

allocate/release space, move data, probe space/data

• Mapped to resources with coarse service APIs

• Services annotated with performance models

• Interfaces to match the TTL API

• Cycle-accurate services and performance models

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package producers_consumer;medium IntM implements IntReader, IntWriter, Semaphore { int[] storage; int reading, writing, space, n, length;

public IntM(String name, int nelement) { space = length = nelement; storage = new int[nelement]; reading = writing = n = 0; }

public update void writeInt(int w) { await{ (space > 0; this.Semaphore, this.Semaphore) { space --; n++; storage[writing++] = w; if (writing == length) writing = 0; }}}



Media Mfinite

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public update int readInt() { int _retval = 0; await(n>0; this.Semaphore; this.Semaphore){ n--, space++;

_retval = storage[reading++]; if (reading == length) reading = 0; } return _retval; } public eval int nspace() { await(true; this.Semaphore; this.Semaphore){ return space; }} public eval int num() { await(true; this.Semaphore; this.Semaphore){ return n; }}



Media Mfinite

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Binding Adjacent Levels of AbstractionBinding Adjacent Levels of Abstraction

Y2T

write()Th,Wk

T2Y

read()

• Implement the upper level services using the current services

: refinement relation

• Metropolis represent both levels of abstraction explicitly, rather than replacing the upper level.

- essential for specifying the refinement relation.

• Refinement relation is associated with properties to preserve through the refinement.

- the properties can be formally specified, and verified either formally or through simulation.

Writer process Reader process

write(), read()

Example: a unbounded FIFO v.s. a bounded FIFO with the finer service.

Unbounded FIFO Level

• Bounded FIFO API, e.g. release space, move data

• FIFO width and length parameterized

Bounded FIFO Level

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Task Transaction Level (TTL) RefinementTask Transaction Level (TTL) Refinement

ttlmedium

Yapi2TTL TTL2Yapi

rdwrth

Producer Consumer

write(data,10)

readth()

claim_space()

release_data(chunk)

read(data,10)

readth()

claim_data()

release_space(chunk)

writeth() writeth()

claim_space()

readth()

release_data(chunk)

writeth()

claim_data()

readth()

release_space(chunk)

writeth()

ttlrefyapi

yapiprocess yapiprocess

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TTL Netlist RefinementTTL Netlist Refinement

package metamodel.plt.TTL;

import metamodel.plt.yapi.*;

public netlist TTLmediumnetlist {

boundedfifo bf; rdwrthreshold rwtr; yapichannel channel; yapi2TTLchannel y2bf; TTL2yapichannel bf2y;

public TTLmediumnetlist(String n,yapichannel ch, int ts,int nt,int it,stfunc f) {

super(n);channel = ch;y2bf = new yapi2TTLchannel(n+"y2bf",ts,nt,f);bf2y = new TTL2yapichannel(n+"bf2y",ts,nt,f);

rwtr = new rdwrthreshold(n+"rdwrth");

bf = new boundedfifo(n+"bf",ts,nt,it, 1); // default width//addcomponent and connect statements follow

…}

Y2T

write()Th,Wk

T2Y

read()

Yapi channel to be refined

Objects are create and connected

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TTL Netlist RefinementTTL Netlist Refinement

package metamodel.plt.TTL;

import metamodel.plt.yapi.*;

public netlist TTLmediumnetlist { … public TTLmediumnetlist(String n,yapichannel ch, int ts,int nt,int it,stfunc f) {

…refine(ch,this);refineconnect(this, getnthconnectionsrc(ch,yapioutinterface,0),

getnthconnectionport(ch,yapioutinterface,0), y2bf);

refineconnect(this, getnthconnectionsrc(ch,yapiininterface,0), getnthconnectionport(ch,yapiininterface,0), bf2y);…}

Y2T

write()Th,Wk

T2Y

read()

1

1

22

3

3

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Refinement VerificationRefinement Verification

Two properties checked for the refinement:

1. Deadlock

2. Data consistency:

Always: forall i: Writer.data[i] = Reader.data[i];

Both were verified for the refined protocol:

1. Automatically applied SPIN in Metropolis:

• Translate the protocol description to SPIN

• Found a deadlock in the original algorithm provided by Philips

2. Automatically applied LoC Monitor in Metropolis

• Translate the property formula to executable code (simulation monitor)

• Simulate the monitor together with the original processes and refined protocol

• Found two bugs in the protocol description (a piece of the writer's data was conditionally ignored in the reader's side).

Y2T

write()Th,Wk

T2Y

read()

Writer

process

Reader

process

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Architecture ExplorationArchitecture Exploration

DSP

CPU

HW

HW

• Configure the resources, e.g. the size of an internal memory, width of a bus.

• Bind the processes to the resources.

• Compose the resource services, e.g. schedules of data transfers, compilation of basic blocks.

Once done, performance analysis and simulation can be carried out, using the performance models associated with the resource services.

But, to do so, we need models for the resources: services and performance.

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Resource ModelingResource ModelingWhat to model/abstract depends on what you are concerned about.

DSP

CPU

HW

HW

Example:

• Where should my data be located?

• When should my data be transferred?

• How often do my peripherals generate interrupts?

These all influence my decisions on sizes of internal memories, bus configuration, data transfer schedules.

Resource models based on these concerns:

• Memory: internal (single-access, dual-access), external

• DSP: bus read/write(), check/serve_Interrupt(), execute()

performance: latency per byte transfer

• DMA control, CPU: similar

• peripheral: non-deterministic interrupt generator

could be restricted wrt supported behavior (under development)

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Architecture ExplorationArchitecture Exploration

DSP

CPU

HW

HW

• Configure the resources, e.g. the size of an internal memory, width of a bus.

• Bind the processes to the resources.

• Compose the resource services, e.g. schedules of data transfers, compilation of basic blocks.

Performance analysis and simulation can be carried out, using the performance models associated with the resource services.

Effective scheduling of process operations mapped to a CPU is a key issue:

• reduce the context-switching between tasks for efficient execution

• increase data coherency among processes for efficient memory usage

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Architecture componentsArchitecture componentsAn architecture component specifies services, i.e.

• what it can do

• how much it costs : quantities, annotation, logic of constraints

: interfaces, implementation

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A Simple Architecture ModelA Simple Architecture Model

Task1

P1

Cpu1 RTOS1


GlobalTime

RtosIf

BusPort

Task2

P2

Bus1

SlavePort

Cpu2

RtosIf

MasterIf

BusPort

MasterIf

RTOS2

Arbiter

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Meta-model: architecture componentsMeta-model: architecture componentsAn architecture component specifies services, i.e.

• what it can do:

• how much it costs:

medium Bus implements BusMasterService …{

port BusArbiterService Arb;

port MemService Mem; …

update void busRead(String dest, int size) {

if(dest== … ) Mem.memRead(size);

}

…

interface BusMasterService extends Port {

update void busRead(String dest, int size);

update void busWrite(String dest, int size);

}

interfaces, methods, coordination (awaits, constraints), netlists

quantities, annotated with events, related over a set of events

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Meta-model: quantitiesMeta-model: quantities• The domain D of the quantity, e.g. real for the global time,

• The operations and relations on D, e.g. subtraction, <, =,

• The function from an event instance to an element of D,

• Axioms on the quantity, e.g.

the global time is non-decreasing in a sequence of vectors of any

feasible execution.class GTime extends Quantity {class GTime extends Quantity { double t;double t; double sub(double t2, double t1){...}double sub(double t2, double t1){...} double add(double t1, double t2){…}double add(double t1, double t2){…} boolean equal(double t1, double t2){ ... }boolean equal(double t1, double t2){ ... } boolean less(double t1, double t2){ ... }boolean less(double t1, double t2){ ... } double A(event e, int i){ ... }double A(event e, int i){ ... } constraints{constraints{ forall(event e1, event e2, int i, int j):forall(event e1, event e2, int i, int j): GXI.A(e1, i) == GXI.A(e2, j) -> equal(A(e1, i), A(e2, j)) &&GXI.A(e1, i) == GXI.A(e2, j) -> equal(A(e1, i), A(e2, j)) && GXI.A(e1, i) < GXI.A(e2, j) -> (less(A(e1, i), A(e2, j)) || equal(A(e1, i), A(e2. j)));GXI.A(e1, i) < GXI.A(e2, j) -> (less(A(e1, i), A(e2, j)) || equal(A(e1, i), A(e2. j)));}}}}

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Meta-model: architecture componentsMeta-model: architecture components

This modeling mechanism is generic, independent of services and cost specified.This modeling mechanism is generic, independent of services and cost specified.

Which levels of abstraction, what kind of quantities, what kind of cost constraints should be Which levels of abstraction, what kind of quantities, what kind of cost constraints should be

used to capture architecture components?used to capture architecture components? depends on applications: depends on applications: on-going researchon-going research

Transaction: Services:

- fuzzy instruction set for SW, execute() for HW

- bounded FIFO (point-to-point)

Quantities:

- #reads, #writes, token size, context switches

Physical:

Services: full characterization

Quantities: time

CPU ASIC2ASIC1

Sw1 HwSw2

Sw I/F Channel I/F

Wrappers

Hw

Bus I/F

C-Ctl Channel Ctl

B-I/FCPU-IOs

e.g. PIBus 32b

e.g. OtherBus 64b...

C-Ctl

RTOS

Virtual BUS: Services:

- data decomposition/composition

- address (internal v.s. external)

Quantities: same as above, different weights

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CPU MediaCPU Media

Cpu

interface CPUServices extends Port {

update void cpuExec(int ClockClycles); update void cpuWrite(int target, int addr, int[] data); update void cpuRead(int target, int addr, int[] data);}

medium CPU implements CPUServices {

port BusMaster Master;

update void cpuExec(int ClockCycles) {

// exclusive usage and backannotation of ClockCycles delay

} update void cpuRead(…) { … Master.Read(); … } update void cpuWrite(…) { … Master.Write(); … } }

}

BusMaster port

CPU port

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CPU MediaCPU Media

Cpu





port Scheduler S;

update void cpuExec(int ClockCycles) {

{$ // request exclusive access to CPU for ClockCycles delay

beg{ S.request(B(thisthread, this.cpuExec)); }

end{ S.request(B(thisthread, this.cpuExec), ClockCycles, Release );}

$}

} update void cpuRead(…) { … Master.Read(); … } update void cpuWrite(…) { … Master.Write(); … } }

}

Scheduler port

BusMaster port

CPU port

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CPU MediaCPU Media

Cpu





port Scheduler S;

update void cpuExec(int ClockCycles) { {$ … $} } update void cpuRead(…) { block(R1) { // request exclusive access to CPU for RWCycles delay

beg{ S.request(B(thisthread, this.cpuExec)); }

end{ S.request(B(thisthread, this.cpuExec), RCycles);

}

Master.readSlave(…);

block(R2) {end{ S.request(B(thisthread, this.cpuExec), Release );}

}

update void cpuWrite(…) { … Master.writeSlave(); … }

}

Scheduler port

BusMaster port

CPU port

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Bus ModelBus Model

medium Bus implements BusMasterService …{

port BusArbiterService Arb; port MemService Mem;

update void busRead(String dest, int size) {

if(dest== … ) Mem.memRead(size);

{$ Arb.request(B(thisthread, this.busRead));

GTime.request(B(thisthread, this.memRead), BUSCLKCYCLE + GTime.A(B(thisthread,

this.busRead)));

$}

}

scheduler BusArbiter extends Quantity

implements BusArbiterService {

update void request(event e){ … }

update void resolve() { //schedule }

}

interface BusMasterService extends Port {

update void busRead(String dest, int size);

update void busWrite(String dest, int size);

}

interface BusArbiterService extends Port {

update void request(event e);

update void resolve();

}

BusArbiterBus

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MyArchNetlist

Meta-model: architecture netlist Meta-model: architecture netlist

Bus

ArbiterBus

Mem

Cpu OsSched

…

…

…

Master

CPU + OS

Slave

Mem

Arbiter

Architecture netlist specifies configurations of architecture components.

Each constructor

- instantiates arch. components,

- connects them,

- takes as input mapping processes.

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Meta-model: mapping processesMeta-model: mapping processes

process MapP{

port CpuService Cpu;

void readCpu(){

Cpu.exec(); Cpu.cpuRead();

}

void mapf(){ …} …

}

thread(){

while(true){

await {

(true; ; ;) readCpu();

(true; ; ;) mapf();

(true; ; ;) readWrite();

}}}

Mapping process

…

…

…

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PiP Architecture PiP Architecture

Bus

Mem

Scheduled Netlist

Task1 TaskN

MemScheduler

CPU RTOS

BusScheduler

CpuScheduler

GlobalTime

Scheduling Netlist

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Meta-model: mapping processesMeta-model: mapping processes

process P{

port reader X;

port writer Y;

thread(){

while(true){

...

z = f(X.read());

Y.write(z);

}}}

process MapP{

port CpuService Cpu;

void readCpu(){

Cpu.exec(); Cpu.cpuRead();

}

void mapf(){ …} …

}

thread(){

while(true){

await {

(true; ; ;) readCpu();

(true; ; ;) mapf();

(true; ; ;) readWrite();

}}}

B(P, X.read) <=> B(MapP, readCpu); E(P, X.read) <=> E(MapP, readCpu);

B(P, f) <=> B(MapP, mapf); E(P, f) <=> E(MapP, mapf);…

Function process Mapping process

MyFncNetlist

MP C

Env1 Env2

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Meta-model: mapping netlistMeta-model: mapping netlist

Bus

ArbiterBus

Mem

Cpu OsSched

MyArchNetlist

mP1 mP2mP1 mP2

MyFncNetlist

MP1 P2

Env1 Env2

B(P1, M.write) <=> B(mP1, mP1.writeCpu); E(P1, M.write) <=> E(mP1, mP1.writeCpu);

B(P1, P1.f) <=> B(mP1, mP1.mapf); E(P1, P1.f) <=> E(mP1, mP1.mapf);

B(P2, M.read) <=> B(P2, mP2.readCpu); E(P2, M.read) <=> E(mP2, mP2.readCpu);

B(P2, P2.f) <=> B(mP2, mP2.mapf); E(P2, P2.f) <=> E(mP2, mP2.mapf);

MyMapNetlist

Bus

ArbiterBus

Mem

Cpu OsSched

MyArchNetlist…

……

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Meta-model: platformsMeta-model: platformsinterface MyService extends Port { int myService(int d); }

medium AbsM implements MyService{ int myService(int d) { … }}

B(thisthread, AbsM.myService) <=> B(P1, M.read);

E(thisthread, AbsM.myService) <=> E(P2, M.write);refine(AbsM, MyMapNetlist);

MyArchNetlistMyFncNetlist MP1 P2

B(P1, M.write) <=> B(mP1, mP1.writeCpu); B(P1, P1.f) <=> B(mP1, mP1.mapf); E(P1, P1.f) <=> E(mP1, )B(P2, M.read) <=> B(P2, mP2.readCpu); E(P2, P2.f) <=> E(mP2, mP2.mapf);

MyMapNetlist1



MyMapNetlist1

B(…) <=> B(…);

E(…) <=> E(…);refine(AbsM, MyMapNetlist1)

MyArchNetlistMyFncNetlist

MP1 P2


MyMapNetlist2

M

B(…) <=> B(…);

E(…) <=> E(…);

refine(AbsM, MyMapNetlist2)

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Meta-model: platformsMeta-model: platforms

interface MyService extends Port { int myService(int d); }

medium AbsM implements MyService{ int myService(int d) { … }}

B(thisthread, AbsM.myService) <=> B(P1, M.read);

E(thisthread, AbsM.myService) <=> E(P2, M.write);refine(AbsM, MyMapNetlist);



MyMapNetlist1



MyMapNetlist1

B(…) <=> B(…);

E(…) <=> E(…);refine(AbsM, MyMapNetlist1)

MyArchNetlistMyFncNetlist

MP1 P2


MyMapNetlist2

M

B(…) <=> B(…);

E(…) <=> E(…);

refine(AbsM, MyMapNetlist2)

A set of mapping netlists, together with constraints on event relations to a given interface implementation, constitutes a platform of the interface.

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Meta-model: recursive paradigm of platformsMeta-model: recursive paradigm of platforms

S

N N'

B(Q2, S.cdx) <=> B(Q2, mQ2.excCpu); E(Q2, M.cdx) <=> E(mQ2, mQ2.excCpu);

B(Q2, Q2.f) <=> B(mQ2, mQ2.mapf); E(Q2, P2.f) <=> E(mQ2, mQ2.mapf);



MyMapNetlist1

MyArchNetlist

MyFncNetlist

MP1 P2B(P2, M.read) <=> B(P2, mP2.readCpu); E(P2, P2.f) <=> E(mP2, mP2.mapf);

M

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A Simple Architecture ModelA Simple Architecture Model

Task1

P1

Cpu1 RTOS1


GlobalTime

RtosIf

BusPort

Task2

P2

Bus1

SlavePort

Cpu2

RtosIf

MasterIf

BusPort

MasterIf

RTOS2

Arbiter

Metropolis supports Metropolis supports Hardware/Software Hardware/Software

modeling modeling

Metropolis supports Hierarchical Metropolis supports Hierarchical Composition of ServicesComposition of Services

(Platforms)(Platforms)

Proc P2 Proc CMedia M

Proc P3

Proc P1

B(P1, M.write) <=> B(mP1, mP1.writeCpu); E(P1, M.write) <=> E(mP1, mP1.writeCpu);

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Injection

Locking Pll

Ctrl

Analog

Digital (FSM)

Hybrid Modeling in MetropolisHybrid Modeling in Metropolisblackbox(SystemCSim)%% setnewinputsample(f,t,e); newsample = integrate(); rt = newsample[1]; re = newsample[0];%%

f: desired frequencyt: final integration timee: error threshold rt: current analog block timere: error

GlobalTime Annotates time

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TRYLOCKING LOCKING

MAYBE LOCKED

Injection Locking PLL Control ExampleInjection Locking PLL Control Example

analog

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TRY TO LOCK 0LOCKING 5.34303e-08TRY TO LOCK 5.54873e-08LOCKING 1.08918e-07LOCKING 1.61311e-07TRY TO LOCK 1.61317e-07LOCKING 2.14747e-07LOCKING 2.67354e-07TRY TO LOCK 2.6736e-07LOCKING 3.2079e-07MAYBE LOCKED 3.47505e-07TRY TO LOCK 3.73173e-07LOCKING 4.26603e-07MAYBE LOCKED 4.53318e-07LOCKED! Go Bears! 4.72774e-06

Simulation ResultsSimulation Results

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Metropolis design environmentMetropolis design environment

Meta model compiler

Verification tool

Synthesis tool

Front end

Meta model language

Simulator tool

...Back end1

Abstract syntax trees

Back end2 Back endNBack end3

Metropolisinteractive

Shell

•Load designs

•Browse designs

•Relate designs

refine, map etc

•Invoke tools

•Analyze results

Verification tool

Functional Spec

Communication SpecConstraints

Architecture

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Backend Point ToolsBackend Point Tools

Synthesis/refinement:Synthesis/refinement: Quasi-static schedulingQuasi-static scheduling Scheduler synthesis from constraint formulasScheduler synthesis from constraint formulas Interface synthesisInterface synthesis Refinement (mapping) synthesisRefinement (mapping) synthesis Architecture-specific synthesis from concurrent processes for:Architecture-specific synthesis from concurrent processes for:

Hardware (with known architecture)Hardware (with known architecture) Dynamically reconfigurable logicDynamically reconfigurable logic

Verification/analysis:Verification/analysis: Static timing analysis for reactive processesStatic timing analysis for reactive processes Invariant analysis of sequential programsInvariant analysis of sequential programs Refinement verificationRefinement verification Formal verification for softwareFormal verification for software

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Metropolis SummaryMetropolis Summary

Concurrent specification with a formal execution semantics Feasible executions of a netlist: sequences of event vectors Quantities can be defined and annotated with events, e.g.

time, power, global indices, composite quantities.

Concurrent events can be coordinated in terms of quantities: logic can be used to define the coordination, algorithms can be used to implement the coordination.

The mechanism of event coordination wrt quantities plays a key role: architecture modeling as service with cost, a mapping coordinates executions of function and architecture netlists, a refinement through event coordination provides a platform.

Metropolis design environment: meta-model compiler to provide an API to browse designs, backend tools to analyze designs and produce appropriate models.

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AcknowledgmentsAcknowledgments

PARADES EEIG: PARADES EEIG: Prof. A.S.VincentelliProf. A.S.Vincentelli

L.Mangeruca, M.BaleaniL.Mangeruca, M.Baleani

UCB: Alessandro Pinto and the Metropolis TeamUCB: Alessandro Pinto and the Metropolis Teamhttp://www.gigascale.org/metropolis/index.htmlhttp://www.gigascale.org/metropolis/index.html

Documents

Modeling of Heterogeneous Systems in Metropolis