344 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2, FEBRIJARY 1987

Modeling of Ambipolar a&: H Thin-Film Transistors

Abstract-Ambipolar hydrogenated amorphous silicon thin-filnr transistors are capable of both n- and p-channel device operation. Er- sential to the fabrication of such devices are ohmic source-drain cor .. tact regions and a high-quality low fixed charge gate insulator. A sin,.- ple model has been developed to describe the output drain cnrrertl versus drain voltage characteristics of these ambipolar devices. Tt.e model involves only the numerical integration of an interpolated she’d conductance function. By using the appropriate flat-band voltage, the model accurately predicts the experimental output drain current char- acteristics for both n- and p-type operation.

T I. INTRODUCTION

HE HYDROGENATED amorphous silicon (a-Si : Hi) thin-film transistor (TFT) has been studied extlen-

sively for many years in laboratories around the w d d [ 11-[3]. Several applications have been identified for this device including its use as a switching element in liqu’d- crystal display arrays [4], image sensors [5] , and thnm dimensional integrated circuits [6]. In addition, much the- oretical work has been done to quantify and explain ‘:he performance of a-Si : H TFT’s. However, throughout these many investigations little has been said or obserwd concerning the ambipolar nature of these devices; that is, the ability of an a-Si: H TFT to operate as an n- 8cH a p-channel device.

Since the primary application of the a-Si: H TFT has been as a simple switching element, this apparent lack of interest in the ambipolar behavior is not surprising. H ~ w - ever, as the device quality of a-Si: H continues to im- prove, the ambipolar nature of these devices could lead to important novel circuit applications, thereby increasing the overall usefulness of a-Si : H TFT’s.

Essential to the fabrication of ambipolar a-Si : H TFT’s is the formation of ohmic source and drain contact reg ions and the use of a high-quality gate insulator. Without the formation of ohmic contacts, the flow of electrons a r d o r holes through these regions can be severely diminished and even blocked. Thus, such devices will be incapable of both n- and p-channel operation.

In addition, the use of a high-quality gate insu1a:Ior is required in a-Si : H TFT’s in order to observe the ambi- polar behavior at reasonable voltage levels. To dale the ambipolar behavior has been observed only in devices

Manuscript received June 18, 1986; revised August 11, 1986. This work was supported by the Air Force Institute of Technology and Delco Elec- tronics.

The authors are with the School of Electrical Engineering, Purdue Uni- versity, West Lafayette, IN 47907.

EE Log Number 863 1082.

containing thermally grown S i 0 2 [7] and quartz [SI insu- lators. Both n- and p-channel operation for the same de- vice using a silicon nitride insulator has not been re- ported. This is due to the inherent fixed positive charge in .the SiN, insulator that prevents the formation of a p-channel device as the gate voltage on the device is biased negatively.

Evidence of the ambipolar behavior of a-Si TFT’s was observed by Neudeck and Malhotra in 1975 191. How- ever, a formal investigation of this property was not done until 1985 when Pfleiderer et al: applied a general ambi- polar field-effect transistor (FET) theory to a-Si : H TFT’s [lo]. This widely publicized theory [11]-[13], based on a modification to the Pao-Sah description of a unipolar FET, is quite thorough and seems to explain the transition between electron and hole regimes very well. However, some limitations appear to exist in its ability to consis- tently predict output drain characteristics over many de- cades of drain current.

In contrast to PAeiderer et al. ’s approach, the present paper presents a much simpler approach to modeling the ambipolar nature of a-Si : H TFT’s based on Tickle’s de- scription of TFT operation [14J. The resulting model is in general agreement with the previous work, but predicts the output drain characteristics over many decades of drain current for a single set of input parameters. The accuracy of the model i s improved when consideration is given to the difference in flat-band voltage between the n- and p-channel modes of operation.

11. EXPERIMENTAL DETAILS The inverted, staggered electrode a-Si: H TFT struc-

ture used in this investigation is shown in Fig. 1. The substrates were (100) single-crystal Si wafers ( p = 4-6 9 * cm) onto which 2000 A of silicon dioxide was ther- mally grown at 1100°C in dry oxygen. The a-Si : €3 film was deposited by the decomposition of silane with a power density of 8.17 mW/cm2 and a chamber pressure of 350 mT. The substrates were held at 250°C during the depo- sition sequence. The resulting film thickness was 3700 A, which was patterned using a technique described else- where [15]. The source-drain contact regions were ion implanted with phosphorus ions at two energies, 30 and 60 keV, each with a total dose of 10l6 ions/cm2. The sub- strate stage was heated to 250°C during the implants. Evaporated AI was used for metallization. A post-metal- lization anneal was performed at 200°C in a dry nitrogen environment for 30 min [ 161. As can be seen from Fig.

0018-9383/87/C200-0344$01.00 0 1987 IEEE

NEUDECK et al.: AMBIPOLAR a-Si:H THIN-FILM TRANSISTORS 345

<loo> P-type Si

Gate Contact

Fig. 1. Cross section of inverted, staggered a-Si : H thin-film transistor

1 , there is some undoped a-Si between the contacts and the enhanced channel at the a-Si/Si02 interface. The de- vices were unpassivated and had a channel width of 1000 pm and a channel length of 10 pm.

After fabricating the devices, both drain current (Z,) versus gate voltage (VG) transfer characteristics and out- put drain current versus drain voltage (V,) characteristics were measured inside a dark box probe station. For each device, a set of transfer curves was measured at four equally spaced values of V, (V, = - 3 , - 1 , 1, and 3 V). At each V,, 1, was measured in 0.5-V increments as V, was swept from -20 to 20 V and back to -20 V. Each Z, measurement was made 10 s after a new V , was ap- plied. Prior to measuring a transfer curve, VG was held at -20 V for 3 min to reduce the number of filled traps in the a-Si : H. As shown in the solid-line curve of Fig. 2, a transfer curve contained a noticeable amount of hysteresis caused by charge trapping and detrapping in the a-Si: H and Si02 insulator. This trapping and detrapping effec- tively caused the flat-band voltage (VFB) to shift up and down the channel as the gate voltage was increased and decreased. In an attempt to reduce the effects of this shift- ing VFB on the subsequent modeling effort, the forward and reverse values of Z, were averaged at each measured V,. The dashed-line curve in Fig. 2 shows an averaged transfer curve.

Each averaged transfer curve was converted to a sheet conductance G, curve using the relation G, = ZD/(W/L)VD. With a set of four sheet conductance curves measured at four spaced values of V,, a two-dimensional spline inter- polation was then performed to obtain the sheet conduc- tance curve at V, = 0 V. Fig. 3 shows an interpolated G, curve (dashed line) plotted with two of the four experi- mental G, curves (solid line). As can be seen from this figure, the interpolation removes the inherent skew in the G, curve determined at a single low V, [ 101. This skew can have a noticeable effect when the G, curve is used to model the device performance.

The output drain characteristics were recorded for sev- eral gate voltages in both the forward (V, = 0 to 30 V) and reverse ( VD = 0 to -20 V) directions. ZD was mea- sured at 0.5-V increments after each V, was applied for age open circuited for 3 min. Fig. 4 shows the experi- 10 s. Prior to recording a forward (n-channel) or reverse mental output drain characteristics for the n-channel de- (p-channel) output drain characteristic, V, was held at vice, while Fig. 5 shows similar characteristics for the -20 or 20 V, respectively, with the drain to source volt- p-channel device. Notice that at large I VDI in both devices

346 IELE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2, FEBRUARY 1987

I I I '

10-13 I I I 1 0.00 5.00 10 .o 15.0 90 .0 25.0 30 .o

Drain Uoltaqe <volts)

- -7

Fig. 4. Experimental and modeled output drain characteristics of an n-channel a-Si : H TFT: circles-experimental data; solid line-rlodeled data.

10-15 L7- -20.0 -17.5 -15.0

-\

-\

O\:; pK Oo

7 , , T -12.5 -10.0 -7.50 -5.00 -2.50 0.00

Drain Uoltage (volts)

Fig. 5 . Experimental and modeled output drain characteristics of ;L p-chan- ne1 a-Si : H TFT: circles-experimental data; solid line-modeled data.

the ambipolar effect of the opposite channel forming can be seen.

In comparing the transfer and output drain chanlcteris- tic measurement techniques, it should be noted th3.t each

technique subjects the device under test to different op- erating conditions, particularly with regard to VFB. For example, during the transfer characteristic measurements, VFB is constantly shifting due to charge trapping as VG is increased and then decreased. Alternately, during the out- put drain characteristic measurements, VFB remains rela- tively fixed at each V,, but changes down the channel as 1 VDl is increased.

111. SIMPLE THEORY Examination of the transfer curve shows two regions of

nearly constant slope on a logarithmic plot. As shown in the average (dashed-line) curve of Fig. 2, one region ex- ists above VFB and one region below VFB. The region above VFB corresponds to electron conduction or n-channel de- vice operation, while the region below VFB corresponds to hole conduction or p-channel device operation. Thus, the device clearly displays ambipolar characteristics.

According to Tickle [ 141, the output drain characteris- tics of a TFT are proportional to the integral of the sheet conductance. Including VFB ir, Tickle's relation yields the following expression:

VC - VFB

I D = (w/L) G m dV (1) VG - VFB - VD

where WIL is the device width to length ratio and V is the voltage across the gate insulator to the channel. Since G,(V) is only a function of voltage across the insulator and not of carrier type, (1) is applicable for ambipolar device operation. Hence, by integrating the G,(V) func- tion and multiplying by WIL, the output drain character- istics can be realized. It should be noted that (1) is equiv- alent to [13, eq. (2)] .

IV. RESULTS In using (1) to model ambipolar a-Si : H TFT perfor-

mance, the G,(V) function (dashed line of Fig. 3) was obtained by interpolating from four equally spaced trans- fer curves to V, = 0 V. A trapezoidal numerical integra- tion technique was then used to integrate the G,(V) curve to obtain the modeled output drain characteristics shown by the solid-line curves in Figs. 4 and 5 . Notice that for the n-channel output characteristics of Fig. 4, the mod- eled ZD follows the magnitude and shape of the experi- mental ID quite well up to where ID rises sharply. Then the modeled ID consistently begins to rise sharply at a value of VD lower than the experimental ID, but still fol- lows the general shape quite well. Interestingly enough, the difference in VD between where the two sharp ZD in- creases occur, seems to correspond to the difference in the flat-band voltages of the n-channel (VFBn) and p-channel ( VFBp) devices seen in Fig. 2.

In looking at the p-channel output characteristics of Fig. 5 , the modeled ID follows the general shape and magni- tude of the experimental ID at low I V , 1 . However, the model seems to fall off at higher I VG I where the experi- mental ID is saturated, just before the device switches

NEUDECK et al.: AMBIPOLAR a-Si:H THIN-FILM TRANSISTORS 347

10-~ -

10" -

a-Si:II

I' I

lo-'* I

0 .oo 5 . 0 0 10 .o 15.0 20.0 25.0 30.0

Drain Uoltaqe (volts)

I _7___(

Fig. 6. Experimental and modeled output drain characteristics of an n-channel a-Si: H TFT: circles-experimental data; solid line-modeled data using a sheet conductance function interpolated to V, = 0 V; dashed line-modeled data using a sheet conductance function determined from measurements at Vo = 1 V.

from predominantly p-channel operation to predominantly n-channel operation.

During this investigation, a brief study was conducted to verify the necessity of using an interpolated G,(V) function. Since the process involved in obtaining the in- terpolated G,(V) curve for V, = 0 V is rather cumber- some compared to simply measuring a single Gs(V) curve at one low V,, a comparison was made between the output curves modeled from these two different sheet conduc- tance functions. As shown in Fig. 3, a noticeable varia- tion exists between the interpolated and two of the exper- imental sheet conductance curves. Since these curves do not coincide, a different output drain curve was expected. This expectation was confirmed as shown in Fig. 6. When the interpolated (V, = 0 V) G,(V) curve was used in (l), the solid-line curves shown in Fig. 6 resulted. In com- parison, when a G J V ) curve measured at V, = 1 V was used, the dashed-line curves of Fig. 6 resulted. Clearly, the interpolated data gave a better fit between the simple theory and experimental data than did the uninterpolated data. Thus, the interpolated G,( V ) curve was determined to be an important function fQr use in (1). Had the V, = - 1 V G,(V) curve been used, the opposite effect is ob- served.

v. DISCUSSION. OF RESULTS A. Device Operation

In examining the n-channel output drain characteristics of Fig. 4 for the ambipolar a-Si : H TFT, four regions of

(b) Fig. 7. Enhanced electron channel of an a-Si : H TFT (a) at pinchoff and

beyond (dashed lines show changing boundary of shrinking channel as VD is changed). (b) Shrinking electron and expanding hole layers in an ambipolar a-Si : H TFT beyond pinchoff (dashed lines show changing boundaries of electron and hole layers as VD is changed).

device operation can be seen. As indicated in Fig. 4 for V, > V,,, the first region occurs at low V, where the characteristic is linear. This corresponds to a low-resis- tance enhanced electron channel existing along the Si02/ a-Si : H interface in parallel with the bulk a-Si : H resis- tance. As the drain voltage is increased above 0 V, elec- tron current through the device increases linearly until the change in potential across the drain end of the device re- duces the number of electrons at the drain end to a neg- ligible amount (see Fig. 7(a)). This potential is called the pinchoff voltage (V,) and serves as the transition between the first and second regions of device operation.

In region 2, as V, is increased beyond V,, the electron current in the enhanced channel increases slightly because V, is mildly dependent on V,. While this electron current is increasing, the drain end of the enhanced channel is being depleted of electrons causing the enhanced electron channel to shrink toward the source (see Fig. 7(a)). Since the increase in V, beyond V, is applied between the drain and the end of the enhanced channel, the potential across the shrinking enhanced channel stays about the same, per- mitting the current to rise only slightly as V, increases. In addition, the parallel current component through the bulk region of the device continues to increase slightly as the drain voltage is increased.

While the device is operating in region 2, an enhanced hole layer begins to form at the drain end of the device in the area previously occupied by the enhanced electron layer (see Fig. 7(b)). This hole layer forms as a result of the drain end potential being larger than the gate poten- tial. A reversed biased situation then exists causing the

348 IEEE TRAIISACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2, FEBRUARY 1987

formation of the enhanced hole layer. The effects of this hole layer are not observed in the device performance un- til the device enters region 3.

As the device enters region 3 , the current begins to in- crease at a faster rate than in region 2. This increased rate is due to the superposition of the current flowing through the electron and hole layers. In this region, the dominant current carrier makes a transition from electron to hole, thereby demonstrating the ambipolar phenomena.

In region 4 , the current initially increases exponentially and then tapers off. The initial increase is due to the p-channel being created by the drain to gate voltage ( VDG), while the gate to source voltage ( VGs) controls the n-chan- ne1 conduction. Since VGs does not change, the n-channel current increases very little. However, since V, (and hence VDG) increases, the p-channel conduction also in- creases resulting in the exponential current rise. The ex- istence of a p-n diode at the a-Si: H interface where the enhanced electron and hole layers meet is of the correct polarity for ID to continue to increase. The rate at which the current rises decreases as the localized state density ait the band edges increases. This increased state density ef- fectively reduces the ability of the Fermi energy to move, thereby reducing the rate at which current can increase through the device (i.e., less band bending per unit volt- age).

By reversing the polarity of the applied biases and al- ternating the n- and p-channel device formation, a de- scription similar to that given above could be presented to explain the p-channel device output drain characteris. tics. Fig. 5 contains an example of these characteristics.

B. Improved Model

In order to obtain a better match between the experi- mental data and the model described by (l) , further con- sideration must be given to the G,(V) function. Recall that this function was derived from 1, measurements averaged between forward and reverse gate voltage sweeps (see Fig. 2). Although this averaging was done to compensate fclr the VFB difference between n- and p-channel devices, :& effectively gave the same VFB to both type devices. As, seen in Fig. 2 and elsewhere [7], the n- and p-channd devices have different VFB (see VFB, and VFBp in Fig. 211.

Incorporating this V F B difference into the interpolated Gs( V ) function yields a better match between the exper i-- mental data and the model described Qy (l), particularly for the n-channel device. One procedure for incorporating the VFB difference consists of breaking the interpolated Gs(V) curve into two regions; Gs(V) for V > VFB ar d G,(V) for V < VFB (see the solid-line curve of Fig. 8). For V > VFB, the GJV) curve is used as shown. For V .< V F B , the G,( V ) curve is altered by extending the G,(J’) value at VFB to VFB - AVFB where AVFB = ( VFB, - VFBp). The GJV) curve is shifted in the negative V, direction by AVFB. The resulting shifted Gs(V) curve is shown by the dashed-line in Fig. 8. When this shifted curve is used in (l), the solid-line curves of Fig. 9 are the result.

10‘~

IO”

10’9

Gate Uoltage (uol ts)

Fig. 8. Sheet conductance functions of an a-Si: H TFT: solid line-inter- polated sheet conductance with no shift; dashed line-interpolated sheet conductance shifted by the difference in n- and p-channel device VFB’s.

10-7

IO” 4

10-13 0 .00 5.00 10 .o 15.0 20.0 25.0 3 0 . 0

I -_r---__l

Drain Uoltage (vol ts)

Fig. 9. Experimental and modeled output drain characteristics of an j n-channel a-Si : H TFT: circles-measured data; dashed line-modeled

data with no shift in the sheet conductance function; solid line-modeled data with the sheet conductance function shifted by the difference in the n- and p-channel device VFB’s.

NEUDECK et al. : AMBIPOLAR a-Si:H ,THIN-FILM TRANSISTORS 349

In examining Fig. 9 for the n-channel device, the solid- line curves obtained using the shifted GJV) curve match the experimental data much better, especially after the op- posite channel device is formed, than the dashed-line curves obtained using the unshifted GJV) curve. Thus, shifting G,(V) by the difference between VFB, and VFBp yields an excellent match between the experimental and modeied output drain cuives for the n-channel device.

In examining the computed results for the p-channel de- vice, the curves obtained using the shifted Gs( V ) curve do not match the experimental data any better than the curves obtained using the unshifted G,(V) curve. Both sets of modeled curves match the experimental curves fairly well in the unsaturated Z, regions and after the opposite device type is formed. However, in the saturated Z, region, the curves obtained from the shifted Gs(V) curve are below the experimental 1, values, while the curves obtained from the unshifted Gs(V) curve are above the experimental Z, values.

VI. CONCLUSIONS a-Si : H TFT’s with ohmic source-drain contact regions

and a high-quality gate insulator have been shown to pos- sess ambipolar characteristics. The output drain charac- teristics of these devices can be modeled quite simply and accurately by numerically integrating an interpolated sheet conductance function obtained from averaged I , measure- ments. The model is improved by including the effects of the different n- and p-channel device flat-band voltages in the interpolated sheet conductance function. By compar- ing the results of using the shifted and unshifted G,(V) curves, the importance of VFB in modeling ambipolar a- Si: H TFT’s was demonstrated. The improved model shows good agreement and consistency with experimental output drain characteristics over many orders of magni- tude of Z, and for both electron and hole currents from a single sheet conductance function.

ACKNOWLEDGMENT The authors would like to thank S . Phillips for provid-

ing the photoplates used in the device fabrication and J. Shields and T. Grotjohn for the software programs used in the data acquisition and analysis.

REFERENCES [ l ] G. W. Neudeck and A. K. Malhotra, “An amorphous silicon thin-

film transistor: Theory and experiment,” Solid-state Electron., vol.

[2] K. D. Mackensie, A. J . Snell, I. French, P. G. LeComber, and W. E. Spear, “The characteristics and properties of optimized amor- phous silicon field-effect transistors,” Appl. Phys. A , vol. 31, pp. 87- 92, 1983.

[3] M. Fukai and S. Nagata, “Amorphous silicon electronic devices,” in Amorphous Semiconductor Tech. and Dev. , Y. Nakayama, Ed. Tokyo: North-Holland, 1981, pp. 199-210.

[4] M. J. Powell, “Material properties controlling the performance of amorphous silicon thin-film transistors,” in Proc. Materials Res. So- ciety Symp., vol. 33, M. J. Thompson, Ed. New York: North-Hol- land, 1984, pp. 259-273.

[5] F. Okumura and S. Kaneko, “Amorphous Si : H linear image sensor operated by a-Si : H TFT array,” in Proc. Materials Res. Society

19, pp. 721-729, 1976.

Symp., vol. 33, M. J . Thompson, Ed. New York: North-Holland, 1984, pp. 275-280.

[6] Y. Nara, Y. Kudou, and M. Matsumura, “Application of amorphous- silicon field-effect transistors in three-dimensional integrated cir- cuits,’’ Japan. J. Appl. Phys., vol. 22, no. 6, pp. L370-L372, June 1983.

[7] M. Matsumura and Y. Nara, “High-performance amorphous-silicon field-effect transistors,” J . Appl. Phys., vol. 51, no. 12, pp. 6443- 6444, Dec. 1980.

181 N. B. Goodman, H. Fritzsche, and H. Ozaki, “Determination of the density of states of a-Si : H using the field effect,” J . Non-Cryst. Sol- ids, vol. 35 and 36, pp. 599-604, 1980.

[9] G. W. Neudeck and A. K. Malhotra, “Field-effect conductance mod- ulation in vacuum evaporated amorphous silicon films,” J. Appl. Phys., vol. 46, no. 1, pp. 239-246, Jan. 1975.

[lo] H. Pfleiderer, W. Kusian, and B. Bullemer, “An ambipolar amor- phous-silicon field-effect transistor,” Siemens Forsch.-u. Entwickl. - Ber., vol. 14, no. 3, pp. 114-119, 1985.

1111 -, “An ambipolar field-effect transistor model,” Siemens Forsch.- u. EntwickLBer., vol. 14, no. 2, pp. 69-75, 1985.

1121 PI. Pfleiderer, “Elementary ambipolar field-effect transistor model,” IEEE Trans. Electron Devices, vol. ED-33, no. 1, pp. 145-147, Jan. 1986.

[13] H. Pfleiderer and W. Kusian, “Ambipolar field-effect transistor,” Solid-state Electron., vol. 29, no. 3, pp. 317-319, 1986.

1141 A. C. Tickle, Thin-Film Transistors. New York: Wiley, 1969. 1151 H. F. Bare and G. W. Neudeck, “Etching patterns in amorphous sil-

icon,” J . Vac. Sci. Technol. A , vol. 4, pp. 239-241, Mar./Apr. 1986. [16] -, “Ion implanted contacts to a-Si: H thin-film transistors,” IEEE

Electron Device Lett. ,. vol. EDL-7, no. 7, pp. 431-433, July 1986.

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350 IEEE TRPd\SACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2 , FEBRUARY 1987

grated circuit fabrication, and amorphous silicon thin-film transistors. Upon completion of the Ph.D. degree at Purdue, he will return to the Department of Electrical Engineering at the U.S. Air Force Academy.

Major Bare is a member of Sigma Pi Sigma and the American Physical Society.

Kyo Y. Chung (S’86) was born in Seoul, Korea, in 1955. He received the B.S. degree (with hon- ors) in electronic engineering from Kymghee University in 1977 and the M.S.E.E. degree from the University of Minnesota in 1984. He is cur- rently working toward the Ph.D. degree in elec- trical engineering at Purdue University.

From 1978 to 1982, he was with the Korea Telecommunication Company. His research inter- ests include electrical characterization and mod- eling of amorphous silicon thin-film transistors and EPROM’s.