POLITECNICO DI MILANO

School of Industrial and Information Engineering

M.Sc. Automation and Control Engineering

Model Library for the Simulation of

Logic Controls

Supervisor: Master thesis of:

Prof. Alberto Leva Tayfun Yıldız, 872876

Academic Year 2017 - 2018

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Acknowledgment

I would first like to thank my thesis advisor Prof. Alberto Leva of the School of Industrial and

Information Engineering / Automation and Control at Polytechnic University of Milan. The

door to Prof. Leva’s office was always open whenever I ran into a trouble spot or had a question

about my research or writing. He consistently allowed this paper to be my own work but steered

me in the right the direction whenever he thought I needed it.

Finally, I must express my very profound gratitude to my parents and to my friends for

providing me with unfailing support and continuous encouragement throughout my years of

study and through the process of researching and writing this thesis. This accomplishment

would not have been possible without them. Thank you.

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Abstract

IndustrialControlSystems library has been created for duplicating and modeling the industrial

controllers to use in the Modelica software in an efficient way. There are some logical functions

in that library but there is no some of them therefore, the aim of this thesis is to create a model

library which can be used in IndustrialControlSystems. It was decided to design Flip-Flops,

Counters and the Sequencer based on the IEC standards with using the OpenModelica

Connection Editor (OMEdit) tool in that model library.

Before designing, the literature research has been made for the IEC standard, PLC

(Programmable Logic Control) libraries, Modelica libraries and the logical functions that how

to implement in model library. After literature research, the logical functions have been

designed based on the IEC standards furthermore, each logical function has been tested and

simulated in the model library. The results have been compared with the truth tables of the

logical functions and the graphical signals of the outputs of the logical functions.

Key words: industrial controls; IEC 61131 standard; PLC; simulation

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Sommario

La libreria IndustrialControlSystems è stata creata per replicare e modellare i controller

industriali da utilizzare nel software Modelica in modo efficiente. Ci sono alcune funzioni

logiche in quella libreria, ma alcune mancano; quindi lo scopo di questa tesi è creare una libreria

di modelli che possa essere utilizzata in IndustrialControlSystems. È stato deciso di progettare

flip-flop, contatori e sequencer basati sugli standard IEC utilizzando lo strumento

OpenModelica Connection Editor (OMEdit).

Prima di progettare la libreria, è stata fatta una ricerca bibliografica per le librerie IEC standard,

PLC (controllore logico programmabile), librerie Modelica e le funzioni logiche che come

implementare nella libreria modello. Dopo tale ricerca lin letteratura, le funzioni logiche sono

state progettate in base agli standard IEC, inoltre ogni funzione logica è stata testata e simulata

nella libreria del modello. I risultati sono stati confrontati con le tabelle di verità delle funzioni

logiche e i segnali grafici degli output delle funzioni logiche.

Parole chiave: controlli industriali; standard IEC 61131; PLC; simulazione

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CONTENTS

1. CHAPTER 1 ...................................................................................................................... 1

1.1 Introduction ..................................................................................................................... 1

2. CHAPTER 2 ...................................................................................................................... 3

2.1 IEC 61131-3 Standard ..................................................................................................... 3

2.1.1 IEC Languages ............................................................................................................ 4

2.1.1.1 Ladder Logic ............................................................................................................ 5

2.1.1.2 SFC (Sequential Function Chart) ............................................................................. 6

2.1.1.3 FBD (Function Block Diagram) .............................................................................. 7

2.2 Overview of PLC Libraries ............................................................................................. 8

2.3 Overview of Logics and Flip-Flops .............................................................................. 10

2.3.1 Sequential Logic ........................................................................................................ 10

2.3.2 Classification of Sequential Logic ............................................................................. 11

2.3.3 Flip-Flops ................................................................................................................... 12

2.3.4 Combinational Logic ................................................................................................. 20

3. CHAPTER 3 .................................................................................................................... 23

3.1 Library Descriptions ...................................................................................................... 23

3.1.1. Modelica Standard Library ........................................................................................ 23

3.1.2. Modelica IndustrialControlSystems Library ............................................................. 28

3.1.3. Modelica Trials Library ............................................................................................. 30

4. CHAPTER 4 .................................................................................................................... 34

4.1 Simulations and Results ................................................................................................ 34

4.1.1. Set-Reset Flip-Flop .................................................................................................... 34

4.1.2. D Flip-Flop ................................................................................................................ 35

4.1.3. JK Flip-Flop ............................................................................................................... 36

4.1.4. Clocked Set-Reset Flip-Flop ..................................................................................... 37

4.1.5. T Flip-Flop ................................................................................................................. 38

4.1.6. Sequencer ................................................................................................................... 39

4.1.7. Asynchronous Counter Down ................................................................................... 40

4.1.8. Synchronous Counter Down ...................................................................................... 41

5. CHAPTER 5 .................................................................................................................... 42

5.1 Conclusion ..................................................................................................................... 42

6. CHAPTER 6 .................................................................................................................... 43

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6.1 REFERENCES AND BIBLIOGRAPHY ..................................................................... 43

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LIST OF FIGURES

Figure 1 : Race condition of logic gate .................................................................................................... 5

Figure 2 : Example of an SFC program ..................................................................................................... 6

Figure 3 : Example of Function Block ...................................................................................................... 7

Figure 4 : Logic operations in PLC ............................................................................................................ 8

Figure 5 : An example of usage of timer in PLC ....................................................................................... 9

Figure 6 : General view of Modelica Standard Library ............................................................................ 9

Figure 7 : General view of the IndustrialControlSystems Library .......................................................... 10

Figure 8 : General view of Sequential Logic .......................................................................................... 11

Figure 9 : Classification of Sequential Logic .......................................................................................... 11

Figure 10 : General view of feedback loop ............................................................................................ 12

Figure 11 : General view of SR flip-flop ................................................................................................. 14

Figure 12 : General view of D flip-flop ................................................................................................... 14

Figure 13 : General view and the truth table of JK flip-flop .................................................................. 15

Figure 14 : Truth table and ladder logic for JK flip-flop ......................................................................... 16

Figure 15 : General view of the JK flip-flop ........................................................................................... 17

Figure 16 : General view of the T flip-flop ............................................................................................. 18

Figure 17 : The logic diagram of the 2-bit ripples up counter ............................................................... 19

Figure 18 : Logic diagram of the 2-bit synchronous up counter ........................................................... 19

Figure 19 : General view of the combinational logic ............................................................................. 20

Figure 20 : General view of the boolean algebra, truth table and logic diagram ................................. 21

Figure 21 : General view of the classification of combinational logic ................................................... 22

Figure 22 : General view of the Modelica Standard library in the OMEdit tool .................................... 27

Figure 23 : General view of the IndustrialControlSystems library ........................................................ 28

Figure 24 : Interface for a generic controller. The in- put/output connector evidenced in yellow are

always present, the other ones can be conditionally selected. ............................................................ 29

Figure 25 : General view of the Trials library in OMEdit tool ................................................................ 31

Figure 26 : An example of one model in Trials library ........................................................................... 32

Figure 27 : An example of a code for that model .................................................................................. 33

Figure 28 : An example of simulation for that model ........................................................................... 33

Figure 29 : Simulation result for the Set-Reset Flip-Flop ...................................................................... 34

Figure 30 : Simulation result for the D Flip-Flop ................................................................................... 35

Figure 31 : Simulation result for the JK Flip-Flop................................................................................... 36

Figure 32 : Simulation result for the Clocked Set-Reset Flip-Flop ......................................................... 37

Figure 33 : Simulation result for the T Flip-Flop .................................................................................... 38

Figure 34 : Simulation result for the Sequencer.................................................................................... 39

Figure 35 : Simulation result for the Asynchronous Counter Down ..................................................... 40

Figure 36 : Simulation result for the Synchronous Counter Down ....................................................... 41

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1. CHAPTER 1

1.1 Introduction

The aim of this thesis is to implement and represent the Logic Control Functions in the

Modelica software. These Logic Functions will be implemented in to the Modelica library that

we have already, consequently the Modelica library will be slightly modified. Moreover, it can

be used for OpenModelica environment and it is suitable for that. OpenModelica is a powerful

program that will be used in the nearest future mainly by the Engineering community [1].

Generally, the idea is to research three main languages which are Ladder Logic, SFC

(Sequential Function Chart) and FBD (Function Block Diagram) that is used to write the PLC

(Programable Logic Control) program and choosing which one is the more suitable and efficient

for Modelica software. After choosing the language, flip-flops, counter and sequencer, “Logic

Contol Functions” were designed and implemented to the Modelica software besides, to be sure

that everything is working, simulation and testing for the Logic Control Functions were done.

For doing that OpenModelica Connection Editor (OMEdit) was used to designing and

implementation. OMEdit is user-friendly a leading open source that has a graphical user

interface that gives the users with easy‐to‐use model creation, connection editing, simulation of

models, and plotting of results. For the simulation it was used Debugger program which is

inside of the OMEdit. It is a strong tool that the user can easily see the simulation result and

also user can plot the result immediately [12].

For the designing and testing of Logic Control Functions, Modelica Standard Library was

used. It is a free library that is developed together with the Modelica language from the

Modelica Association. It contributes model components and standard component interfaces

from several engineering domains. Inside of the Modelica Standard Library, some of the

libraries such as library of basics input/output control blocks, library of connectors and partial

model for input/output blocks and library of single source block is used (more details about

Modelica Standard Library will be provided in the next chapter) [13].

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After designing that model library, it will be added in to the Modelica library which is called

IndustrialControlSystems. That library was designed with the Modelica language to use the

industrial controllers in Modelica software efficiently. IndustrialControlSystems library is an

open source and it provides a set of continuous and discrete control systems moreover, it can

be used to arrange the majority of industrial controllers. That library includes many control

functions (more details about IndustrialControlSystems library will be explained in the next

chapter) [1] [13].

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2. CHAPTER 2

2.1 IEC 61131-3 Standard

The IEC (International Electrotechnical Commission) is an international standards

organization that publishes electrical and electronic standards. Hundreds of them, in fact;

standardizing everything from letter symbols in electronics to medical equipment and railroad

communication and signaling [1] [9].

The adoption of IEC 61131-3 by the industry is driven by the increasing software

complexity of control and automation requirements. The time to create, labor cost, and

maintainability of control software has a major impact on control projects which can be

improved using the IEC 61131-3 vendor independent programming language standard.

Applying a standard programming language has a positive impact on the software life-cycle

that includes requirements analysis, design, construction, testing (validation), installation,

operation, and maintenance. The impact on maintenance is important since control software

maintenance, including upgrades, is generally 2- 4 times the labor of initial programming.

IEC 61131-3 provides multiple language support within a control program. The control

program developer can select the language that is best suited to a particular task, greatly

increasing their productivity. Plus, with a standardized programming interface that is

completely independent of the hardware platform, users can greatly reduce the cost of program

maintenance and training across companywide automation applications.

IEC 61131-3 is hardware independent. The ability to transport automation solutions to other

platforms is vastly improved over PLC applications offering users and System Integrators a

level of reusability never before available. IEC 61131 increases the efficiency and speed of

implementing new automation solutions by using readily available control components

developed on other projects and by outside developers.

Companies that have chosen to implement IEC 61131-3 find that they reduce human

resource costs in training, debugging and maintenance, and improve productivity from the

higher reusability [1] [9].

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2.1.1 IEC Languages

IEC 61131-3 is the international standard for programmable controller programming

languages. Fundamentally, it determines the syntax, semantics and display for the following

parcel of PLC programming languages:

• Ladder diagram (LD), graphical

• Function block diagram (FBD), graphical

• Structured text (ST), textual

• Instruction list (IL), textual (deprecated in 3rd edition of the standard)

• Sequential function chart (SFC), has items to construct programs for sequential

and parallel control processing [1] [8].

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2.1.1.1 Ladder Logic

Ladder logic is a drafted technique to archive the design and construction of relay rocks,

and it is used in manufacturing and process control. Ladder logic has emerged into

a programming language that shows a program by a graphical diagram form on the circuit

diagrams of relay logic hardware. It is used to develop software for programmable logic

controllers (PLCs) used in industrial control applications [1] [3].

Although there is an IEC standard to represent ladder logic, it has not been used to represent

Logic Control Functions in Modelica software. The first problem of the ladder logic is the

transformation of the Logic Control Functions to the Modelica. In that software, ladder logic

representation is used like a parallel contact, on the other hand, in the PLC (Programmable

Logic Control), it is used like series contact. It is very hard to transform series contact to the

parallel contact or vice versa.

The second problem of the ladder logic is that it is suited to control problems where only

binary variables are required, whereas Modelica software is object-oriented and equation-based

program and binary variables are not used in that software.

The other problem is the race condition or race hazard of logic functions. It can be easily

understood from the figure 1 what the race condition is. According to the figure, Δt1 and Δt2

represent the propagation delays of the logic views. If the input value A changes from low to

high then, the circuit outputs will be (∆t1 + ∆t2) − ∆t2 = ∆t1

Figure 1 : Race condition of logic gate

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It is the behavior of an electronic, software or other system where the output is dependent

on the sequence or timing of other uncontrollable events. That condition is mostly occurred in

logic circuits, and it may produce unexpected results. In ladder logic representation, the

sequential order of operations may be undefined or obscure because of the race condition.

Therefore, ladder logic is not preferred to represent Logic Control Functions in Modelica

software [1] [3].

2.1.1.2 SFC (Sequential Function Chart)

SFC is a graphical and structured representation language that display the process flow as

a diagram, and it is used for programmable logic controllers (PLCs). SFC provides the

connection method of the application program by dividing the step and each step is related to

the action and each transition is related to its condition. It allows to users to control the

sequential process by describing the transition conditions and actions. SFC is suitable for

understanding the process order and status transition of a program. The figure 2 represents an

example of a program written in SFC to understand better [4] [7].

Figure 2 : Example of an SFC program

SFC is also not suitable to represent the Logic Control Functions in Modelica software,

and it was not used. It is very much based on Petri nets, but that software is equation-based

program therefore, it is not easy and efficient way to represent Logic Control Functions with

using SFC language.

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Designing parallel structures is possible in SFC, since state more than one phase may be

active at the same time. Moreover, sequential controls parameterize and activate lower level

logical control systems by setting corresponding global control signals. These control signals

can have a brief or a lasting, a direct or a delayed effect. Sequential controls as well as logical

control systems have to support different operating modes.

Therefore, SFC language is not best way to describe and design the Logic Control

Functions in Modelica software [4] [7].

2.1.1.3 FBD (Function Block Diagram)

FBD is a graphical language that can express the function between input variables and

output variables. A function block is a program instruction part which, when performed, yields

one or more output values. It works with a list of networks, where each network has a structure

that can consist of the logical and arithmetic definitions, calls of function blocks, a jump or a

return information. A function block is represented in the figure 3 with the function name [3]

[5] [2].

Figure 3 : Example of Function Block

FBD is chosen to represent Logic Control Functions in Modelica software. First of all, it is

easy to understand the program control logic by means of graphical representation. It will be

much easier and more efficient to design logic control functions with using FBD in Modelica.

Moreover, graphical data flow of FBDs makes debugging easy and many FBD program editors

(such as Siemens Step 7) also support animation showing data flow to make debugging easier.

The main benefit of the function block diagram is that the code can be reused again. It is

used as existing function blocks such as PIDs and filters or encapsulate custom logic, and this

code can be easily rehash throughout the programs. Since divided copies are made, every time

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these function blocks are called, it cannot be risk accidentally overwriting data. Additionally,

function blocks also can be invoked from ladder diagrams and even textual languages such as

structured text, making them easily transported among different models of computation.

As a result, FBD is suitable and efficient way to describe and design the Logic Control

Functions in Modelica software [3] [5] [2].

2.2 Overview of PLC Libraries

For this thesis, it has been chosen the three PLC libraries which are ABB, Beckhoff and

Siemens, to implement Logic Control Functions to Modelica software based on some common

points of these companies’ library, and it will be much easier for us to design logic functions.

These companies’ libraries have the standard library that is designed to use FBDs most efficient

way. Generally, the standard libraries of these PLCs contain string functions, bistable function

blocks, counter, timer and trigger. If FBDs are needed to use in the program, it can be used from

that library. It can be seen from the figure 4 that inside the standard library, logical function

operations are included.

Figure 4 : Logic operations in PLC

Most common point of these PLCs libraries is that they have the standard library which

helps to the users to code any logical operations in the software furthermore, under that library,

logical functions which are timers, counters and other logical operations can be used as an FBD

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when it is needed during the inside of program. It can be seen from the figure 5 that when the

user wants to use a logical operation, it can be added easily.

Figure 5 : An example of usage of timer in PLC

In our case, there is one library that is already designed which is called Modelica Standard

Library in Modelica software. With using that library, Flip-Flops, Counter and Sequencer can

be modeled in that software easily furthermore, it can be added that logic functions in

IndustrialControlSystems Library because that library already includes some logical functions

to model and design the industrial controllers.

The general view of the Modelica Standard Library can be seen from the figure 6. It

includes Modelica package and inside there are many operations and blocks that help to the

users to design their model in an efficient way.

Figure 6 : General view of Modelica Standard Library

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It can be seen from the figure 7 that in the IndustrialControlSystems Library some

operations such as timers, counters etc. already exist there. The purpose of this library is to

support an opportunity for the users who want to use industrial control operations in the

Modelica software to design their model.

Figure 7 : General view of the IndustrialControlSystems Library

2.3 Overview of Logics and Flip-Flops

2.3.1 Sequential Logic

Sequential Logic Circuits have some form of inherent “Memory” built in. That means that

sequential logic circuits afford to get into account their previous input state including those

present, a sort of before and after effect is convoluted with sequential circuits [11] [15].

In other words, the output state of a Sequential Logic Circuit is a functional operation of

the following three states, the present input, the past input and/or the past output. Sequential

Logic Circuits recognize these conditions and remain fixed in their current state until the next

clock signal come up one of the states, giving sequential logic circuits “Memory”.

Sequential logic circuits are commonly subtitled as two state or bistable devices which

have their output or outputs set in one of two basic states, a logic level 1 or a logic level 0

furthermore, will stay latched (hence the name latch) continually in this current state or

condition until some other input trigger pulse or signal is activated which will affect the bistable

to change its state once again.

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Figure 8 : General view of Sequential Logic

2.3.2 Classification of Sequential Logic

The standard logic gates are the main blocks of combinational circuits, bistable latches and

flip-flops are the elemental building blocks of sequential logic circuits. Sequential logic circuits

can be established to support either simple edge-triggered flip-flops or more complex sequential

circuits such as storage registers, shift registers, memory devices or counters. Either way

sequential logic circuits can be branched into the following three main categories:

• 1. Event Driven

Asynchronous circuits that transform the state immediately when enabled.

• 2. Clock Driven

Synchronous circuits that are harmonized to a specific clock signal.

• 3. Pulse Driven

Which is a combination of the two that responds to triggering pulses.

Figure 9 : Classification of Sequential Logic

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In addition, the two logic states declared above logic level “1” and logic level “0”, a third

element is mentioned that separates sequential logic circuits from their combinational

logic counterparts, namely TIME. Sequential logic circuits go back to their original steady state

once reset and sequential circuits with loops or feedback paths are said to be “cyclic” in nature.

It is known that in sequential circuits changes appear only on the application of a clock

signal making it synchronous, in another way the circuit is asynchronous and depends upon an

external input. To contain their current state, sequential circuits rely on feedback and this

appears when a fraction of the output is fed back [11] [15].

Sequential Feedback Loop

Figure 10 : General view of feedback loop

The two inverters or NOT gates are linked in series with the output at Q fed back to the input.

Unfortunately, this configuration never changes state because the output will remain the same,

either a “1” or a “0”, it is permanently set. However, it can be seen how feedback works by

examining the most basic sequential logic components, called the SR flip-flop in detail.

2.3.3 Flip-Flops

The flip-flop or latch is a circuit which has two stable states moreover, it can be used to

save state information. The circuit can be created to modify the state by signals applied to one

or more control inputs and it will have one or two outputs furthermore, it is the basic storage

element in sequential logic. The Flip-flops and latches are elements of building blocks of the

digital logic systems and they can be used in computers, communications, and many other types

of systems.

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Flip-flops and latches can be used as data storage elements in digital logic. A flip-flop is a

device which saves a single bit (binary digit) of data; one of its two states shows a "one" and

the other shows a "zero". This data storage is used for storage of state, and such a circuit is

illustrated as sequential logic in electronics. When it is used in a finite state machine, the output

and next state depend not only on its current input, but also on its current state (and hence,

previous inputs). Meanwhile, it is also used for counting of pulses, and for adjusting variably-

timed input signals to some reference timing signal [11] [15].

The flip-flops can be seen either simple (transparent or opaque) or clocked (synchronous or

edge-triggered). Although the term of the flip-flop has historically mentioned generically to

both simple and clocked circuits, in modern usage it is so common to save the term flip-

flop exclusively for arguing clocked circuits; the simple ones are generally called latches.

There are 5 types of flip-flops and which are;

• SR Flip-Flop

• Clocked SR Flip-Flop

• D Flip-Flop

• JK Flip-Flop

• T Flip-Flop

2.3.3.1 SR Flip-Flop

The SR flip-flop, also known as a SR Latch, can be examined as one of the most elemental

sequential logic circuit. This simple flip-flop has essentially a one-bit memory moreover, it is

a bistable device that has two inputs, the one which makes the device “SET” (meaning the

output is equal to 1), and is defined as S and the another one which makes the device “RESET”

(meaning the output is equal to 0), is represented as R.

The meaning of SR description is that making the logic operation “Set-Reset”. The reset

input makes the flip-flop reset and it returns back to its original state with an output Q that will

be either at a logic level “1” or logic “0” depending upon this set/reset condition [11] [15].

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Figure 11 : General view of SR flip-flop

2.3.3.2 D Flip-Flop

Figure 12 : General view of D flip-flop

It can be remembered that a simple SR flip-flop desires two inputs, one of them is “SET”

which makes the output set and the other one is “RESET” which makes the output reset. By

linking an inverter (NOT gate) to the SR flip-flop, it can be obtained “SET” and “RESET”

operation for the flip-flop by using just one input as now the two input signals are complements

of each other. This complement prevents the ambiguity inherent in the SR latch when both

inputs are “LOW", since that state is no longer possible [11] [15].

Therefore, this single input is called the “DATA” input and if this data input is grasped

HIGH, the flip flop will be triggered “SET” and when it is triggered “LOW”, the flip flop will

change and become “RESET”. However, this would be rather pointless since the output of the

flip-flop would always transform on every pulse applied to this data input.

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To avoid this, a supplementary input called the “CLOCK” or “ENABLE” input can be used

to confine the data input from the flip-flop’s latching circuitry after the desired data has been

saved. The effect is that D input condition is only duplicated to the output Q when the clock

input is activated. This form, the basis of another sequential device called a D Flip-Flop.

The D flip-flop can be stored data that the output whatever logic level is enforced to its data

terminal so long as the clock input is “HIGH”. Once the clock input is “LOW”, the “set” and

“reset” inputs of the flip-flop are both triggered at logic level 1 so it will remain in its state and

it store whatever data was present on its output before the clock transition appeared. In other

words, the output is triggered at either logic 0 or logic 1 [11] [15].

2.3.3.3 JK Flip-Flop

J-K flip-flop is another variation on a theme of bistable multivibrators. Typically, that

flip-flop is a modified version of an S-R flip-flop with no “invalid” or “illegal” output

moreover, it can be seen from the figure 13 that how that flip-flop is accomplished:

Figure 13 : General view and the truth table of JK flip-flop

2.3.3.3.1 The J and K Inputs

What used to be the S and R inputs represent now the J and K inputs, commonly. The

old two-input AND gates have been reintegrated with 3-input AND gates, and the third input

of each gate collects feedback from the Q and not-Q outputs. What this does for us is

allowance the J input to have effect only when the circuit is reset and allow the K input to

have effect only when the circuit is set. In other words, the two inputs are meshed, to use a

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relay logic term, so that they cannot both be stimulated simultaneously. If the circuit is “set,”

the J input is reserved by the 0 status of not-Q through the lower AND gate; if the circuit is

“reset,” the K input is constrained by the 0 status of Q through the upper AND gate.

When both J and K inputs are 1, however, something unique happens. Because of the

selective inhibiting action of those 3-input AND gates, a “set” state inhibits input J so that

the flip-flop reacts as if J=0 while K=1 when in fact both are 1. On the next clock pulse, the

outputs will turn on (“toggle”) from set (Q=1 and not-Q=0) to reset (Q=0 and not-Q=1).

Conversely, a “reset” state constrains input K so that the flip-flop reacts as if J=1 and K=0

when in fact both are 1. The next clock pulse toggles the circuit again from reset to set [11]

[15].

Logical Sequence of J-K Flip-Flop

It can be seen from the figure 14 that the equivalent of the J-K flip-flop as in this sequence

can be designed in ladder logic:

Figure 14 : Truth table and ladder logic for JK flip-flop

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The end of the result is that the S-R flip-flop’s “invalid” state is ignored (along with the race

condition it engendered) and therefore, J-K flip-flop was developed.

There is no such thing as a J-K latch, only J-K flip-flops. Without the edge-triggering of the

clock input, the circuit can be triggered continuously toggle between its two output states

when both J and K were grasped high logic level 1, making it an astable device instead of a

bistable device in that circumstance. Bistable operation can be conserved for all combinations

of input states therefore, edge-triggering must be used for toggle operation only when the one

step (clock pulse) was known in a time [11] [15].

The Block Symbol for J-K Flip-Flops

The block symbol for a J-K flip-flop is a whole lot less daunting than its internal circuitry,

and just like the S-R and D flip-flops, J-K flip-flops show up two clock varieties (negative

and positive edge-triggered) and it can be seen from the figure 15 [11] [15].

Figure 15 : General view of the JK flip-flop

2.3.3.4 T Flip-Flop

T flip-flop is the modified version of JK flip-flop. It is gained by connecting the same input

‘T’ to both inputs of JK flip-flop. It works with only positive clock transitions or negative clock

transitions. It can be seen from the following figure 16 the circuit diagram of T flip-flop.

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Figure 16 : General view of the T flip-flop

This circuit has T input and the clock input also it has two outputs which are Q(t) and Q(t)’.

The operation of T flip-flop is similar to JK flip-flop moreover, it can be considered the inputs

of JK flip-flop as J=T and K=T in order to appropriate the modified JK flip-flop for 2

combinations of inputs. So, it can be ignored the other two combinations of J and K, for which

those two values are complement to each other in T flip-flop [11] [15].

2.3.3.5 Counter

The counter is a sequential circuit which is used for a counting the pulses in electronics.

The counter is the widest application of flip-flops that is a group of that logic functions with a

clock signal applied. The counters can be seen generally in two types which are;

• Asynchronous or ripple counters

• Synchronous counters

Asynchronous or ripple counters

The logic diagram of a 2-bit ripples up counter is shown in figure 17. The toggle (T) flip-flop

was used to design the asynchronous counters on the other hand, J-K flip-flop can be also used

with connecting the J and K permanently to the logic level 1. External clock is used for the

clock input of flip-flop A, and QA output is applied to the clock input of the next flip-flop i.e.

FF-B [11].

19

Figure 17 : The logic diagram of the 2-bit ripples up counter

Synchronous counters

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a

counter is called as synchronous counter.

2-bit Synchronous up counter

It can be seen from the figure 18 that logic 1 is applied to the JA and KA inputs of FF-A. This

means that FF-A will work as a toggle flip-flop. The JB and KB inputs are linked to QA.

Figure 18 : Logic diagram of the 2-bit synchronous up counter

20

2.3.4 Combinational Logic

2.3.4.1 Combinational Logic Circuit Definition

The combinational logic circuits or time-independent logic circuits in digital circuit theory

can be described as a type of digital logic circuit enforced by using Boolean circuits, where the

output of logic circuit is a pure function of the present inputs only. The combinational logic

circuit operation is spontaneous, and these circuits do not have the memory or feedback loops.

This combinational logic is in contrast distinguished to the sequential logic circuit in which

the output depends on both present inputs and also on the previous inputs. Therefore, it can be

said that combinational logic does not have memory, whereas sequential logic stores previous

input in its memory. Thus, if the input of combinational logic circuit changes, then the output

also changes [11] [15].

Figure 19 : General view of the combinational logic

Combinational Logic Circuits are created from basic logics such as NAND, NOR or NOT

gates that are connected or linked to support more complicated switching circuits. These logic

gates are the main blocks of combinational logic circuits. An example of a combinational circuit

is a decoder, which converts the binary code data present at its input into a number of different

output lines, one at a time producing an equivalent decimal code at its output.

Combinational logic circuits are very simple or very complicated moreover, any

combinational circuit can be enforced with only NAND and NOR gates as these are classed as

“universal” gates.

The three main paths of specifying the function of a combinational logic circuit are;

21

• 1. Boolean Algebra

This algebraic expression can be used for the operation of the logic circuit for each input

variable either True or False that results in a logic “1” output.

• 2. Truth Table

A truth table represents the function of a logic gate by supporting a concise list that shows

all the output states in tabular form for each possible combination of input variable that the

gate could encounter.

• 3. Logic Diagram

This is a graphical representation of a logic circuit that shows the wiring and connections of

each individual logic gate, showed by a specific graphical symbol, that creates the logic

circuit moreover, all three of these logic circuit representations are shown in below [11] [15].

Figure 20 : General view of the boolean algebra, truth table and logic diagram

As combinational logic circuits are created from individual logic gates only, these logical

functions can also be examined as decision making circuits and combinational logic is related

with combining logic gates together to operate two or more signals in order to generate at least

one output signal according to the logical function of each logic gate. Common combinational

circuits built from individual logic gates that carry out a desired application consist of the

Multiplexers, De-multiplexers, Encoders, Decoders, Full and Half Adders etc.

22

2.3.4.2 Classification of Combinational Logic

Figure 21 : General view of the classification of combinational logic

One of the most common uses of combinational logic function is in Multiplexer and De-

multiplexer type circuits besides, multiple inputs or outputs are linked to a common signal line

and furthermore, logic gates are used to clear up an address to pick up a single data input or

output switch.

A multiplexer includes two separate components, a logic decoder and some solid-state

switches. For more detail about the combinational logic, such source can be used to research to

learn [11] [15].

23

3. CHAPTER 3

3.1 Library Descriptions

3.1.1. Modelica Standard Library

It is a free library from the Modelica Association to create model mechanical (1D/3D),

electrical (analog, digital, machines), magnetic, thermal, fluid, control systems and hierarchical

state machines. Moreover, numerical functions and functions for strings, files and streams are

included [13].

Package Modelica is a free library that is developed together with the Modelica language

from the Modelica Association, and it is also called Modelica Standard Library. It provides

model components and standard component interfaces from many engineering domains. Each

model comes with documentation included. The generous license conditions allow the usage of

the software in commercial products [10] [13].

The usage of that software library requires a simulation environment that such an

environment, already includes the Modelica standard library. It is possible that the demo version

of the financial tools will not allow to simulate non-trivial examples from the library.

That version of the Modelica Standard Library contains:

• 1288 component models and blocks,

• 402 example models, and

• 1227 functions

that can be used directly.

24

Models

The Modelica Standard Library consists of many different domains which is useful for users,

specific libraries inside of it. This section supports an overview of each of these domains and

considers how models in each domain are coordinated [10] [13].

Blocks

The Modelica Standard Library consists of a collection of models for building causal, block-

diagram models. The descriptions for these models can be found in

the Modelica.Blocks package. Examples of components that can be found in this library

include:

• Input connectors (Real, Integer and Boolean)

• Output connectors (Real, Integer and Boolean)

• Gain block, summation blocks, product blocks

• Integration and differentiation blocks

• Deadband and hyteresis blocks

• Logic and relational operation blocks

• Mux and demux blocks

The Blocks package includes a wide variety of blocks for carrying out operations on signals.

These blocks are generally used for describing the function of control systems and strategies

[10] [13].

Electrical

The Modelica.Electrical package includes sub-packages specifically have connection with

analog, digital and multi-phase electrical systems. It also contains a library of basic electrical

machines by the way. In this library, it can be found the components like:

• Resistors, capacitors, inductors

• Voltage and current actuators

• Voltage and current sensors

• Transistor and other semiconductor related models

• Diodes and switches

• Logic gates

25

• Star and Delta connections (multi-phase)

• Synchronous and Asynchronous machines

• Motor models (DC, permanent magnet, etc.)

• Spice3 models

Mechanical

The Modelica.Mechanics library consists of three main libraries which are;

Translational

That library involves component models used for modeling one-dimensional translational

motion. This library includes components like:

• Springs, dampers and backlashes

• Masses

• Sensors and actuators

• Friction

Rotational

The rotational library contains component models used for modeling one-dimensional

rotational motion. This library includes components as follows:

• Springs, dampers and backlashes

• Inertias

• Clutches and Brakes

• Gears

• Sensors and Actuators

MultiBody

That library includes component models used for modeling three-dimensional mechanical

systems [10] [13]. This library consists of components like:

• Bodies (including associated inertia tensors and 3D CAD geometry)

• Joints (e.g., prismatic, revolute, universal)

• Sensors and Actuators

26

Fluids and Media

There are two packages in the Modelica Standard Library related with modeling fluid systems.

The first is Modelica.Media which is a library of property models for various media as follows:

• Ideal gases (based on NASA Glenn coefficient data)

• Air (dry, reference, moist)

• Water (simple, salt, two-phase)

• Generic incompressible fluids

• R134a (tetrafluoroethene) refrigerant

These property models support functions for figure out fluid properties like enthalpy, density

and specific heat ratios for a variety of pure fluids and mixtures [10] [13].

Moreover, Modelica Standard Library also contains the Modelica.Fluid library which is a

library of components to illustrate fluid devices, for example:

• Volumes, tanks and junctions

• Pipes

• Pumps

• Valves

• Pressure losses

• Heat exchangers

• Sources and ambient conditions

Magnetics

The Modelica.Magnetic library contains two sub-packages. The first one is

the FluxTubes package which can be used to construct models of lumped networks of magnetic

components. This consists of components to show the magnetic characteristics of basic

cylindrical and prismatic geometries as well as sensors and actuators. The other is

the FundamentalWave library which is used to model electrical fields in rotating electrical

machinery.

27

Thermal

The Modelica.Thermal package includes two sub-packages:

HeatTransfer

The HeatTransfer is for modeling heat transfer in lumped solids. Models in this library are used

to create lumped thermal network models using components as follows:

• Lumped thermal capacitances

• Conduction

• Convection

• Radiation

• Ambient conditions

• Sensors

FluidHeatFlow

Normally, the Modelica.Fluid and Modelica.Media libraries should be used to model thermo-

fluid systems because they are eligible to handle a wide range of problems involving complex

media and multiple phases. However, for a certain class of simpler problems,

the FluidHeatFlow library is used to create simple flow networks of thermo-fluid systems [10]

[13].

The general view of the Modelica Standard Library which is used in the OpenModelica

Connection Editor (OMEdit) tool, can be seen from the figure 22.

Figure 22 : General view of the Modelica Standard library in the OMEdit tool

28

3.1.2. Modelica IndustrialControlSystems Library

The package “Industrial Control Systems” is a library that is developed with the Modelica

language and supports a set of continuous and discrete control systems. That library can be used

to arrange or duplicate for many industrial controllers [13].

The first version of the library has been presented at the 9th Modelica conference, held in

Munich 3-5 September 2012. The library won the 2nd prize at the Modelica library competition

award [13].

The general structure of the Industrial Control Systems library can be seen from the figure

23. It is easy to understand the general idea and also it is so user-friendly for the users.

Figure 23 : General view of the IndustrialControlSystems library

The library is organized into sub-packages; a list of the major ones is given as follows:

• Logical: that contains all logical elements, timers, counters, and so forth.

• MathOperations: including the necessary operators for real and integer numbers

(which is some- times very useful to correctly represent the operation of some industrial

blocks).

• LinearSystems: where some blocks are enclosed that can be used to easily close loops

29

to test controllers. Part of those blocks are also associated to well-known controller

benchmarks, this sub-package is provided basically for convenience and to obtain a

self-contained library, but many alternatives can be used [6].

• Controllers: where both modulating and logic control blocks are represented, in three

basic (and interchangeable) manners:

• (a) as continuous- time equations, (b) as equations but evolving by events, and (c) when

multiple assignments could not be avoided, although research to solve this is underway

as algorithms.

• Applications: that contains a quite large set of examples to better understand and use

the library.

Figure 23 shows an overview of the library structure. Readers that are familiar with control

systems and control theory will easily get familiar with the library and its structure (just by

observing the library components); non-experienced user can find further details into the

included documentation [6].

Interfaces

Figure 24 : Interface for a generic controller. The in-

put/output connector evidenced in yellow are always

present, the other ones can be conditionally selected.

30

Name Description Conditional?

SP Set Point NO

PV Process Variable NO

CS Control Signal NO

TR Track Reference YES

TS Track Signal YES

Bias Bias signal YES

ATreq Automatic Tuning request YES

Table 1: This table contains the definition of the interface of a generic controller with its

conditional in- put/output connectors.

Each model/block/controller contained into the Industrial Control Library can be linked

with other models’ ones through its standard connectors, defined in the Modelica Standard

Library. In each sub-package, a partial interface model has been defined in order to develop the

readability of the code and reduce as much as possible the number of code lines spent for

nonspecific purposes. Figure 24 represents the interface of a generic controller. The

input/output connectors of such a block can be conditionally selected through various boolean

flags as shown in table1. With these conditional connectors a controller can be used even if it

does not use all its features, without connecting dummy inputs to it and thus increasing the

clarity of the control scheme. The interfaces and the variables of the models have been named

according to the standard terminology in the field of control systems [6].

3.1.3. Modelica Trials Library

It is a model library that consists of logical functions for users who will use the Modelica

software with OpenModelica Connection Editor (OMEdit) tool, and it also supports to model a

control function in an efficient way. The library can be used to design the logical circuits and it

was designed with using OMEdit tool [13].

This package provides a background for users how to control the logical operations, and it

can be added to the IndustrialControlSystem Library for arranging or duplicating the many

industrial control functions precisely. It was designed based on Modelica software rules and it

was used some operations from the Modelica Standart Library to model the logical functions in

efficiently.

31

The library contains one sub-package and inside, there are logical operations that have been

tested. The list of the major ones is given as follows;

• Trials: that contains logical functions which are Flip-Flops, Counters and Sequencer

and each logical operations have the test model.

Under the Trials package, the logical functions with the test models are given as follows;

• FF_SR (Set-Reset Flip-Flop), test_FF_SR

• C_SR_FF (Clock Set-Reset Flip-Flop), test_C_SR_FF

• D_FF (D Flip-Flop), test_D_FF

• JK_FF (JK Flip-Flop), test_JK_FF

• T_FF (T Flip-Flop), test_T_FF

• Asyn_counter_down (Asynchronous counter down), test_asyn_counter_down

• Syn_counter_down (Synchronous counter down), test_syn_counter_down

• Sequencer, test_sequencer

The general view of the Trials library in the OpenModelica Connection Editor (OMEdit)

can be seen from the figure 25. The users who are familiar with the programming, can

understand the general idea of the library, and they can use it easily.

Figure 25 : General view of the Trials library in OMEdit tool

32

It was used same operations from the Modelica Standard Library to design a model. These

operations are connected to the each of the Modelica libraries and it can be used to design any

in kind of a model and also in any kind of a Modelica package. Less code and less line will be

used to create any kind of model thanks to that connection and that will increase the adaptivity

of the model in the software.

It can be seen from the figure 26 that FBD (Functional Block Diagram) standard has been

chosen to represent the logical functions moreover, two Boolean Inputs and two Boolean

Outputs were used for that specific model from the Modelica Standard Library. Figure 26 is an

example of the one model which is included in the Trials library.

Figure 26 : An example of one model in Trials library

For designing that specific model, it was used some basic codes that includes equation part

and algorithm part. First of all, it has been created a model package to model that specific logic

function with using OMEdit tool. It has been explained at the beginning part that Modelica is

an equation-based software therefore, it is needed to define the equations at the beginning part

or during the inside of the code moreover, it should be used an algorithm operation for coding

to work properly and cyclically.

Our purpose is the triggered the events thus, it was used “when” operation to doing that in

the algorithm part and also equation part was defined before the algorithm part. It can be seen

from the figure 27 that the users who are familiar with programming can easily understand the

logic of the code.

33

Figure 27 : An example of a code for that model

Some of the sources such as the main one “BooleanPulse”, which is include in the Modelica

Standard Library were used for testing each model moreover, BooleanStep was also used in

same of the cases. For that specific model, also BooleanPulse source was used and that source

was given to the inputs thanks to that, outputs were observed. It can be seen from the figure 28

that the logic of the testing for that specific model.

Figure 28 : An example of simulation for that model

The Trials Library was created with following some rules which are;

• Creating a model file in OMEdit tool

• Designing each model based on standards

• Coding and testing each model

34

4. CHAPTER 4

4.1 Simulations and Results

4.1.1. Set-Reset Flip-Flop

The simulation result for the Set-Reset Flip-Flop can be seen from figure 29. The general

idea of the result is that when the Set is triggered the output signal that is called Q1 which is

equal the first output of the Set-Reset Flip-Flop then, must be triggered as well. When the reset

signal occurred, the Q1 signal must be false furthermore, the second output which is called Q’

is always equal to negative of Q1 output. For the simulation result of Q’ will be a reverse signal

of the Q1.

Figure 29 : Simulation result for the Set-Reset Flip-Flop

35

4.1.2. D Flip-Flop

The period of the clock signal was arranged quite high because of the D input signal. The

aim of arranging that signal high is to catch the false case of the output signal which is called

Q1. The general idea is that when the D input signal is triggered with the Clock signal then the

Q1 signal must be triggered as well otherwise Q1 signal must be in false. The result can be seen

in figure 30.

Figure 30 : Simulation result for the D Flip-Flop

36

4.1.3. JK Flip-Flop

The simulation result for the JK Flip-Flop was shown in figure 31. The idea is that when

the clock signal is triggered and at the same time J input signal is true and the K input signal is

false, then Q1 output signal should be true furthermore, when clock signal is triggered and at

the same J input signal is false and K input signal is true, then Q1 should be false. When both J

and K inputs are true and at the same time the clock signal is triggered then, the flip-flop must

do the toggle operation.

Figure 31 : Simulation result for the JK Flip-Flop

37

4.1.4. Clocked Set-Reset Flip-Flop

The simulation result for the Set-Reset Flip-Flop can be seen from figure 32. The general

idea of the result is that when the Set is triggered with the Clock signal, the output signal that

is called Q1 which is equal the first output of the Set-Reset Flip-Flop then, must be triggered as

well. When the reset signal occurred, the Q1 signal must be false furthermore, the second output

which is called Q’ is always equal to negative of Q1 output. For the simulation result of Q’ will

be a reverse signal of the Q1. The only difference from the Set-Reset Flip-Flop is that it has

only the Clock signal.

Figure 32 : Simulation result for the Clocked Set-Reset Flip-Flop

38

4.1.5. T Flip-Flop

The simulation result for the T Flip-Flop can be seen from figure 33. The point of that result

is to see the toggle operation by looking the output signals. When the clock signal is triggered

and at the same time the T input signal is true then, T Flip-Flop must do the toggle operation

and Q1 signal must change from true to false or vice versa.

Figure 33 : Simulation result for the T Flip-Flop

39

4.1.6. Sequencer

The simulation result for the Sequencer can be seen from figure 34. The general idea of the

simulation is that the output signals must follow each other. To get this result, the clock signal

must be triggered and the input signal which is Enable (EN) must be true furthermore, the mode

function which exists in the Modelica software was used [14].

Figure 34 : Simulation result for the Sequencer

40

4.1.7. Asynchronous Counter Down

The simulation result for the asynchronous counter down is shown in figure 35. The main

idea of this simulation is to count down from 3 to 0 because it was used 2 D flip-flop moreover,

Q’ which is the negative of the Q output is also used for counting down. It can be increased the

counting number (7-0, 15-0 etc.) according to the number of the flip-flops. When both signals

are true with the Clock signal, the counting number will be 3 and the rest will go down according

to the Clock signal and it will repeat itself cyclically.

Figure 35 : Simulation result for the Asynchronous Counter Down

41

4.1.8. Synchronous Counter Down

The simulation result for the synchronous counter down can be seen from figure 36. The

main idea of this simulation is to count down from 3 to 0 because it was used 2 JK flip-flop

moreover, Q’ which is the negative of the Q output is also used for counting down. It can be

increased the counting number (7-0, 15-0 etc.) according to the number of the flip-flops. When

both signals are true with the Clock signal, the counting number will be 3 and the rest will go

down according to the Clock signal and it will repeat itself cyclically.

The main difference between counting-up and counting-down is that the negative output

which Q’ is used to count furthermore, Q’ is also used for connecting the 2 or many flip-flops

in the Modelica software.

Figure 36 : Simulation result for the Synchronous Counter Down

42

5. CHAPTER 5

5.1 Conclusion

In this thesis, it was studied a model library to implement the logical functions such as Flip-

Flops, Counters and Sequencer to the Modelica software library with using OMEdit tool. Each

logical function has been designed with using IEC 61131-3 standard which includes FBD

(Functional Block Diagram). Aside from this, Modelica Standart Library was also used to

design the logical functions. Testing part which each model has, for the logical functions have

been done and simulated so far and the results for the simulating part was compared in the truth

tables and output signal graph which the all logical functions have.

The general idea for designing that model library is to add in the IndustrialControlSystems

library which includes in Modelica software. For the future work it can be developed to

implement that library to the IndustrialControlSytems library.

To sum up, the work that has been done so far, as follows;

• Creating model library

• Designing the logical functions

• Modeling and testing the logical operations

For the future work;

• Implementing the Trials library to the IndustrialControlSystems Library

• Testing and simulating that library.

43

6. CHAPTER 6

6.1 REFERENCES AND BIBLIOGRAPHY

REFERENCES:

[1] Miltiadis, T. (2014). Representation of PLC Ladder Diagrams in Modelica Language.

(Master thesis, Politecnico di Milano). Retrieved from: [https://www.politesi.polimi.it/]

[2] Mani P., Prasanna M. (2016). Automatic Test Case Generation for Programmable Logic

Control Using Function Block Diagram. ICICES2016. ISBN: 978-1-5090-2552-7

[3] Bolton, W. (2016). Programmable Logic Controllers. Burlington, MA: Newnes/Elsevier.

pp. 454-481.

[4] CX-Programmer Operation Manual SFC, CX-Programmer Operation Manual. (2018).

[ebook] OMRON Corporation Industrial Automation Company. Available at:

[https://assets.omron.eu/downloads/manual/en/r149_sfc_getting_started_guide_en.pdf]

[Accessed 5 Jun. 2018].

[5] Luciano B., Gianni F., Alberto L., Matteo R. (2012). Flexiable Logic-based Co-simulation

of Modelica Models. (Beijing, China), Access Number: 12997542

[6] Marco B., Alberto L. (2012). A Modelica Library for Industrial Control Systems. (Munich,

Germany), DOI: 10.3384/ecp12076477

[7] Martin B. (1999). Programming PLCs using Sequential Function Chart. (University of

Nijmegen). Retrieved from:

[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.48.8416&rep=rep1&type=pdf]

[8] Marcin J., Dariusz R. (2013). Automatic Connections in IEC 61131-3 Function Block

Diagrams. (Federated Conference on Computer Science and Information Systems), Access

Number: 978-1-4673-4471-5, pp. 463-469.

[9] Karl H. J., Michael T. (2001-2003). IEC 61131-3 Programming Industrial Automation

Systems. Springer: Berlin, Germany. pp. 240. Retrieved from:

44

[http://www.dee.ufrj.br/controle_automatico/cursos/IEC611313_Programming_Industrial_Au

tomation_Systems.pdf]

[10] Tiller, M. (2015). Modelica by Example. [ebook]. Retrieved from:

[http://book.xogeny.com/]

[11] Learn about Electronics - Sequential Logic, Combinational Logic. (2007-2018).

Retrieved from: [http://www.learnabout-electronics.org//Digital/dig50.php]

[12] Openmodelica.org. (2015). Welcome to OpenModelica - OpenModelica. [online]

Available at: https://www.openmodelica.org/ [Accessed 7 Dec. 2018].

[13] Modelica.org. (2015). Modelica and the Modelica Association — Modelica Association.

[online] Available at: https://www.modelica.org/ [Accessed 7 Dec. 2018].

[14] Infosys.beckhoff.com. (2016). Beckhoff Information System – German - FB_Sequencer.

[online] Available at: https://infosys.beckhoff.com/ [Accessed 7 Dec. 2018].

[15] www.electronics-tutorials.ws. (2014). Sequential Logics. [online] Available at:

https://www.electronics-tutorials.ws/ [Accessed 10 Nov. 2018].

45

BIBLIOGRAPHY:

Bolton, W. (2016). Programmable Logic Controllers. Burlington, MA: Newnes/Elsevier. pp.

454-481

Karl H. J., Michael T. (2001-2003). IEC 61131-3 Programming Industrial Automation Systems.

Springer: Berlin, Germany. pp. 240.

Tiller, M. (2015). Modelica by Example. [ebook]

CX-Programmer Operation Manual SFC, CX-Programmer Operation Manual. (2018).

[ebook]. OMRON Corporation Industrial Automation Company.