Mobile Robot Path-planning Implementation in Software and ...wseas.us/e-library/conferences/2007corfu/papers/540-165.pdf · Virtex BlockRAMs or in an external dynamic RAM). All components

Mobile Robot Path-planning Implementationin Software and Hardware

LUCIA VACARIU, FLAVIU ROMAN, MIHAI TIMAR,TUDOR STANCIU, RADU BANABIC, OCTAVIAN CRET

Computer Science DepartmentTechnical University of Cluj-Napoca

26-28 Baritiu Str., Cluj-NapocaROMANIA

http://www.cs.utcluj.ro/

Abstract: Search algorithms represent a useful and reliable technique in solving path finding, path planning andobstacle-avoidance types of problems that appear in mobile robots applications. The paper presents differentimplementations, both in software and in hardware, of the Breath-First (BF) Search Algorithm. The softwareimplementation uses the standard type Intel Pentium 4 Processor and Java software environment. We alsoimplemented the search algorithm in a hardware-based environment, built upon Xilinx FPGA coretechnologies. The comparison shows that the hardware implementation is an alternative to the classicalsoftware implementation that is a larger resources and time consumer.

Key-Words: Mobile Robot, Path-planning, Search algorithms, FPGA, VHDL

1 IntroductionThe mobile robots need a control system fornavigating in an environment [1]. A component ofthis navigation control system is the planning of thepath the robot must follow. The path planningsystem determines the current position of the robotin the path, when the Start and the Goal position areknown, with respect to the same reference system inthe environment where the robot navigates. Theenvironment is static or dynamic, with discrete orcontinuous representation.

To obtain the optimization of the path planning itis necessary to avoid obstacle collisions and toprovide the shortest way or the shortest time fromStart Point to Goal Point. With respect to this, thereare different path planning implementations [2].

The search algorithms represent a useful andreliable technique in solving path-finding, path-planning and obstacle-avoidance types of problems.BF (Breath-First), DF (Depth First), A-staralgorithms are successfully used to determine avalid path [3]. The characteristics of thesealgorithms allow them to be well fitted into mobilerobots applications.

The diversity of applications for mobile robotsand the diversity of environments where theynavigate require in path planning a large amount ofcomputer resources.

Another alternative to software implementationof algorithms is the use of digital devices Field

Programmable Gate Arrays (FPGA) with very goodperformances in the processing capacity [4]. Thereconfigurable logic devices may be used forrepetitive and very much time consumingoperations. Plus, the reconfigurable hardwareprovides great flexibility [5].

We used the BF algorithm to obtain the path of amobile robot that navigates in a given staticenvironment. We implemented and optimized thealgorithm both in software and in hardware. Weobtained results which prove that the executiontimes of the algorithm in hardware are much betterthan in software, using tests on the sameenvironments.

The paper is structured as follows: section 2deals with the overall description of BF usedalgorithm and its software implementation. Section3 explains the hardware implementation chosen forthe algorithm and presents the tests andexperimental validation of the hardwareimplementation. Section 4 reports the comparativeresults obtained in the two implementations, andsection 5 presents conclusions and ideas for futurework.

2 Software ImplementationWe used the Breath-First Search Algorithm toobtain the valid path for a mobile robot thatnavigates in a given static and discrete environment.

Proceedings of the 6th WSEAS International Conference on Signal Processing, Robotics and Automation, Corfu Island, Greece, February 16-19, 2007 140

2.1 Breath-First Search AlgorithmThe BF is a search facility developed in order tofind a path from a certain point to another, in anenvironment which can be always a more or lessparticular representation of a (Nodes, Vertices)Graph [3].

The Breath-First is a technique for searching andreturning a path from a given Starting Point to agiven Goal Point. The algorithm guarantees findinga solution, if there exists one. As for the complexity,it is a linear algorithm with respect to the number ofconsidered nodes, while the way it searches is basedon maintaining a queue of all neighbors found to beaccessible through means of vertices until the Goalis reached. Keeping a similar queue, in which foreach node we keep the one from which our nodewas found as neighbor, does the reconstruction ofthe path.

We chose to use a typical, bidimensional,discrete environment, most often represented as amatrix of squares (cells), and denote the positions ofthe cells using the combination of the twocoordinates. This way, the environment presents thecells as Nodes, and we consider the Vertex to berepresented by the neighbors in the 4 directions (N,S, W, and E). There is no connection on diagonals(Fig.1).

Fig.1 Neighbors scheme

The matrix contains free spaces, obstacles, theStarting Point (S) and Goal Point (G). It is assumedthat the matrix is closed, bordered by obstacles(Fig.2).

Fig.2 Sample matrix

Given a random map that respects the criteria

mentioned above, a Starting Point and a Goal Point,the implementation of the Breath-First Search willreturn (if there exists) a valid path between the twopoints. The path will be marked, assuming that onecan pass only through the free spaces and thedirections of motion are only the ones stated. Thealgorithm is presented in Listing 1.

Listing 1. BF Search Algorithm

The reconstruction of the solution is done bymeans of a special routine, which takes the list ofprevious elements and reconstructs the visited pointsof the map (Listing 2).

Listing 2. Reconstruction of path

2.2 Implementation in SoftwareFor the software implementation and experiments,we have chosen Java as Integrated DevelopmentEnvironment. The implementation required Object-Oriented techniques, Graphical User Interface andData/Maps saving and exporting, the Java compilerand emulator [6], and the Eclipse IDE [7].


The procedure to measure the time interval inwhich the algorithm runs was to capture the systemtime and to compute the difference of the valuesbefore and after the execution of the algorithmroutine (Listing 3).

Listing 3. Execution time computing

We performed various tests including manuallygenerated maps, random maps and small to largemaps. We observed that the running time increasessignificantly for large maps. Each increase in thelength of an assumed square matrix produces a 2nd

order polynomial increase in the number of cells andspreading of the algorithm queue (which is thenumber of cells included in the queue but that arenot on the path). Results prove very fast times andvery short paths (80% of the times optimal) forsmall matrices (Fig.3).

Fig.3 Result of BF Search

For very large dimensions of maps (e.g. 200x200cells) we could not test the algorithm because theprogram required more virtual memory forprocessing than the operating system could give it.This is one of the limitations of the softwareimplementation, another one being that for evenlarger maps (e.g. 1000x1000), the memory isinsufficient even to hold the map data.

Also, a comparison table has been generated,based on the obtained results. The lower thespreading is, the shorter the time becomes. The timeis given in milliseconds.

Table 1. Software BF Implementation Results

3 Hardware ImplementationOur hardware-based environment is built uponXilinx FPGA core technologies, which is the well-known developing technology in reconfigurable-based computing functionalities.

3.1 Hardware environmentFor the hardware implementation, we chose fromthe FPGA family, a Xilinx Virtex 2Pro Board(XC2VP30-FF896-6), manufactured by DigilentInc. The board is equipped with VGA-output, usedfor visualization of test results on the monitor. Itrequired Xilinx ISE 8.1 Environment [9], which wasused for VHDL code synthesis, implementation andboard programming.

A series of adaptations of the BF algorithm hadto be done, in order to exploit the logic resources ofthe Virtex FPGA device. The input matrix is storedin BlockRAMs. Depending on the space available inthe FPGA device, the process memory can beimplemented inside or outside the chip (in theVirtex BlockRAMs or in an external dynamicRAM).

All components have been described inparameterizable VHDL code. Thus, the designbecomes portable on any hardware support system.

3.1.1 Design of componentsThe hardware solution is based on a structuraldescription with component-style design. It usesinterconnected components, each of themperforming a certain task. The most importantcomponent is the BF component, which implementsthe algorithm (Fig.4).

Fig.4 BF Component top view


The signals interact with the required memoryfor applying the BF algorithm, while some of thesignals (clock, solve as inputs and ready as output)are signals that belong to the hardwareconfigurations and interconnections.

The MarkPath component is the one thatimplements the reconstruction of the path after thealgorithm has been applied (Fig.5).

Fig.5 MarkPath Component

In hardware, no values initialization is madeautomatically, therefore it is required that before anyalgorithm is applied, the system is brought to aknown state, which must be the initial state of thealgorithm. Every signal must be initialized, and thememory map also. Therefore, we have designed acomponent that deals with all these and with otherclock synchronization and enable / ready types ofsignals. The component is called CentralUnit(Fig.6).

Fig.6 Central Unit Component

One of the components required for theintegrated system to work is the CopyMemcomponent, which reinitializes the matrix for thealgorithm. This matrix will be usable for futureimplementation of other algorithms too (Fig.7).

Fig.7 CopyMem Component

All these components are gathered into a largerone, which is a relatively simple Finite StateMachine (FSM). This component supervises by its 4states (Standby, Init, BF, and Path) the system’stasks.

The VGA module contains the necessary signalsto synchronize the output on a regular monitor, itcaptures the value from the matrix and it outputs thecolor corresponding to the matrix value (Fig.8).

Fig.8 VGA Component

The block represents the VGA controller thatprovides the image on an 800x600 pixels screendisplay. It uses a 65 MHz clock and 60 ± 1 Hzrefresh. This block generates the CRT-based HS andVS timing signals, and the R, G, B video datasignals.

3.1.2 Integrated system designThe architecture of integrated system has beendesigned as the collection of components, connectedto each other by signals, and with a few processesthat handle the necessary synchronizations,command all the components, acquire signals fromboard inputs, and send data to outputs (monitor)(Fig.9).


Fig.9 Integrated system

3.2 Testing and performance of hardwareimplementation

The hardware implementation was tested severaltimes using different maps, the same that were usedfor the software implementation.

The results were photographed after thealgorithm execution.

At the beginning, the report of the Xilinxsynthesis process shows that the system can work ata maximum frequency of 185 MHz. We also testedthe performances of our hardware implementationusing the testing environment ModelSIM XE III 6.1from Xilinx [10]. The waveforms generated helpedus in choosing the working. We decided to starttesting at 120 MHz frequency.

The images taken from the hardwareimplementation of the BF algorithm present theobtained map on the monitor. On the map, the pathfound and the dispersion are in the left side, and thedirections chosen at each point, are in the right side.Fig. 10 to 14 show different map dimension used toverify that the BF algorithm obtains a valid path andto check how much time is required for that.

Figures prove that the algorithm performs verywell in terms of path optimality, even if thespreading is almost every time very large.

Table 2 and Table 3 presents samples ofalgorithm execution times (in µs) in our hardwareimplementation at the 120 MHz and 150 MHzworking frequency.

Fig.10. Result for 10x10 map dimension






Table 2. Hardware BF Implementation Results at120 MHz working frequency

Table 3. Hardware BF Implementation Results at150 MHz working frequency

The memory available in FPGA Virtex devicesallows the implementations of large matrix (e.g.100x100). Our maps use variable dimensionmatrices. Even for large maps, the FPGA circuit isused only at a small fraction of its capacity. But a lotlarger maps cannot be stored into the BlockRAMs,considering the fact that we also need to keep themap of chosen directions, to be able to reconstructthe path. For these situations, an external DynamicRAM memory can used.

4 Comparison ResultsThe different results between the two kinds ofimplementation appear especially for the run time ofthe algorithm. Generally, all of the measured timeswere at least two orders of magnitude better inhardware than in software.

By increasing the working frequency of thehardware clock, the execution time diminishesproportionally.

For very small dimension maps the softwareimplementation is preferable because the time issmall enough and the implementation is easy. Forlarge dimension maps the hardware one ispreferable because of much better running times.

The memory size used for maps in hardwareimplementation can be limited only to the amount ofBlockRAM memory available in the Virtex devices.If a larger size memory is necessary, it can beimplemented outside the chip, but in this case theworking frequency will obviously be smaller thannow.

The board with FPGA digital device is proper touse for mobile robot applications. It is now possibleto take over a part of the necessary control system ofthe mobile robot skills.

5 ConclusionOurs results demonstrate that the hardware-levelsolution for path-planning algorithmsimplementations is much faster and proves to be aserious alternative to usual software solutions.

The development of such hardwareimplementations remains quite difficult because ofthe lack of standards and the need to focus on everysingle detail of the implementation, normal for sucha low-level approach.

Software implementations though provideflexible solutions, easy to implement, manage andmaintain, and easy to modify, but much slower.

In our future research, we intend to makehardware implementations for other known path-planning algorithms, also based on the agent-oriented paradigm, and to use them for mobile robotnavigation.

References:[1] Siegwart, R., and Nourbakhsh, IR. Introduction

to Autonomous Mobile Robots, The MIT Press,2004.

[2] Arai T., Pagello, E., and Parker, LE. Advancesin Multi-Robot Systems, IEEE Transactions onRobotics and Automation, Vol.18, No.5, 2002,pp. 655-661.

[3] Cormen, TH., Leiserson CE., Rivest, RL.Introduction to Algorithms. The MIT Press andMcGraw-Hill, 1990.

[4] Cret, O., Mathe, Z., Grama, C., Vacariu, L.,Roman, F., Darabant, A. Solving the MaximumSubsequence Problem with a Hardware Agents-based System. WSEAS Transactions onCircuits and Systems, Vol.5, No.9, 2006, pp.1470-1478.

[5] Katz, RH., and Borriello G. ContemporaryLogic Design. Benjamin Cunnings/AddisonWesley Publishing Company, 2005.

[6] The Java API, java.sun.com/reference/api[7] The Eclipse IDE, www.eclipse.org[8] Digilent XUP/V2P board documentation,

www.digilentinc.com[9] The Xilinx ISE 8.1 Environment,

www.xilinx.com/support[10] ModelSIM XE III, www.model.com


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Mobile Robot Path-planning Implementation in Software and ...wseas.us/e-library/conferences/2007corfu/papers/540-165.pdf · Virtex BlockRAMs or in an external dynamic RAM). All components