Mobile Platform

SKKU 휴대폰학과 © 조준동 2008 1

조 준 동 2008.1

1

Mobile Platform

SKKU 휴대폰학과 © 조준동 2008 2 2

발표순서• Why Platform-based Design?• S/W configurable platform 의 필요성• Mobile Platform


플랫폼 (Platform)

인터넷 사회에서는 무엇인가 할만한 틀 (frame, 즉Platform) 만 제공해주면 사람들이 몰려들어 그 도구를 이용해 새로운 가치를제공하는 멋진 것을 만들어 냄 .

Linux, wikipedia, eBay, Amazon, 싸이월드 ,…

In computing, a platform describessome sort of framework, either inhardware or software, which allowssoftware to run – in Wikipedia

Platform : ' 평평한 장소 ' 라는프랑스어에서 생겨난 단어


Definition of Platforms?

•An architecture that is designed for an application domain


Motivation

• 개인의 다양한 욕구• 상품의 life-cycle 의 감소• 무선통신 서비스의 중요성 증대• 단말기의 소형화 , 경량화 , 저가격화 , 고성능화• 온 - 칩 통합화 (system on chip) 를 통한 개발기간의 단축 및 경쟁력 제고 를 위한

설계 방법론과 검증 방법의 등장


Mobile System Complexity

DigitalCellular• Voice• Email• Photos• Web• ~100kbps data• GPRS/ EDGE• CDMA 2000 1X

Wide-BandDigitalCellular• Video• M-pixel cam.• 3D• 300kbps ~14Mbps• UMTS, HSDPA• CDMA 1X EVDO

Wide-Band Network• Ubiquitous data• Flexible Spectrum use• Enhanced apps.• 100Mbps-1Gbps• OFDM

Wide-BandDigital Cellular• Video• High-end gaming• 100Mbps, 10msec Flexible bandwidth•

• All IP Network• Super 3G/LTE• OFDM (MIMO)• Wibro/WiMAXAnalog

Cellular• Voice• AMPS,TACS

DigitalCellular• Voice• Pager• 10kbps data• GSM, TDMA• CDMAOne


Challenges of Mobile SoCs

• Low power and high performance– Omni-directional efforts

• Whenever possible, power is off/reduced as long as the performance requirements are met

• Short time-to-market– Extensive re-use of design components

• Platform-based design is one of solutions


SoC and Customizable Platform Based-Design

ReconfigurableHardware

(Coarse Grain)ASIC 1

DSP Reconfigurabl

eHardware

(Fine Grain)ASIC 2

ControllerCPU

RAMROM

Flash

?

ControllerCPU

RAMROM

Flash

?


Platform-Based Design• Platform

– Hides unnecessary details– Targets a range of applications– Composed of basic building blocks including processors and communication

fabrics

IP Blocks

RTLBlocks

SWModels

cluster

abstract DSP MPEGCPUDMA

C MEM I O

Processor IPs

DMADSPCPU MPEGMEM

Bus and other IPs

BUS

Platform

IP-based design

Platform-based design

Productivity increase


Platform 분류• Application Platform:

– 멀티미디어 platform: Nexperia, TI 의 OMAP – 3G 무선 platform: Infineon 의 M-gold – Bluetooth platform: Parthus– 무선 platform: ARM 의 PrimeXsys

• Process-centric platform– Improv System, ARC, Tensilica, Triscend

• Communication-centric platform:– Sonics, Palmchip


최근 연구동향• Intel’s Reconfigurable Radio Architecture. (mesh + nearest neighbor)• Reconfigurable Baseband Processing, Picochip• Portable Components using Containers for Heterogeneous Platforms,

Mercury Computer Systems, Inc.• A configurable Platform, Altera, Excalibur, Xilinx Virtex FPGA• Adaptive Computing Machine, Quicksilver Tech.• Mercury, Sky, Galileo, Tundra (crossbars, bridges)• Virginia Tech’s reconfigurable hardware


66% chips are not OK on first silicon (2004)

Mid-90s – 6 months late = > 31% earnings lossToday 3 month late = $500M loss


HIERARCHY OF PLATFORMS


Full Application Platform• users design full applications on top of hardware an

d software architectures • Nexperia• Texas Instrument's OMAP multimedia platform• Infineon's M-Gold 3G wireless platform,• Parthus' Bluetooth platforms• ARM's PrimeXsys wireless platform


processor-centric platform • focus on access to a configurable processor but doe

sn't model complete applications • Improv Systems• ARC• Tensilica• Triscend


communication- centric platform • interconnect architecture but doesn't typically provid

e a processor or a full application • Sonics' SiliconBackplane • PalmChip's CoreFrame architectures.


fully programmable platform • consisting of FPGA logic and a processor core • Altera's Excalibur, Xilinx' Virtex-II Pro and Quicklogi

c's QuickMIPS • Xilinx-IBM XBlue architecture


SoC Platform Adaptation


The Platform-Based Design Concept Cadence

ApplicationSpace

HW-SW Kernel

MEM

FPGACPU Processor(s), RTOS(es)

and SW architecture

*IP can be hardware (digital or analogue) or software. IP can be hard, soft or‘firm’ (HW), source orobject (SW)

Scaleablebus, test, power, IO,clock, timing architectures

+ Reference Design

Programmable

SW IP

Hardware IP

Pre-Qualified/VerifiedFoundation-IP*

Foundry-SpecificHW Qualification

Reconfigurable Hardware Region(FPGA, LPGA, …)

SW architecturecharacterisation


Platform Architecture

How fast will my user interface

software run? How much can I fit onto my microcontroller?

Which Bus? PI? AMBA?Dedicated Bus for DSP?

Which RTOS do I use? Which scheduling policy do I have to choose ?

Do I need a dedicated DSP ?Which micro-

controller? ARM?HC11? ARC?

Can I buy a QCELPdecoding core?

Do I need a dedicatedHW or can I run this

on the Microcontroller ?


Example of a commercial SoC

More CPUs?More SRAM/Flash?Add FPGA?


Today’s Wave: Mobile - Digital Today’s Wave: Mobile - Digital ConvergenceConvergence

Broadcasting

TelematicsImage Processing

Computing

CommunicationEntertainment

• Smart Mobile Phone – A Variety of Smart Mobile Phone – A Variety of FunctionsFunctions

• Mobile DevicesMobile Devices• Center of Ubiquitous Media NetworkCenter of Ubiquitous Media Network• Driver for Semiconductor IndustryDriver for Semiconductor Industry


Case Study: 노키아 N95


Case Study: 노키아 N95


미래의 모바일 컴퓨팅

Mudge et al:

• 실시간 처리 이동 슈퍼 컴퓨팅– Speech recognition, Cryptography.– Augmented reality.

• 16 개의 Pentium-4 필요– 2004 Intel P4 @3GHz; 55M TR’s 122mm2 0.09u – 2014 20GHz 0.03u

• 저전력을 만족하면서 고성능 – requires (massive) parallelism– Multi-processor systems– Subsystem integration


모바일 플랫폼 구조


플랫폼 계층 및 구분 • Level 0: Foundation Platform

– Infrastructure & standards : Basic Arch.• Processor core, Peripheral/Interface IP, Bus: e.g., ARM PrimeXsys

• Level 1: Application specific Integration Platform• Application Specific SoC: HW & SW• Mobile Platform, Home Platform

• Level 2: System Platform• Terminal Platform• Handset case: RF + Modem + AP + Memory + MMI


플랫폼 구조 예 (Scalable Multi-processors)


차세대 휴대 단말플랫폼- 기존 3G 셀룰러 및 Wibro 에서 Mobile TV 기능을

흡수지원 : DMB 별도 시장과 경합

- PC 와의 컨버젼스 경향- 안테나 : MIMO 지원을 위한 안테나 수 증가 + cellular, DMB

안테나 별도 존재 (need Convergence)- 배터리 : Killer application 일수록 전력 소모 증가 (need low powe

r consumption)- Form factor: 칩 개수 증가 : 칩 셋 통합 (RF, Memory, Baseband

Modem, Power Management IC, ….)


Networks-on-Silicon, PhillipsAlbert van der Werf, Philips Research


모바일 플랫폼 개념적 구조


Mobile Platform Interoperability (Qualcomm)


WiPi : (Wireless Internet Platform for interoperability)


재구성 가능한 플랫폼

MicroProcessor(Run-timeconfigu-ration

control)

Bootable LoadPROM/PLD

HOSTProgram

Con

f igur

atio

nco

ntro

lcod

eRA

MReconfigurable

Array of ProcessingElements

Interface(formation/interpretation)

I/OC

ontr

olle

r

Inte

rfac

e

Processing status info.

Oth

erDi

gita

lSig

nalP

roce

ssin

gbl

ock

Configurationinformation

MicroProcessor(Run-timeconfigu-ration

control)

Bootable LoadPROM/PLD

HOSTProgram

Con

f igur

atio

nco

ntro

lcod

eRA

MReconfigurable

Array of ProcessingElements

Interface(formation/interpretation)

I/OC

ontr

olle

r

Inte

rfac

e

Processing status info.

Oth

erDi

gita

lSig

nalP

roce

ssin

gbl

ock

Configurationinformation


SDR Configuration• Modulation Format

– QPSK– DQPSK– /4 DQPSK– {16,64,256,1024} QAM– OFDM– OFDM CDMA

• Digital Down/Up Conversion (DDC)– Channel Center– Decimation/Interpolation rates– Compensation Filters– Matched Filter = {0.25,0.35,...}

• FEC– Convolutional– Reed-Solomon– Concatenated Coding– Turbo CC/PC– (De-)Interleave

Soft RadioDigital Signal

Processing Engine

• Network Interface Definition

• Channel Access– CDMA– TDMA

• Security• Beam Forming

• DSSS– Rake, track, acquire– Multi User Detect. (MUD)– ICU


다중 Radio 통합• 다양한 응용 서비스에 따라 다중 모드 / 다중 밴드

Radio 기술의• 통합이 요구됨


개방형 인터페이스 : MIPI

노키아 , TI, STMicro, ARM 등이 주도하는 MIPI (Mobile Industry ProcessorInterface) 표준이 더 빠르고 다양한 범위의 인터페이스 표준 채용을 촉진


Mobile Platform

CPU(ARM)

OS Protocol stack, device driver, library, API

Voice Modem

Bus

• GSM/GPRS/EDGE/WCDMA/HSDPA/HSUPA

• CDMA/CDMA2000 1x/EV-DO/EV-DV

DSP(Teak, TeakLite, StarCor

e)

GPS

RF I/F

Modemcore

Interface IPs

Interface IPs

CPU(ARM)

OS Protocol stack, device driver, library, API

Data Modem

Bus

• SDMB/TDMB/DVB-H

• WIBRO

RF I/F

Modemcore

Interface IPs

Interface IPs

Security


FPGA Platform for Voice Modem

SCom5700ES FPGA Board

제어 보드 (CPU, Peripheral)

Modem보드 (Rx/Tx)


FPGA Platform for Data Modem

PC SMC120

# 1

SDAB1000 Testbed 구성도

Scom5010

FPGA TFTLCD

FlashROM SRAM

Keypad

#1 SDAB1000 Main FPGA Board#2 SDAB1000 Control Board#3 RF&ADC board#4 ADC board#5 DAG Board#6 SMC120 board

담당자 :

CODEC

SDABFPGA1

SDABFPGA2

SDABFPGA3

SRAM32M(221*16- bit)

FPGA USB module

SDRAM

SDRAM

# 5

# 6# 2

담당자 : RSP

담당자 :담당자 :

송신 장비 ADC

# 4

담당자 :

RF & AD

# 3

담당자 :

PCI interface


공통된 통합 Modem Platform

WCDMA Modem SOC

CDMA2000 Modem SOC

Phase #1 – Multi Device

MCU DSP

WCDMA Modem HW Core

Macro#2Macro#1

Macro#3 Macro#4

Macro#n Macro#m

MCU DSP

CDMA2000 Modem HW Core

Macro#5Macro#4

Macro#6 Macro#7

Macro#k Macro#m

WCDMA/CDMA2000 Modem SOCPhase #2 – Device Integration

MCU DSP

WCDMA Modem HW Core

Macro#3Macro#1 Macro#2

Macro#4

Macro#n

CDMA2000 Modem HW Core

Macro#7Macro#5 Macro#6

Macro#k Macro#m

Phase #3 – Unified Platform

MCUDSP

Macro#z

DSP

RP RP RPMacro#m


Software-Defined Radio (SDR) Platform

MemoryController

CPUBridge

RP

Backbone BUS – Multi-Layer

Peripheral BUS

Application specific Efficient processor engine Filter/Correlator/ACS/FFT … 51GOPS 350mW

DDR / DDR-2

System BUS(Display, Camera, etc.)

Peripheral BUS-A

System Memory IF(FLASH / ROM / SRAM)

DSP DSP

High-Throughput Low Latency: Real Time 처리

RP RP

RTOS/Protocol stack 수행 Middleware JAVA acceleration L1 / L2 Cache, MMU ARM11 440MHz 220mW

L0 control PHY algorithm serial portion Symbol rate processing Vocoder/Stereo dec. 11GIPS 550mW

RP

High Data Transfer Rate Efficient Scheduling Low Latency AXI/AHB Bus ~2.5GB/sec

Peripheral BUS-B

ACS: Add-Compare-Select UnitAHB: Advanced High speed BusAXI: Advanced eXtensible Interface


SDR Platform

WiBro

Products

Target System

CPU

GSM/GPRS

M/M

SDR Modem

IPs DSPs

RPs


Virtual Platform– A function-accurate and cycle-approximate hardware mode

l in SystemC or C++ whose abstraction level is much higher than register transfer level (RTL)

– 500x ~ 1000x faster simulation speed than RTL• 정량적 data 를 활용한 system analysis 가능

– Code size is usually 1/5~1/3 of its corresponding RTL model• Less mistake/error, higher productivity

– uses a C-level simulator• Rich debugging feautures including stop/break are pro

vided Easy to debug

Fast (system) architecture exploration and optimization is possible


Verification Platform with ARM and DSP-based Multi-processor Architecture of DVB-T Baseban

d Receiver


2 Teak DSP Platform


Configuration of crossbar switch


A crossbar switch cell

in_data0

in_dada1

out_data0

out_data1

Switch control=0

in_data0

in_dada1

out_data0

out_data1

Switch control=1


CI-controller State Diagram


CI-controller State Diagram (Continued)


CI controller simulation waveform


of DVB-T Baseband Receiver


Hardware-software co-design flows


A shared memory structure and hardware-software partitioning


Functions of DVB-T Baseband Receiver mapped at Multi-processor platform


TeakDSP Platform hardware/software co-verification using Mentor Graphics Seamle

ss CVETM


Scheduling for dual processor implementation


Frequency offset compensator hardware


Fine and Coarse Frequency Synchronizer (Beek & Classen)


FFT block diagram


Equalizer hardware block diagrams


a) “Power on” or “Channel change”: Initial symbol synchronization and frequency

synchronization; b) “After completing system synchronization”: Equalization


Performance evaluation of each functional block of DVB-T baseband receiver

Functional

Block / Processing

Types

Frequency Compensator & Guard removal

Classen Beek

FFT

Equalizer

Software - 2.3ms 1.5ms 280ms 15ms

HW/SW Co-design 172us 230us 28.5us 175.1

us 210us


Extended multi-processor platform


DVB-T baseband Receiver Scheduling I using Multi-processor Platform


DVB-T baseband Receiver Scheduling II using Multi-processor Platform


Performance evaluation Processing Types / Functional Block

SW SW & HW

(Teaks + ARM + HW IP)

HW(IP) only MAL

Frequency compensator & Remove Guard - 182.5us 13.8us 10.5us

Fine Freq. sync. (Beek) - 56.3us 1.5us 7.8us

Symbol Timing Recovery 144 us - - 5.2us

FFT - 188.9us 38.6 us 13.6us

Coarse Freq. Sync. (Classen) - 241us 3.3us 11us

Scattered Pilot Detection 46.5us - - 3.3us

Equalizer - 219.5us 11.2us 9.5us

De-mapping 19.9us - - 4.9us


Task Chart of Multi-processor platform for DVB-T baseband receiver


Task Chart of Multi-processor platform for DVB-T baseband receiver


맺음말• (Mobile) SoC 의 complexity 및 cost 의 증가로 platfo

rm 을 이용한 설계 프로세스 중요

• Mobile platform 의 challenge 로 low power, RF I/F 를 포함한 검증 , variety of standards, platform optimization 제시

• 여러 platform 및 methodology 의 장단점을 취한 platform 개발이 바람직

• HW/SW/algorithm 을 이해하고 설계할 수 있는 인재(system architect) 육성


퀴즈 사용자 중심의 모바일 플랫폼 구조를 개발하기 위한 플랫폼 설계 경향이 아닌 것은 ?

1. 플랫폼 계층 및 구분2. Mobile Platform Interoperability3. 재구성 가능한 플랫폼4. Software defined radio 플랫폼

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Mobile Platform