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Stephen Sunter
Mixed-signal testing, DFT, and BIST: Trends and Principles
Engineering Director, Mixed-Signal
Silicon Test Solutions
June 2010
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Introduction
More analog functions being implemented digitally— But analog circuitry still increasing in SoCs bottleneck for TTM
Analog testing is a battle— Noise is the enemy
– From overhead, in the power rails … di/dt– Either side, by capacitive coupling … dv/dt– Down below, in the substrate …… leakage– Deep inside each transistor …… thermal
— No general, systematic DFT techniques ad hoc, chaos
— Insufficient analog in ATE is preventing more multi-site test
Analog BIST is an amazing challenge— Design it faster, more accurate than fastest, most accurate design— Many analog designers don‘t believe it‘s possible
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Outline
Trends in process and design— Poor matching; Digital shrinking faster; PLL and SerDes
Trends in analog testing— Digital-only ATE; Multi-site; RF
Trends in design for test— Systematic techniques; RF DFT; Analog BIST
Principles of analog BIST— How can/does it work?
To get a copy of presentation: [email protected]
EDN Jan. 2010
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Outline
Trends in process and design— Poor matching; Digital shrinking faster; PLL and SerDes
Trends in analog testing— Digital-only ATE; Multi-site; RF
Trends in design for test— Systematic techniques; RF DFT; Analog BIST
Principles of analog BIST— How can/does it work?
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Trends in process and designDigital density
Function density improving faster for digital than analog— Digital transistors shrinking by Moore‘s law— Analog transistor shrinking limited by linearity, matching
– 4 years behind
1970 1975 1980 1985 1990 1995 2000 2005 2010
Source: Intel
Transistors
10B
1 Billion
100M
10M
1 Million
100K
10K
1K
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Trends in process and designDigital density
Result: Digital versions of analog functions— More flexible, reconfigurable, programmable— Characteristics different than analog (e.g. spurious tones in jitter)
Example: all-digital PLL— PFD Time-to-digital converters— Loop filter Sigma-delta techniques— VCO DAC + DCO
(on/off current sources + LC tank, adjustable C)
Integrator Digital LPF
TDC
DCODigital Controlled Osc.
+
_FCW
Freq. Control Word
FOUT
Charge pump
PFD RC filter VCOFIN
E.Temporiti et al, ―Insights into Wideband Fractional All-Digital PLLs for RF Applications‖, CICC 2009
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Source: Gelsinger, ISSCC 2001
Power for 1 cm2 IC (W) Sun’s surface
Nuclear reactor
Hot plate
Rocket nozzle
Source: Khakifirooz, ESSDRC 2008
Active
Leakage
Trends in process and designParameters
Increasing Power density and Temperature— Circuit characteristics can change while testing
IDDQ increasing 10X per CMOS generation [ITRS 2009]— Decreasing ability to detect defects using IDDQ tests
Source: IBM, 2002
1kW/cm2
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0
1
2
3
4
250 180 130 90 65 45 32 22 15
CMOS generation (nm)
Trends in process and designParameters
VDD/VT ratio decreasing— Increasing sensitivity to
power rail noise
Reliability decreasing— Burn-in increasingly unsuitable
– Burn-in rooms require cooling!
— Negative-bias temperature instability (NBTI)– Increases magnitude of PMOS threshold voltage over time– Need continuous performance adjustment: adaptive– Need continuous performance test: parametric BIST
VDD/VT
VDD
VT
Source: Khakifirooz & Antoniadis, ―MOSFET Performance Scaling – Part II: Future Directions‖, IEEE Trans. on Electron Devices, June 2008
You are here
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Trends in process and designMatching
Transistor matching unreliable— For transistor lengths <100 nm— More digital self-calibration: more transistors— More testing to achieve same fault coverage
– Scan for digital portion, and structural test for analog portion
Arrays of identical transistors have significant variation— More parameters to test— Variation in threshold voltage
– Affects offset
— Variation in effective channel length– Affects gain
— Variation in back-bias effect– Affects linearity
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Trends in process and designPLL
More PLLs on each IC (2~20) — Used for controlling phase delay; higher on-chip clock frequencies
Jitter decreasing— 0.5~2 ps rms is common (despite power rail noise; LC vs delay line)
50% duty cycle more important at higher clock rates— Especially for dual edge logic (e.g. DDR memory, latch-based logic)
All-digital PLLs— For software defined radio— Extremely fine frequency resolution and fast lock times
External test becoming impractical — Too many PLLs— I/Os too slow, add jitter, distort duty cycle
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0
500
1000
1500
2000
2500
3000
3500
4000
4500
0 0.01 0.1 1 10 100 1000
Trends in process and designSerDes
Rent‘s rule: # signal pins = C∙NP
— C = terminals per transistor = 3— N = transistor count— P = 0.25~0.35
SerDes is industry‘s choice to reduce pin-count— Fewer pins 90% reduction— Lower power (P=fCV2) constant f× CPIN but 5x lower VSWING
— More noise tolerant differential signals subtract interference— Less EMI radiation cancels in differential signals— Faster less SSN (from constant current drivers)
Serializ
er
Pins
M Transistors
0.35
0.30
0.25
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Trends in process and designSerDes
Comparing SerDes signals to parallel, single-ended signals— Clock embedded in data need PLL/CDR to receive— 10X smaller voltage swing more sensitive to voltage offset— Jitter 10X more significant may need to test— Protocol standards (PCIe, USB, …) bit insertion/deletion— Equalization (filtering) analog
— Non-deterministic
Need analog test methods, especially if >3 Gb/s— Wire properties dominate jitter >5 Gb/s, and therefore equalization
b0
b1
bN
Serializ
er
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Trends in process and designSerDes
Serial rates increasing
Jitter (RJ) 0.5~2 ps rms— Typically too low to
test in production
Equalization — Essential >4 Gb/s— Continuous time, and discrete time— Adaptive: Feedforward (FFE), Decision Feedback (DFE)— Deterministic jitter affected by ATE interface and equalization setting
Gb/s Commodity Mainstream In design
Consumer <3 3~7 8
Networking <5 5~8 8~20
Telecom <10 10~20 >20
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Outline
Trends in process and design— Poor matching; Digital shrinking faster; PLL and SerDes
Trends in analog testing— Digital-only ATE; Multi-site; RF
Trends in design for test— Systematic techniques; RF DFT; Analog BIST
Principles of analog BIST— How can/does it work?
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Trends in analog testingIntroduction
Analog test cost and effort much greater than for digital— ―AMS circuitry typically occupies 20% of the area but incurs 70% of
the test cost and 45% of the DFT/test effort‖Karim Arabi, Senior Engineering Director, Qualcomm ITC 2009, VTS 2010
Improvements for analog are improvements for whole IC— DFT— Test generation— Characterization— Test time
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Trends in analog testingDigital ATE for AMS
Digital-only ATE— Cheaper than mixed-signal ATE— Has more channels than MS ATE: e.g. >1000 vs <32— More of them on production floor
Using digital ATE for mixed-signal ICs— Lower cost per test-sec.— Enables multi-site (most effective way to reduce test cost)— Easier production scheduling
Requires different test techniques— Conversion to/from analog on interface board— Measure only DC voltages— Apply square waves— Built-off self-test (BOST)
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Trends in analog testingImpact of memory
Embedded memories in SoC— RAM test time = 20N~50N clock cycles (N = bits)
– 100 MHz 2~5 seconds per 10 Mb
— Some ICs have >500 Mb– 1 GHz 2~5 seconds per 100 Mb
— Flash test time >1 minute, for any size– Dominated by erase time
Industry uses multi-site testing for these ICs— Low pin-count testing almost essential— Requires contactless I/O test strategy
– Digital pins: boundary scan– Analog pins: must contact
Intel 22nm IC
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Trends in analog testingMore parallelism
Analog is slow compared to digital— Scan test time for 1M to 1B logic gates can be 1~2 seconds
– Scan chains tested in parallel– Chain length decreases when using scan compression or logic BIST– Clock rates increasing
Analog <20% of most SoCs, but >70% test time— Digital test resources mostly idle
More parallelism added to some ATE— Asynchronous clocking, parallel processing, etc.— But less so for analog
Industry wants to use multi-site testing— Analog resources in ATE limits the number in multi-site— ATE access to analog circuitry limits too
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40%
50%
60%
70%
80%
90%
100%
90% 92% 94% 96% 98% 100%
Probability IC is defect-free
Package y
ield
Trends in analog testingKnown Good Die
Driven by growth in MCM, SiP, 3D— Multiple ICs in one package— Each IC fully tested before assembling into package— Some attempts to test after adding each IC
KGD issues — Power integrity— Multi-site test (low pin-count access)— Burn-in
123
7 ICs
4
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Trends in analog testingRF
RF ICs— Very low cost, and usually have custom test setup
Ferrario et al, ―Architecting Millisecond Test Solutions for Wireless Phone RF IC‘s‖ ITC 2002 (Best Paper)
— Very few transistors, low price, high volume– Adding DFT is generally uneconomic
RF in SoC— Reduces system cost and power
– SiP and 3D are alternatives
— Problem for design, but opportunity for DFT – Can use DFT, BIST that would not be practical in RF IC– Indirect test methods
– DC bias voltages– Total power– Abhijit Chatterjee, Georgia Tech.; Sule Ozev, Arizona State Univ.
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Outline
Trends in process and design— Poor matching; Digital shrinking faster; PLL and SerDes
Trends in analog testing— Digital-only ATE; Multi-site; RF
Trends in analog design-for-test— Systematic techniques; RF DFT; Analog BIST
Principles of analog BIST— How can/does it work?
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Trends in DFT Systematic methods
Loopback
Analog test bus
1149.1
1149.4
1149.6
P1149.8
P1687
Structural test
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Trends in analog DFTLoopback
Multiple pathsSerDes example
— Serial data path
— Parallel data path
PRPG
BERT
Source: Altera
BERT
PRPG
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Trends in analog DFT Loopback
Multiple pathsSerDes example
— Reverse serial data path(Pre or post CDR)
— Reverse parallel data path
Source: Altera
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Trends in analog DFT Loopback
Advantages— Minimal area and performance impact— Required by some standards
– Modem– SerDes
Disadvantages— Non-diagnostic— May not detect compensatory faults
– e.g. high gain output low gain input
Solutions– Between transmitter and receiver, insert:
– Offset voltage (Degang Chen et al)– Filter (Jacob Abraham et al)– Mixer (Sule Ozev et al)
– Compare measurements with/without inserted change
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Trends in analog DFT Analog test bus
Advantages— Brings internal analog signals to a pin
Disadvantages— Capacitive loading affects CUT— Capacitive coupling to adjacent circuitry adds noise— Leakage current of access transistors limits number of nodes— Limited bandwidth : 1/2(RCUT+RSWITCH)CBUS
— Analog buffer affects offset, linearitySolutions
– Use pre-tested ADC or buffer
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Trends in analog DFT 1149.1 “JTAG”
―IEEE Standard Test Access Port and Boundary-Scan Architecture‖
Advantages— Standard test access (TAP) for all test data, control— Widely used for automated IC and board testing— Timing insensitive
Disadvantages— 4 or 5 pins dedicated to test access
– Mostly-analog ICs have few digital pins, no scan
— Test access bottleneck for billion-gate ICSolutions
– Compliance-enable pin to allow reuse of system pins– System bus to convey test data to embedded TAP– System pins for parallel scan data– BIST to minimize test data
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Trends in analog DFT1149.4 “Analog boundary scan”
―IEEE Standard for a Mixed Signal Test Bus‖
Advantages— Standard test access for analog signals— Access to board signals without contacting them
Disadvantages— Lack of automation— On very few product ICs, and only for internal access— Long analog bus on IC limits bandwidth, voltage, currentSolutions
– Analog BSDL standard nearing completion– Creative use of LF analog bus
– DC references for comparators– On-chip undersampling
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Trends in analog DFT 1149.6 “ACJTAG”
―IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks‖
Advantages— Diagnoses defects in differential and AC-coupled board signal paths— Low frequency test access to high frequency signals on board— Broad acceptance in industry for SerDes pins, to >10 Gb/s— No analog changes to SerDes transmitters
Disadvantages— Requires analog changes to receiver pin circuitry— Complex to understand: a digital solution to an analog problemSolutions
– Implement with assistance from experienced EDA suppliers– Use SerDes receivers that are 1149.6-ready
Connected to each AC-coupled/differential
input pin
Connected to boundary scan cells
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Trends in analog DFT P1149.8.1 “Atoggle”
Proposed ―IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components‖
Advantages— For testing IC connections to empty sockets, passives, non-BS ICs— Adds only a few logic gates to standard boundary scan cell— Diagnoses differential signal paths without changes to RX or TX
Disadvantages— Requires pins to be bidirectional (facilitates contactless test)— Only helps board test, with capacitive sense ATE
Board under test
Mounting block
in top cover Buffer
Spring posts
Sense Plate
DUT
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Trends in analog DFT P1687 “IJTAG”
Proposed ―IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device‖
Advantages— Standardizes access to on-chip test capabilities— For IC and board test— Simplifies automated test generation
Disadvantages— Usually requires changes to existing BIST and DFT circuit designs — Not widely understoodSolutions
– Implement with assistance from experienced EDA suppliers
D Q
TCKShift
Update
From TDI
To/from “child” scan path
1
0
Instrument A
D Q D Q D Q
1
0
Instrument B
D Q To TDOD Q
1
0
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Trends in analog DFT Structural test
Apply non-function stimuli until targeted defects tested— vs DOT (defect-oriented test): test specs to detect structural defects
Proven solution in digital test— Enabled ATPG, BIST automated, faster tests— Enabled easier diagnosis higher yield
Tougher in analog— No analog fault model to show equivalence to functional test
Compromise: function-like patterns, spec-based defects— Examples
– Apply linear ramp to ADC– Transmit clock-like pattern from SerDes to measure RJ
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Trends in analog DFT Fault modeling
―Impossible‖
Source: Dalal et al, ―A Layout-Driven Yield Predictor and Fault Generator for VLSI‖,IEEE Trans. on Semiconductor Manufacturing, Feb 1993
Fault simulation— Major roadblock: some companies persevering, but no standard
Equivalent to stuck-at: opens, shorts between node pairs— Most time-consuming simulation— Saving simulation time
– Short = 1 Ω (instead of range)– Open = 1 MΩ (instead of infinite)– Only simulate possible shorts
— Weight by likelihood of occurrence (spacing and process dependent)
Equivalent to delay fault: excess parametric deviation— Depends on design margin relative to specifications— Saving simulation time
– Only variations greater than process specification (function independent)– Only variations in principal parameters (W, L, tOX, …)
— Weight by likelihood of occurrence (using PDF of variation)
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Trends in analog DFT RF
RF DFT— Hot area for university research (as digital DFT research decreases)
Measure wideband power using power detector (rectifier)— Assumes all AC power caused by stimulus (sine or PRBS)— High input impedance, DC voltage output— Diode
– DC coupled– Single-ended
— NMOS– AC coupled– Differential
Source: Zhang et al, ―Low Cost RF Receiver Parameter Measurement with On-chip Amplitude Detectors‖, Proc. of VTS, 2008
VDC
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Trends in analog DFT PLL BIST
Typically test only lock time— Reset IC, wait lock time, then test logic clocked by PLL
Built-in parametric test: delay line-based jitter test— Limited by jitter in delay line— Limited by delay steps – can use CDF, and calibrate points of interest
DPLL— Permits testing more functionality via scan— Lock times of a few microseconds – harder to verify
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Trends in analog DFT SerDes BIST
Simple digital BIST: standard loopback PRBS, no jitter test— <3 Gb/s: typically lots of margin for mature IP
Built-in parametric test: phase interpolator-based (analog)— Using function‘s comparator
– RX and TX must have same ref. frequency
— Using shadow comparator– Does not test function‘s comparator
Macro-ext. parametric test: undersampling-based (digital)— Unlimited time resolution analysis, without calibration
– Resolution determined by frequency offset between fRXREF and fTXREF
— Median edge detection, with clock-like bit pattern or mod. PRBS
TXTxData
fTXREF
RXRxData
fRXREF
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Trends in analog DFT ADC BIST
Apply linear ramp— ≤10 bit: typically lots of margin for mature IP— Analog circuit (constant current + capacitor)— Mostly digital circuit (sigma-delta pattern + analog filter)— Most proposals don‘t address differential or low impedance inputs— Apply digital pattern to delta-sigma front-end (bypass analog input)
Built-in parametric test: test ADC + DAC together— ≥14 bit: performance dominated by self-calibration, noise, jitter
A/D
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Trends in analog DFT DAC BIST
Stimulus easy to generate— Linear ramp from a counter— Sine from data pattern stored in RAM
Response capture very difficult— A comparator would need voltage-independent offset
Solution: use pre-tested ADC
D/A
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Digital, time-based test
Trends in analog DFT Analog BIST
Random analog— Ad hoc for regulators, comparators, …— Built-in parametric test: use ADC, DAC— Filters, op-amps: oscillation BIST— High order filters: split into lower orders
No general, systematic DFT method(like scan is for digital)— Except proposal at TVHSAC‘09 Workshop
FrequencyCounter
Test
fFILTER
fH
fOSC = fFILTER
1-fHfFILTER
Oscillates when
fFILTER(j) fH(j) = 1
CUT
Arabi & Kaminska
VREF1
VREF2
QREF2
QREF1
Duty cycle 1
Duty cycle 2
VREF
DutyCycleAmplitude =
(assumes THD < 5%)
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Analog BIST strategy
Synchronous data,
for serial or
parallel analysis
(LF sine or ramp
force/sense in ATE)
+
Analog
CUT
D Q
D Q
Programmable
counter
Spice simulate
fREF2
Analog
CUT
VREF
fREF
VAC
Spice simulate
VDC
HF
Select & fREF
US patents: 6885213Sunter, “A General Strategy for BIST of High-Speed Analog Functions”, Workshop on TVHSAC, Nov. 2009
+
fREF2
Analog
CUTVDC
LF
Shift register
pattern
Spice simulate
+
Source: Sunter, ―A General Strategy for BIST of High-Speed Analog Functions‖, TVHSAC Workshop, Nov 2009
D Q
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Outline
Trends in process and design— Poor matching; Digital shrinking faster; SerDes and RF
Trends in analog testing— Digital-only ATE; Multi-site; RF
Trends in analog design-for-test— Systematic techniques; RF DFT; Analog BIST
Principles of analog BIST— How can/does it work?
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Principles of analog BIST - Introduction
How can one circuit test another on same IC?— Implies that BIST is ‗better‘ than the CUT!
(beware of designer‘s ego)
The challenges— Design it faster, more accurate than fastest, most accurate design— Make it simpler, higher yield, and don‘t affect CUT— Make it self-testing and diagnostic
The potential benefits
7 essential principles for practical BIST— Analog or digital
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Compare to digital BIST
Key characteristics— Generate pseudo-random data— Apply to CUT via scan— Capture responses via scan— Compress result into digital signature— Compare bit-wise to correct signature
Stimulus & response: 0/1, at-speed
Gate-level functional test— Tests that output of AND gate is A & B, for various bit combinations
D Q
D Q10
10
D Q10
Source: Clive Maxfield, www.techbites.com
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What is an “analog” circuit?
Analog core, input, output— Amplifiers, filters (sampled/continuous), regulators, …— RF
Analog core, digital in or out— ADC, DAC
Analog core, digital in and out— PLL, DLL, SerDes, DDR
Digital— I/O parameters (delay, drive, leakage, VSW, SSN, …)
Output is non-deterministic— Anticipate noise— Must test that output is between upper and lower limits
Functioncore
in out
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Analog BIST challenge
Faster, more accurate— 10X
Multiple stimulus types— DC, ramp, sine
Multiple responses— May be different from stimulus— DC, ramp, sine, noise, frequency, impulse, ...
Multiple analyses— Offset, gain, linearity, rise time, jitter/noise, duty cycle, delay, …
Not understood by many analog designers— ―If your PLL BIST is so accurate, why don‘t you design PLLs?‖
Founder of analog IP company, DAC 2009
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Potential benefits of analog BIST
Faster time to market— Faster characterization (automated, pre-simulated tests)— Faster diagnosis (access to embedded IP, access in-system)
Lower test cost— Low-cost ATE (low speed, digital vs. HF mixed-signal)— Low pin-count access (cheaper probe cards, fewer ATE channels)— More multi-site (faster test time for many ICs)— More tests in parallel (faster test time for each IC)
Higher yield— Less impact on CUT (smaller loads, no transmission lines)— Low pin-count access (less contact noise)— Higher reliability (in-system test for parameter degradation)— Higher performance (test capability scales with technology,
same loading as end application)
WOW !
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7 essential principles
Test the BIST
Undersample
Subtract for accuracy
Add for precision
Higher yield than CUT
Spec-based structural tests
Deliver digital measurement, pass/fail
Necessary and sufficient
If enough tests, accuracy, precision for required DPM
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Principle 1Test the BIST
ATE is calibrated before use— Often requires many minutes, and performed once a week— Must do same for BIST, but in milliseconds, in every IC
Test the BIST— Earn the trust of designers— Use only timing-insensitive digital patterns, clocks, and DC voltages— Without high performance or mixed-signal ATE
– Would prevent many of the benefits
— If BIST uses an ADC, how is ADC tested? (if you can‘t use ATE)
Digital finite state machines of BIST tested by scan— Typically <1 millisecond
Analog is a problem— Including digital delay lines
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Principle 1Test the BIST
PLL BIST (jitter)— Measure output edge times relative to input edges, using delay line— Convert delay line into a ring oscillator, measure oscillation period— Best accuracy when measuring changes in delay
Avoid delay lines— Adds timing jitter (may be more than CUT)— Limited range (typically <256 steps)— Longer test times (increases for smaller delay steps)
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Principle 1Test the BIST
ADC BIST (linearity) — Apply linear ramp: constant current charging a capacitor
– Must test linearity and offset
— Apply two ramps to ADC, with small offset voltage for second ramp– Requires Least Squares calculation from histogram data– Can compute linearity of source (if noise, offset, signal stability <1 LSB)
– Stimulus Error Identification and Removal– Degang Chen, Iowa State Univ.
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Principle 1Test the BIST
Conclusions
Use mostly digital circuitry— Scan test is very fast, and well proven
Use simplest analog— Ensure its accuracy is almost irrelevant (see Principle 3)
– If it must be more accurate than CUT, how is its accuracy tested?
— What can be used? – R, C, buffer, transmission gate, dynamic comparator (diff‘l latch)– Variation calibrated with one measurement, or inherently subtracted
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Principle 2Undersample
BIST slower than CUT— BIST is smaller, lower power, more accurate— BIST needs time to capture, store, analyze
Example: ADC/DAC self-calibration— Low-speed ADC undersamples same signal as high-speed ADC— Low-speed ADC undersamples output of DAC— First order sigma-delta very small, but many bits of resolution
Undersampling— Definition: sampling frequency <2X highest frequency of interest— Waveform must be periodic— Widely used principle, in ATE too— ―Equivalent Time Sampling‖ in oscilloscopes
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Principle 2Undersample
Suitable for analog and digital waveforms
Equivalent time
sampling of
square wave
QOUT
Undersampling
a sine wave
fT
fS
Analyze Analyze
QOUT
or square wave
1/fS
1/fT-1/NfS
Sampling point
advances by,
say 1 ps, each
sampling clock
cycle because
sampling frequency
is offset from sine
frequency
D Q
fS
QOUTPLLOUT
1/(fT-NfS)
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Principle 2Undersample
PLL BIST (jitter)— Reference clock input samples PLL out
– Phase offset (adjustable)
— Sampling clock samples PLL out– Frequency offset
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Principle 2Undersample – Measuring time
Time offset, using adjustable delay line— Best for measuring timing of single events— Jitter in delay line increases with delay
– Limits range-to-resolution ratio (e.g. 500 ps range, 2 ps resolution)– Range and resolution shrink as technology shrinks– Can use programmable delay, or Vernier delay line
— Insensitive to frequency of events
Frequency offset, using adjustable oscillator— Best for measuring repetitive events— Jitter increases with decreasing offset (due to LF jitter, 1/f effect)
– Limits resolution, not range (example: unlimited range, .1 ps resolution)– Resolution shrinks as technology shrinks– Can use PLLs, with LC oscillators
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Principle 3Subtract for accuracy
Subtract systematic errors— Offset voltages, leakage currents— Access path delay, interference— Power supply noise (50/60 Hz, switched regulator)
Measure with and without signal, or with opposite signal— Differentially, or synchronously
Analog— Auto-zero (sample VOS, then VOS+Vin, subtract)— Correlated double sampling (sample VOS–Vin, then VOS+Vin, subtract)— Offset cancellation (sample VOS+Vout, then VOS+Vin, subtract)
Digital— Subtractor— Count up, then down
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Principle 4Add for precision
Add noise samples— Thermal noise— Pseudo-random data— Via power rail or substrate
Average multiple measurements— Precision improves by √N
Analog— Low pass filter— Integration capacitor
Digital— Adder— Counter
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Principle 5Higher yield than CUT
Economics— Logic BIST must user fewer gates than logic-under-test
– Typically 1~2% of random logic area (<1% of IC)
— Analog BIST must have more design margin than CUT
Especially important for SoC— If analog BIST uses 0.01% of area, but 2% parametric yield loss,
then equivalent to analog BIST that uses 2% of SoC area– e.g. analog BIST test chip relied on high-performance analog buffers
– Only 70% of the ICs achieved required accuracy and bandwidth!
Must be almost all-digital
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Principle 5Higher yield than CUT
How to develop BIST for miscellaneous analog functions?— Comparators, op-amps, filters, regulators, buffers, …— Area of BIST typically larger than CUT
Share one analysis block— MADBIST: DSP tests ADC, then ADC tests DAC, then test rest of IC
– Gordon Roberts, McGill Univ.
— Analog test bus– Limitations discussed earlier
Serial digital bus— 1-bit sigma-delta or undersampling— Local analog/digital conversions
fS
D Q D Q D Q To analysis
Q=0: X1=1 , X2=2
Q=1: X1=2 , X2=1
Source: Malcovati et al, Trans. CAS, Mar. 2003
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Principle 6Specification-based structural tests
Benefits of structural tests— Automated DFT — Automated test generation, with ~100% fault coverage— Automated (or fast) defect diagnosis
Digital, scan-based structural tests— Serially loaded in test mode, but applied in parallel in function mode
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Principle 6Specification-based structural tests
Analog ―structural‖ tests— Never occur in CUT‘s function mode— Examples
– Configure op-amp into oscillator, measure fOSC
– Apply PRBS stimulus to a filter, detect output zero-crossings
— Prevents correlation to specification-based parametric tests– How to ensure IC is good or bad, relative to datasheet?– How to improve yield when too many fail?– How to relax a specification test limit?
Structural test yield/quality not suitable for marginal devices— 1995 study of analog IC production testing:
Structural test OK only if lots of marginManoj Sachdev, Univ. of Waterloo (while at Philips/NXP)
— Need structural tests that apply function-like stimuli
M.Sachdev, ―A Realistic Defect Oriented Testability Methodology for Analog Circuits‖, JETTA, vol. 6, no. 3, pp. 265-276, June 1995
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Principle 6Specification-based structural tests
Need structural tests that correlate to specification tests— All elements of analog CUT may be defect-free, but circuit fails spec.— One element may be defective, but CUT meets spec.— Test circuit in function-like mode, with function-like patterns
ExamplesApply Measure
— Linear ramp to ADC DNL, INL— Square wave to ADC Aperture jitter— Clock to PLL Jitter— Clock-like bit pattern to SerDes Random jitter— Voltage step to low-order filter Phase delay
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Principle 6Specification-based structural tests
Example: SerDes BISTSerdesTest sampling resolution =
0.38ps, at 10.31232 Gb/s
y = 0.9917x - 0.0962
R2 = 0.9968
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5
SRS BERTScope (ps rms)S
erd
esT
est (p
s r
ms)
RJ
10 Gb/s
BIST sampling resolution 0.4 ps rms
TXfTXREF
RXfRXREF
BERTScope
BIST
1010
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Principle 7Deliver digital measurement and pass/fail result
Only pass/fail result— Prevents characterization, diagnosis— Prevents statistical analysis
Only measurement— Prevents using WGL— Increases test time— Prevents using zero capture-memory ATE channels— Limits choice of ATE, which affects scheduling, second sources, …
Digital output(instead of DC voltage)— Convey across IC, and out to ATE, without affecting accuracy— Requires ability to shift upper/lower digital test limits into IC— JTAG TAP permits in-system use
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Roadblocks to adoption of AMS BIST
Analog fault model— To compare old method with new— Industry work-around:
silicon, measure DPM at QC and customers
It takes time …— Make silicon— Correlate BIST tests to ―functional‖ tests— Status quo tolerable Wait until the ―crisis hits the fan‖
— Companies that sell only analog BIST eventually don‘t– Opmaxx Fluence Credence IP abandoned– Vector 12 out of business– DFT Microsystems now only sells ATE modules
Analog designers— All DFT must be added manually, by designer— Don‘t understand BIST: How can it be better than my circuit?
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Conclusions
Trends— Increasing variations, temperatures, SSN, mismatch, pin-counts— Analog functions becoming more digital, digital becoming analog— SerDes / PLL: >10 GHz, <1 ps rms, external test impractical— ADC / DAC: No successful BIST, but good attempts for ADC— Random analog: still ad hoc DFT (only one general proposal)
Drivers of change: multi-site test; analog TTM bottleneck— Flash memory, >100Mb eDRAMs, analog, in larger SoCs— Driving need for low pin-count test, systematic analog DFT, BIST
Analog BIST— Ultimate challenge, but possible using 7 principles
To get a copy of presentation: [email protected]