MIPS R-format Instructions...80386 (1985): 32-bit extension (now IA-32) ! Additional addressing modes and operations ! Paged memory mapping as well as segments s . Chapter 2 — Instructions:

Chapter 2 — Instructions: Language of the Computer — 1

MIPS R-format Instructions

n  Instruction fields n  op: operation code (opcode) n  rs: first source register number n  rt: second source register number n  rd: destination register number n  shamt: shift amount (00000 for now) n  funct: function code (extends opcode)

op rs rt rd shamt funct 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits


R-format Example

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

op rs rt rd shamt funct 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits


MIPS I-format Instructions

n  Immediate arithmetic and load/store instructions

n  rt: destination or source register number n  Constant: –215 to +215 – 1 n  Address: offset added to base address in rs

n  Design Principle 4: Good design demands good compromises

n  Different formats complicate decoding, but allow 32-bit instructions

uniformly n  Keep formats as similar as possible

op rs rt constant or address 6 bits 5 bits 5 bits 16 bits


Branch Addressing n  Branch instructions specify

n  Opcode, two registers, target address n  Most branch targets are near branch

n  Forward or backward

op rs rt constant or address 6 bits 5 bits 5 bits 16 bits

n  PC-relative addressing n  Target address = PC + offset × 4 n  PC already incremented by 4 by this time


Jump Addressing n  Jump (j and jal) targets could be

anywhere in text segment n  Encode full address in instruction

op address 6 bits 26 bits

n  (Pseudo)Direct jump addressing n  Target address = PC31…28 : (address × 4)


Addressing Mode Summary


Synchronization

n  Two processors sharing an area of memory n  P1 writes, then P2 reads n  Data race if P1 and P2 don’t synchronize

n  Result depends of order of accesses

n  Hardware support required n  Atomic read/write memory operation n  No other access to the location allowed between the read and

write

n  Could be a single instruction n  E.g., atomic swap of register ↔ memory n  Or an atomic pair of instructions

§2.11 Parallelism

and Instructions: Synchronization


Synchronization in MIPS n  Load linked: ll rt, offset(rs) n  Store conditional: sc rt, offset(rs)

n  Succeeds if location not changed since the ll n  Returns 1 in rt

n  Fails if location is changed n  Returns 0 in rt

n  Example: atomic swap (to test/set lock variable) try: add $t0,$zero,$s4 ;copy exchange value ll $t1,0($s1) ;load linked sc $t0,0($s1) ;store conditional beq $t0,$zero,try ;branch store fails add $s4,$zero,$t1 ;put load value in $s4


ARM & MIPS Similarities n  ARM: the most popular embedded core n  Similar basic set of instructions to MIPS

§2.16 Real S

tuff: AR

M Instructions

ARM MIPS Date announced 1985 1985 Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers 15 × 32-bit 31 × 32-bit Input/output Memory

mapped Memory mapped


Compare and Branch in ARM n  Uses condition codes for result of an

arithmetic/logical instruction n  Negative, zero, carry, overflow n  Compare instructions to set condition codes

without keeping the result n  Each instruction can be conditional

n  Top 4 bits of instruction word: condition value n  Can avoid branches over single instructions


Instruction Encoding


The Intel x86 ISA n  Evolution with backward compatibility

n  8080 (1974): 8-bit microprocessor n  Accumulator, plus 3 index-register pairs

n  8086 (1978): 16-bit extension to 8080 n  Complex instruction set (CISC)

n  8087 (1980): floating-point coprocessor n  Adds FP instructions and register stack

n  80286 (1982): 24-bit addresses, MMU n  Segmented memory mapping and protection

n  80386 (1985): 32-bit extension (now IA-32) n  Additional addressing modes and operations n  Paged memory mapping as well as segments

§2.17 Real S

tuff: x86 Instructions


The Intel x86 ISA n  Further evolution…

n  i486 (1989): pipelined, on-chip caches and FPU n  Compatible competitors: AMD, Cyrix, …

n  Pentium (1993): superscalar, 64-bit datapath n  Later versions added MMX (Multi-Media eXtension)

instructions n  The infamous FDIV bug

n  Pentium Pro (1995), Pentium II (1997) n  New microarchitecture (see Colwell, The Pentium Chronicles)

n  Pentium III (1999) n  Added SSE (Streaming SIMD Extensions) and associated

registers n  Pentium 4 (2001)

n  New microarchitecture n  Added SSE2 instructions


The Intel x86 ISA n  And further…

n  AMD64 (2003): extended architecture to 64 bits n  EM64T – Extended Memory 64 Technology (2004)

n  AMD64 adopted by Intel (with refinements) n  Added SSE3 instructions

n  Intel Core (2006) n  Added SSE4 instructions, virtual machine support

n  AMD64 (announced 2007): SSE5 instructions n  Intel declined to follow, instead…

n  Advanced Vector Extension (announced 2008) n  Longer SSE registers, more instructions

n  If Intel didn’t extend with compatibility, its competitors would! n  Technical elegance ≠ market success


x86 Instruction Encoding n  Variable length

encoding n  Postfix bytes specify

addressing mode n  Prefix bytes modify

operation n  Operand length,

repetition, locking, …


Fallacies n  Powerful instruction ⇒ higher performance

n  Fewer instructions required n  But complex instructions are hard to implement

n  May slow down all instructions, including simple ones

n  Compilers are good at making fast code from simple instructions

n  Use assembly code for high performance n  But modern compilers are better at dealing with

modern processors n  More lines of code ⇒ more errors and less

productivity

§2.18 Fallacies and Pitfalls


Fallacies n  Backward compatibility ⇒ instruction set

doesn’t change n  But they do accrete more instructions

x86 instruction set


Concluding Remarks n  Measure MIPS instruction executions in

benchmark programs n  Consider making the common case fast n  Consider compromises

Instruction class MIPS examples SPEC2006 Int SPEC2006 FP Arithmetic add, sub, addi 16% 48%

Data transfer lw, sw, lb, lbu, lh, lhu, sb, lui

35% 36%

Logical and, or, nor, andi, ori, sll, srl

12% 4%

Cond. Branch beq, bne, slt, slti, sltiu

34% 8%

Jump j, jr, jal 2% 0%

Chapter 3

Arithmetic for Computers

Chapter 3 — Arithmetic for Computers — 20

Arithmetic for Computers n  Operations on integers

n  Addition and subtraction n  Multiplication and division n  Dealing with overflow

n  Floating-point real numbers n  Representation and operations

§3.1 Introduction


Integer Addition n  Example: 7 + 6

§3.2 Addition and S

ubtraction

n  Overflow if result out of range n  Adding +ve and –ve operands, no overflow n  Adding two +ve operands

n  Overflow if result sign is 1

n  Adding two –ve operands n  Overflow if result sign is 0


Integer Subtraction n  Add negation of second operand n  Example: 7 – 6 = 7 + (–6)

+7: 0000 0000 … 0000 0111 –6: 1111 1111 … 1111 1010 +1: 0000 0000 … 0000 0001

n  Overflow if result out of range n  Subtracting two +ve or two –ve operands, no overflow n  Subtracting +ve from –ve operand

n  Overflow if result sign is 0

n  Subtracting –ve from +ve operand n  Overflow if result sign is 1


Dealing with Overflow n  Some languages (e.g., C) ignore overflow

n  Use MIPS addu, addui, subu instructions n  Other languages (e.g., Ada, Fortran) require

raising an exception n  Use MIPS add, addi, sub instructions n  On overflow, invoke exception handler

n  Save PC in exception program counter (EPC) register n  Jump to predefined handler address n  mfc0 (move from coprocessor reg) instruction can

retrieve EPC value, to return after corrective action

Other Adders n  BASICS of ADDING LOGIC

n  Carry-out n  Sum Generation

n  Ripple Add n  Carry Bypass n  Carry Select n  Carry Lookahead


25

The Ripple-Carry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

td = O(N)

tadder = (N-1)tcarry + tsum

FA FA FA FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

A3 B3

S3

Ci,0 Co,0

(= Ci,1)

Co,1 Co,2 Co,3

26

Carry-Bypass Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Multiplexer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

Also called Carry-Skip

27

Linear Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Ci,0

(1)

(1)

(5)(6) (7) (8)

(9)

(10)

(5) (5) (5)(5)

28

LookAhead - Basic Idea

Co k, f Ak Bk Co k, 1–, ,( ) Gk PkCo k 1–,+= =

AN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A0, B0

29

Look-Ahead: Topology

Co k, Gk Pk Gk 1– Pk 1– Co k 2–,+( )+=

Co k, Gk Pk Gk 1– Pk 1–… P1 G0 P0Ci 0,+( )+( )+( )+=

Expanding Lookahead equations:

All the way:

Co,3Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2

G3

30

Carry Lookahead Trees

Co 0, G0 P0Ci 0,+=

Co 1, G1 P1G0 P1P0Ci 0,+ +=

Co 2, G2 P2G1 P2P1G0 P+ 2P1P0Ci 0,+ +=

G2 P2G1+( )= P2P1( ) G0 P0Ci 0,+( )+ G2:1 P2:1Co 0,+=

Can continue building the tree hierarchically.


Multiplication n  Start with long-multiplication approach

1000 × 1001 1000 0000 0000 1000 1001000

Length of product is the sum of operand lengths

multiplicand

multiplier

product

§3.3 Multiplication


Multiplication Hardware

Initially 0


Optimized Multiplier (ignore) n  Perform steps in parallel: add/shift

n  One cycle per partial-product addition n  That’s ok, if frequency of multiplications is low


Faster Multiplier n  Uses multiple adders

n  Cost/performance tradeoff

n  Can be pipelined n  Several multiplication performed in parallel


MIPS Multiplication n  Two 32-bit registers for product

n  HI: most-significant 32 bits n  LO: least-significant 32-bits

n  Instructions n  mult rs, rt / multu rs, rt

n  64-bit product in HI/LO

n  mfhi rd / mflo rd n  Move from HI/LO to rd n  Can test HI value to see if product overflows 32 bits

n  mul rd, rs, rt

n  Least-significant 32 bits of product –> rd


Division (IGNORE THIS) n  Check for 0 divisor n  Long division approach

n  If divisor ≤ dividend bits n  1 bit in quotient, subtract

n  Otherwise n  0 bit in quotient, bring down next

dividend bit

n  Restoring division n  Do the subtract, and if remainder

goes < 0, add divisor back n  Signed division

n  Divide using absolute values n  Adjust sign of quotient and remainder

as required

1001 1000 1001010 -1000 10 101 1010 -1000 10

n-bit operands yield n-bit quotient and remainder

quotient

dividend

remainder

divisor

§3.4 Division


Floating Point n  Representation for non-integral numbers

n  Including very small and very large numbers n  Like scientific notation

n  –2.34 × 1056 n  +0.002 × 10–4 n  +987.02 × 109

n  In binary n  ±1.xxxxxxx2 × 2yyyy

n  Types float and double in C

normalized

not normalized

§3.5 Floating Point


Floating Point Standard n  Defined by IEEE Std 754-1985 n  Developed in response to divergence of

representations n  Portability issues for scientific code

n  Now almost universally adopted n  Two representations

n  Single precision (32-bit) n  Double precision (64-bit)


IEEE Floating-Point Format

n  S: sign bit (0 ⇒ non-negative, 1 ⇒ negative) n  Normalize significand: 1.0 ≤ |significand| < 2.0

n  Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit)

n  Significand is Fraction with the “1.” restored n  Exponent: excess representation: actual exponent + Bias

n  Ensures exponent is unsigned n  Single: Bias = 127; Double: Bias = 1203

S Exponent Fraction

single: 8 bits double: 11 bits

single: 23 bits double: 52 bits

Bias)(ExponentS 2Fraction)(11)(x −×+×−=


Single-Precision Range n  Exponents 00000000 and 11111111 reserved n  Smallest value

n  Exponent: 00000001 ⇒ actual exponent = 1 – 127 = –126

n  Fraction: 000…00 ⇒ significand = 1.0 n  ±1.0 × 2–126 ≈ ±1.2 × 10–38

n  Largest value n  exponent: 11111110 ⇒ actual exponent = 254 – 127 = +127

n  Fraction: 111…11 ⇒ significand ≈ 2.0 n  ±2.0 × 2+127 ≈ ±3.4 × 10+38


Double-Precision Range n  Exponents 0000…00 and 1111…11 reserved n  Smallest value

n  Exponent: 00000000001 ⇒ actual exponent = 1 – 1023 = –1022

n  Fraction: 000…00 ⇒ significand = 1.0 n  ±1.0 × 2–1022 ≈ ±2.2 × 10–308

n  Largest value n  Exponent: 11111111110 ⇒ actual exponent = 2046 – 1023 = +1023

n  Fraction: 111…11 ⇒ significand ≈ 2.0 n  ±2.0 × 2+1023 ≈ ±1.8 × 10+308


Floating-Point Precision n  Relative precision

n  all fraction bits are significant n  Single: approx 2–23

n  Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal digits of precision

n  Double: approx 2–52

n  Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal digits of precision


Floating-Point Example n  Represent –0.75

n  –0.75 = (–1)1 × 1.12 × 2–1

n  S = 1 n  Fraction = 1000…002 n  Exponent = –1 + Bias

n  Single: –1 + 127 = 126 = 011111102 n  Double: –1 + 1023 = 1022 = 011111111102

n  Single: 1011111101000…00 n  Double: 1011111111101000…00


Floating-Point Example n  What number is represented by the single-

precision float 11000000101000…00

n  S = 1 n  Fraction = 01000…002 n  Fxponent = 100000012 = 129

n  x = (–1)1 × (1 + 012) × 2(129 – 127) = (–1) × 1.25 × 22 = –5.0


Denormal Numbers n  Exponent = 000...0 ⇒ hidden bit is 0

n  Smaller than normal numbers n  allow for gradual underflow, with

diminishing precision

n  Denormal with fraction = 000...0

Two representations of 0.0!

BiasS 2Fraction)(01)(x −×+×−=

0.0±=×+×−= −BiasS 20)(01)(x


Infinities and NaNs n  Exponent = 111...1, Fraction = 000...0

n  ±Infinity n  Can be used in subsequent calculations,

avoiding need for overflow check n  Exponent = 111...1, Fraction ≠ 000...0

n  Not-a-Number (NaN) n  Indicates illegal or undefined result

n  e.g., 0.0 / 0.0 n  Can be used in subsequent calculations


Floating-Point Addition (IGNORE)

n  Consider a 4-digit decimal example n  9.999 × 101 + 1.610 × 10–1

n  1. Align decimal points n  Shift number with smaller exponent n  9.999 × 101 + 0.016 × 101

n  2. Add significands n  9.999 × 101 + 0.016 × 101 = 10.015 × 101

n  3. Normalize result & check for over/underflow n  1.0015 × 102

n  4. Round and renormalize if necessary n  1.002 × 102


FP Adder Hardware (ignore)

Step 1

Step 2

Step 3

Step 4


Floating-Point Multiplication (ignore) n  Consider a 4-digit decimal example

n  1.110 × 1010 × 9.200 × 10–5

n  1. Add exponents n  For biased exponents, subtract bias from sum n  New exponent = 10 + –5 = 5

n  2. Multiply significands n  1.110 × 9.200 = 10.212 ⇒ 10.212 × 105

n  3. Normalize result & check for over/underflow n  1.0212 × 106

n  4. Round and renormalize if necessary n  1.021 × 106

n  5. Determine sign of result from signs of operands n  +1.021 × 106


FP Arithmetic Hardware (ignore) n  FP multiplier is of similar complexity to FP

adder n  But uses a multiplier for significands instead of

an adder n  FP arithmetic hardware usually does

n  Addition, subtraction, multiplication, division, reciprocal, square-root

n  FP ↔ integer conversion n  Operations usually takes several cycles

n  Can be pipelined


FP Instructions in MIPS n  Single-precision arithmetic

n  add.s, sub.s, mul.s, div.s n  e.g., add.s $f0, $f1, $f6

n  Double-precision arithmetic n  add.d, sub.d, mul.d, div.d

n  e.g., mul.d $f4, $f4, $f6 n  Single- and double-precision comparison

n  c.xx.s, c.xx.d (xx is eq, lt, le, …) n  Sets or clears FP condition-code bit

n  e.g. c.lt.s $f3, $f4 n  Branch on FP condition code true or false

n  bc1t, bc1f n  e.g., bc1t TargetLabel


FP Example: °F to °C n  C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr - 32.0)); }

n  fahr in $f12, result in $f0, literals in global memory space

n  Compiled MIPS code: f2c: lwc1 $f16, const5($gp) lwc2 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra


Accurate Arithmetic n  IEEE Std 754 specifies additional rounding control

n  Extra bits of precision (guard, round, sticky) n  Choice of rounding modes n  Allows programmer to fine-tune numerical behavior of a

computation n  Not all FP units implement all options

n  Most programming languages and FP libraries just use defaults

n  Trade-off between hardware complexity, performance, and market requirements


x86 FP Architecture (ignore) n  Originally based on 8087 FP coprocessor

n  8 × 80-bit extended-precision registers n  Used as a push-down stack n  Registers indexed from TOS: ST(0), ST(1), …

n  FP values are 32-bit or 64 in memory n  Converted on load/store of memory operand n  Integer operands can also be converted

on load/store n  Very difficult to generate and optimize code

n  Result: poor FP performance

§3.7 Real S

tuff: Floating Point in the x86


x86 FP Instructions (ignore)

n  Optional variations n  I: integer operand n  P: pop operand from stack n  R: reverse operand order n  But not all combinations allowed

Data transfer Arithmetic Compare Transcendental FILD mem/ST(i)

FISTP mem/ST(i)

FLDPI

FLD1

FLDZ

FIADDP mem/ST(i)

FISUBRP mem/ST(i) FIMULP mem/ST(i) FIDIVRP mem/ST(i)

FSQRT

FABS

FRNDINT

FICOMP

FIUCOMP

FSTSW AX/mem

FPATAN

F2XMI

FCOS

FPTAN

FPREM

FPSIN

FYL2X


Who Cares About FP Accuracy? n  Important for scientific code

n  But for everyday consumer use? n  “My bank balance is out by 0.0002¢!” L

n  The Intel Pentium FDIV bug n  The market expects accuracy n  See Colwell, The Pentium Chronicles


Concluding Remarks n  ISAs support arithmetic

n  Signed and unsigned integers n  Floating-point approximation to reals

n  Bounded range and precision n  Operations can overflow and underflow

n  MIPS ISA n  Core instructions: 54 most frequently used

n  100% of SPECINT, 97% of SPECFP

n  Other instructions: less frequent

§3.9 Concluding R

emarks

Documents

MIPS R-format Instructions...80386 (1985): 32-bit extension (now IA-32) ! Additional addressing modes and operations ! Paged memory mapping as well as segments s . Chapter 2 — Instructions: