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402 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
S
m at z d el t
Harry K. Charles Jr.
d t d v a d t t l y, l d w t t a at d la a , f t a f - f a at z d l t y t
a t l xa f t t a d f t l t d v t l y t aw ll , ta t t ApL. it al l at t lat t t d a a a d w a a-
y t t d v l t f - f a y t . T t at f advd v w t -d ty a a a a t f ApL a t v tf t VT f z t t lat t at ll t . A l t t t t al f a d
t at , w d a d a d t , a d a a t f at d vf a t d. T a a d f adva d t
t f x l t at .
INTRODUCTIONm at z d l t ( l t , a t t all d) a y a l f ApL’ y t
a f at- a t t t t d v l tf t la ta y a aft. A vTechnical Digest
a t l1 l t t l y av a y xa l ft t a d a t f at z d l t att La at y. T q t w a : W a-t z d l t t l y ad d, a d w w ll ApL
a t a dly a a a f t l y? Tlay t dw t a w t q t , t
xa t f t t d a d t l al adva t at d t (ic ), l t a a , a d
y t t at .
INTEGRATED CIRCUITSs l o -ba d ic t h ology ha o t u d to
volv dy a ally f o t b g g 1958.2 Th
d t o of moo ’ Law3,4 fo d v d ty t llhold, w th th u b of o o t (a t v d vo t a to ) o a gl h doubl g v y 1.5 to2 y a , d d g o d v t h ology. A g a h al
bod t of moo ’ Law g v F g. 1. Fo xa -l , a i t l p t u 4 h o o o ( t odu d
nov b 2000) o ta d a ox at ly 55 ll ot a to ( lu oth t g at d o o t ) o a
of l o ot u h la g tha a av ag - z dg a l (≈ 80 2). Lat v o of th p t u 4
hav o ta d o tha 108 d v dual t a to ,w th th lat t i t l ita u a oa h g 53 108 d v . i o t a t, th t ic o ta d o ly ot a to a d a f w a v o o t a d wa abouto - fth th z (10.63 1.5 ). Today, o alic x t w th o tha 108 a t v d v o hl tha 100 2 a a. p ototy d v w th
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Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005) 403
miniATuriZeD eLecTronics
109 t a to hav b d o t at d; by a ly
th xt d ad , th u b of d v o t a tohould a h 1011 o la ly z d h .
A ic t l y v lv , t a d aa d v d ty w ll a . i - f -
a d v , t ta da d al - l all y tall zat , w t v
a t - t t d , al ady la d y , w t t
l t al d t v ty.5 s la ly, t - ad l t lay tw t lt lay tall zat a
la d y a at al w t l w d l -t ta t a ly d , z y l t , T - a d at al . i t f t , f t tt l a d d, a ay d a t d l -t . T at f l w t v ty (a d ta )f t a d a ’ v y l w d l t ta tw ll all w ic t at at xt ly d . W tt day’ -d ty , t ty al a w td v a d v tw d v t d
f 1000 l t . A t f d v a a t t 1010 a , w t a lta t d v z f
l t a 10–8 2, t f l t d vd t t l d t . b a f l a aa d l a , t t a a d v t f a
all q a t ty f a a t f d l a ly yt d v t l y ( la j t t a t
ld ff t t a t ) a d w ll q t d v l -t f w d v t t a d t d t
t d f l t t a t t l.6
Wide Bandgap Semiconductorsi add t t w d v t t , t -
d t at al w ll d d t add al a l -at q t . F xa l , gaA a d
-f q y a d - wa l at . it t a tay a t vd v f wav w d vd t t l t l tya d t a l ty t at at t at (a v 150°–200°c)d t t - lat avh w v , av al a
t d f lt t v at f -w d v , t tat tt f gaA t l t a100 m t a d t a ta -da d l , w a x
at ly 500 m t . T t dgaA a xt ly f a l ,
a a ly d f lt. Ta w t -t at , -
w at ay l alt -at d t a la d7 a iii- t d – a d -
10 10
1960 1965 1970 1975 1980 1985
Year
N u m
b e r o
f t r a n s
i s t o r s p e r c
h i p
1990
4004
Early MOS logic
Memory
Microprocessor1K
4K16K
64K256K
1M4M
16M64M
128M256M
512M 1G 2G 4G
80088080
8086286
PentiumPentium II
Pentium IIIPentium 4
ItaniumItanium 2
i 386
i 486
1995 2000 2005 2010
10 9
10 8
10 7
10 6
10 5
10 4
10 3
10 2
10
0
Figure 1. Moore’s Law reecting the exponential growth in transistor density on a singlechip. (i386, i486, Pentium, Pentium I, Pentium II, Pentium III, Pentium 4, Itanium, and Ita-nium 2 are all Intel Corp. trademarks.)
d a gan.8 s l a d y fa t t
at f t at al . i fa t, a - d d ly tal s c waf av ally ava la l
f t a a d ad , w l iii- t d d v ytal av w tly y t taxy f -
t at a a s c. s iii- twt a x v , av l t d a l
al d t la -v l d t , a d d lat v ly q al ty ( d f t d ty) iii- t d ytal . s c d v y tal ty ally av d f a
t d f w d f t ( y tal d l at ) t a gan,a d t a l t al l td v . s l a d a y fav a l
t t at a t ta l f -t at , f q y, a d - w a l at . T lw d a d a , t al d t v ty ( tt t a
at t at ), l t ld ad w t t (a x at ly 10 t t at f s ),
at at d d ft v l ty ( at t a gaA ), a d -al t .
W l s c d , v al l v t a v al . D f t dty, alt tt t a iii- t d , t ll
aj s c. D f t ta a d f . ., all l (0.1–5.0m d a t ) t at t at
t t at . T a a tt l a a d t t at a d t y
d ad d v f a . T d ty f t t d f 103 /2 f t t
ally ava la l t at . s a d ty, a a f d t t , w ld lt a xt
l w y ld f d v (ic ) la t a a f a t f all t . ot l l d d t s
lay ( at t a 50m ) w t l w d l v l (lt a 1015 a /3) a d l ty a l f -t . A t a t y t T y ta c t al
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404 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
r a a d D v l t La at na a t , Ja a , a d at d t at T y ta a d d s c
l y tal t 7 a , w t d f t d t t a f 10/ 2 a 2 d f a t d v -
t v v t ally d d s c, all wt d t f la d v w t a a l y ld.
D t t al y tal , l w- w t tys c l t t ,9–11 a w ll a iii- t d d v ,
av d t at d at t 300°–600°c t -at a . i fa t, s c d v av d t at dt a t a t w ll a v 900°c. g v d -
t at d f a , s c ld a t flv t t a d -t at a l -
at l a la , a aft, a t l ,a fa t a d w la t , d ea t x l a-
t a d l d ll , a d - w at .s t -t at f a w ld al
v d a a f ty f l t y ta a t t ff t f l a t w a t at
at t at . i add t t t d vt lv , -t at a a w ll al
a aj all t t w d ad d l y t fs c gan.
Carbon NanotubesT day, mosFeT a t a tay l t d v
f ic . T d a f mosFeT v t d vty tly d t t d a l al t .A d f t mosFeT , t d v tfa t a d l w , t f l t v -
a d f d v a l f l - (m ’ Law). c t mosFeT av at l t
t d f 100 , w t a j t d f a-t z f 50 y t ta t f t xt d ad . byt ddl f t xt d ad , a y a l vt at t mosFeT w ll t t al t l -
al a a d v f da tal y al l tatt a y f t z d t . Y t, al f l t -
f t l t d t y, t av y t t d w d v ( at al ) t at
v t f t l a t at dw t t t d al f mosFeT . ca a -t (cnT ) a d d y a y a t t a w .
s i j a12 t v d cnT 1991 w lt dy t d d y t l t al d a
tw a l t d . i j a’ a t t df v al a t t ( d f lt l layf a at ) ll d t t yl d . T
t yl d a w all d lt wall d a -t . i 1993, i j a a d t f d t at y add
all a t f atalyt tal t t a l -t d t y ld d cnT t f a lat lay f a ( a t t t ) f t wall .T cnT a w all d l -wall d a t .
T day, va t q , l d la a lat a ta t a d tal- atalyz d al va
d t , av d t d cnT . s lwall d cnT a t t t f lt a l at .
s l -wall d cnT a ty ally 2 d a ta d a t v al ll t l t . g vt xt ly la l t /w dt at , cnT av
l d al 1-D y t . T y a d ly t (tt l t t a y t at t a t l), wxt ly t al d t v t ( a a l t
d a d). T t d f a at a d t -t ( a d a t ) d t w t a a ta t a a tal a d t . T x t
t ty f l -wall d cnT a a d ft at f all- a – a d a l t t
l y w t a t v d v a d tl -wall d cnT a d t l t al t t a
tall cnT . 13Va ty f d v a ad f l
wall d cnT . T t a t a a t t
cnT ld ff t t a t (cnTFeT), w a all lt l - a d FeT f t day’ v t al t l-
y. s at tat f cnTFeT a v F . 2. c v t al FeT av l tat
f t al , l d q a t a al t -l a t l t f t a l a d t t
Figure 2. Schematic representation of CNTFETs: (a) bottom gateand (b) top gate.
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Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005) 405
miniATuriZeD eLecTronics
f t at x d d a . T t l at lal a a t , w d ad t f t f tt a t a a w t . T l a a t al t -
t t ta d y w a d v all w -t . m tall zat al d FeT -
t al a a, l ad t a d ta ( lt d d a d y t f a ). i add t ,
l l a l ad t a at ty f l -
t at - d d t . s l -wall d a -t a 1-D y t , w d t all w t all-a l att f l t ( l ) y latt d f t
t at 3-D y t . i cnT , aav ly tw d t f a at —f wa d a wa d. T a att t at lt l t -al ta q a t v al, a d
t a l ty f t t a cnT xt lyall. b a f t d d att , l -wall d
cnT x t l w t v ty t a v t al 3-Dd v . i tall a t , l t t a t
all t ( att ) v a f w t f l tat t at . ev d t a t
x t all t av v at l a t a f w d da t . T , y d at l -wall da t al a d a l w d ty -
a a tly d d. na t d t fff l t at , a d tall a t a
a y t d t 100–1000 t at t atal a al —t tal d t day’ d t .s d t l -wall d a t a d t
a d a at al ( ally a 1- V a d a ) a da d tly a a d t l t, t y ff t
t t al f a l a w t l t t l ya d l -wall d cnT . b t -ty a d -ty
cnFeT a d d, t v t att day’ cmos t l y a al z d w t a -t at a all al . s l -wall d cnT a
d ally t d f cmos a l at a t y avy t val a d d t a d , a d l t
a d l av a ly t a ff t v a . o -d al s tt y a –l d v a al f d at tal/ l -wall d cnT t fa . if t
t fa at lat lay t , s tt ya cnT a la . A a la d v
d lay l t d t w a t v a a l d a d l d t w a at v a a l d. u d ta a d t , l t a d
l a lta ly j t d f t td f t cnT. s av , alt t f l
t al t a t - a d t t l y f t day,ff at f t al l t .14 s l -
wall d cnT av al d d tw twl t d a d d a l t a al llat .
sta l llat tw 3 a d 200 mhz av d t at d. n t ly a t y d a a f q y
ta da d t al , a f t xt ly l w a ,
a a . s a ld t t at t a l t w a at .15
Other Devicesot d t - a d t l , at at d t 16 a d l t a al y t
(mems), 17 ld aj wt d t a l -
at a t t l y at . ea f t wx t a t t d v d v la d l t a a a t v t . W t t
f w d v t l y, t at a d t a t f mems, a d t w d a d-w dt ( f at a dl a l ty) aff d d y t
at d t , l t at zat ad dl t y t t at t a l f
d t at al. T l x ty a d at al d ff - tw t t al a d at a
al w ld a t d f t a t at z d l t a d t a a
a t a t l . h w v , ta f da tal a
x l d.mems d v a a al a d l t a -
al a t fa at d at t al t da d t d a at d w t t ic d tA mems d v t f a al
l t ( . ., a t l v , , v t , tt , t .) t at a f t v d xt ally a l d
f t ally at d l t a t A l at f mems t l y a f l
a al a t d a a d a t at t l x y t xt v l t t l
al t at d t adja t t ta al a t .
eff t v ly t at l t t y t w t t mems a t , t t w t t a -
at a a , all , ally f -dl t t y. i t at d y t al t t w t mems , a
t , a d t al av al ady a v d al . D v a - z d
a y y t , d y t , a d a l y t w ll t at t a t las t mems lay a d t t a lat v lyt a f l t t t f
a al lay (ty ally ly l ), t d fa a al d v a t a d a t at
t at d la - t al a a t d l v laf t q . T “t ” l a
a t ally lv d y t d v l t f t l t a y,l t lat , a d ld (LigA).1 i t
LigA , tal a l a att d latw t t t - t wall t t f 200m
at , a t t v tfa t f 100 . ApL a t v t t mems a a
av d ta l d v a t l .1,16,17
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406 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
DEVICE TECHNOLOGY AND ITSIMPACT ON APL
ApL t t fa at , altw t d t a ly y a f t t a t /ic v l -t .18 W ly al f a t ady ly
f ic . g ally, w d t at atw t al v d a d a ly t ta da d
q way . T a tw x t t t -al- ff-t - lf (coTs) d . o t f
at a ay w t v d l a ta da d d f lt l t ld l a d ApL
fy w t y a t t d. Tlat t d t f t at a ay at ApL t ld
a a l at a ay (FpgA). i FpgA , t t -t tw ld l al ady x t;
fa t, all f t a a l t a f l -t ally a a l f a d a t f . i t way,d ff t t at a a v d w t t
a y d v l d ff t a al -t . o t t t d att d v l d ftwa , t FpgA la d a al a dwa
t t at a ( a d l f l l ) “ ” t t t d att t t t lf.T d x t t d f t ic t ata d d w t coTs FpgA t
a t t t a d y t q t . ApL aa l , f l t y d t .1
T e m rta e f ic t ApL a t e ver-em a zed, a d we m t ave a red a e t a w dearray f ic t meet t e vary r y tem de-ma d . A t e f t re f ic te l y ev lve , ApL m tkee a e w t t e late t a e dev e te l yt e a mart a l er. A ted a ve, t e e a e a
e q te rad al, ra fr m d tal w t ver 109 tra t r t - erf rma e m r wave a ed
s c a d gan te l y. c are t ly e mde er a d m re ex t em d t mater al ,
t ey are al e m m re ada ta le. u l ke FpgAa d t m , erta ew a a t ally at e r r t rat at w ll der ftware tr l. T e e ada ta le w ll erta ly d t e r way
t ma y f t re ApL y tem devel me t . W le mf t e a ve d v lve e a eme t f trad
t al ele tr r try a d m e t , ma y ewalle e fa e r t de er , l d ew mater
a d rad ally ew dev e a t e cnT. ApL m tt ally e a e t k wled e f adva ed dev ete l y a d e f lly ver a t t a l at te re t at r t mer eed f r ele tr w ll e met
t e f t re.
ELECTRONIC PACKAGINGW le (ic) te l y a d erf rma e eem
t e r w w t t d , t e ele tr a kaw rld der maj r a e t try a d kee a ew t t e ever- rea dema d m ed y t e ica d t e e d- e y tem a l at . pa ka de ea t e met d l y f r e t a d terfa t eic te l y w t a y tem a d, lt mately, t e y alw rld. i re e t year , t ere ave ee maj r ft
a ka a t re d t t e a w rldw de eletr d try. i t day’ ele tr w rld, t e em a
rta l ty. Al w t rta l ty everal t ey tem-level fa t r , e. ., mall ze, l w we t, l w t,
f t al ty, ea e f e, a d e t v ty (w rele ). T e e y tem-level dr ver ervade ele tr r d-
t fr m pc a d w rele tele e t m l tary eldardware, med al tr me tat , a d a e t
ele tr . small, l twe t, l w- t, ly f -t al, a d e ted ardware r d t are key t all
m der ele tr y tem a l at . s ardwarer d t a d t e r a ated y tem-level devel me tave f r ed maj r arad m ft ele tr a ka
T e e arad m ft are emat ally a t red F .
Figure 3. Electronic packaging paradigm shifts.
Fine pitch SMT area array (e.g., ball-grid array, BGA)Direct chip attachment (DCA) – packageless
Chip interconnection Wirebonding Flip-chipping Micro-sized compliant interconnect
Package (to board) interconnection Pin-in-hole Surface-mount technology (SMT)
Single-chip packages Dual-in-line package (DIP) quad flat package (QFP) QFP BGA chip-scale package and BGA
DCA wafer-level or wafer-scale packaging
Multichip packages Hybrid (chip and wire) multichip module (MCM) composite MCM wafer-scale integration Discrete passives (R, L, and C) embedded (integrated) R and C embedded (integrated) R, C, and L
Package hermeticity Hermetic (ceramic, metal, glass) nonhermetic (plastic) encapsulants or overcoats wafer-level packaging
Evolutionary shiftRevolutionary shift
µ µ
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Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005) 407
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f r f t t ta t t t l -t a a a a.
A t d a v , t t at d t a dmems w ll lay xt ly ta t l t -f a f f t “ l t ” y t . T a t
a a w ll a t a t l t w ldft f d v d ally a a d t at d -t t f lly t at d y t . T d v l t f
t at d a a l t ta t al, l t -al, a d a al d v a d y t , all at l t y y, w ll t .ev w t t day’ -d ty a a , a a
f y ( at f t a a f t ic t t a af t d ly t d w a d pWb) t llxt ly l w ( ally 8–10%). T f ll t atf all t ( . ., t , a a t , d t ,
wav d , t l t , t .) a t t t al ta t a a f y a v 80%. s a -
t, a at ally t d F . 4, q a -a t l y t adva t t t w d -v d al a v t , t l t t ,
a d rF wav t a dd d
t a 10 ghz. T t, t lla f t -j t x t l w al l at f q x
100 ghz. W l d tal t a t atat t l f q (>10 ghz) t day, t -
t t f - f a ic l al 100 l , t tat l w-l al w t t t a dw dt a a 35 ghz.21 F 5 ll t at ty al w d a d -
t t .T atta t f a ic d tly t a t a d(w t t a l - a a ) y t w d
- w ll a . s d t attaw ll v d w t t all a
a d v lv f t ta da d la - – fpWb ( d a d ) t t , d a d t t( x a d x ta ). W d
t t a t d d xt v ly, d at y a d a a t a d d f
q y, t d a ff t d.22Fl - t t a al d l t a d . W l t - t x atta
t ( ld w) lat v ly t a tf
A AA
Integrated circuit
Chip interconnect
Passive layer
Optical layer
Power andground layer
RF andmicrowavelayer
IC IC IC IC
Multilayer thin-film signal routing
Figure 4. Schematic representation of next-generation integrated substrate technologywith embedded RF, microwave, optical, and passive component layers coupled with inte-gral power and ground.
WirebondChip passivation
ICBoard
metallization
Die attachmaterial
IC
Solder bumpUnderfill
IC chip
Substrate or boardSubstrate or board
Solderbump
CrCuAu
Barrier layermetallurgy
SiO 2 /Si 3N4
n +
SiO 2Chip
bondingpad
Glass/ solder dam Substrate
Topsidemetallurgy
IC chip
SiO 2 /Si 3N4
n +SiO 2
Chippassivation
Chipbonding padWire bond
Chipbonding padWirebond
Figure 5. Schematic representation of wirebond (left) and ip-chip (right) geometry.
t a d a d t d t ta add t al a d fa a a. W tt t t at a d t
xt v w d ty ad -l y t f t - l d -
t , t fa f t a d a v d w t - d d ic
( a l - a d at ).
InterconnectionsT a aj ft t-
l v l t t ( t a -a a d) f w d t
- . Alt t w,19 - t l y t t
a aj ad t t l -t a a w ld, w wa
l ly d at d y w da f w y a a . st ll, d t tt d t wa d - t -
t , t a 1012 w da ad a ally.20 Fl - -
tly t a w d-, v v l , a
f t a d ic q d t t t ld all
t d ad a d t d fal w q t. D t
t a d t, t w t t- t t -
a y t a f a .W d av f q y l tat (l ), w l t t
ff t v t f q l
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408 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
w t t t d atta t, a -at d w t w d a . o aj a t t al l a l ty a f t f t
f t al x a (cTe) at tw td d t (l w cTe) a d t -
f d x l t a d ( cTe). La cTeat tw a d t a d a d
la t a t ld j t , l ad t fat fa l-
. T l xa at d w t t y la a d t d a t f t ld all t t z d t a v d ty (la t/ t t
). A l l t t t l a l ty - t f d ll, w a xy j t d
tw t a d t t a d t ll t aa d “ l ” t fa f t t t fa f t
a d w l f lly a lat t ld j t . T f d ll - - ta da d - f d
pWb a l ( d a d ) a w t -a tly v l a l ty. u d ll f -
x ly t a l d v l d -t w t x d lt l a l ty v t.
s t f t d t at al a ic ly d d f a dl t waf a d d
, t f t d d x ld f lv l a l ty w t t d ll .23 D at a 25m av atta d t 25- t 50-m -t
x a d , a v all x l a l l t a100 m t ( F . 6). s al a dl t d ft t av t d t av d da a da ly.23
D v y t a d l x ty, alt at vt v t al - t l y a d.Tw xa l a w F . 7. b t l -
d d all d , d d y a t at w da al w , t at a la d t ’
d ad l d w t a d t a ad-v . i t t t q , t l - d d all d “ t d ” a la d a d t d ta d
Figure 6. Ultra-thin silicon on exible circuit board assembly. Thechips are 50 m m thick and each contains 1368 solder bumps. Theex board is also 50 m m thick.
Gold bump(single-ended
wirebond)
Region between chip and board (substrate) can be underfilled
Double-layer anisotropic conducting film,upper-layer insulating adhesive, lower layerfilled with conductive compliant microspheres
(c)
(b)
(a)
Board or substrate
Conducting spheresin underfill capturedbetween stud bumpand board bonding pad
Self-underfill
(d)
Solder mask
Solder mask
Board or substrate
Solder maskBoard or substrate
IC
Chip bonding pads
Passivation
Dielectric coat
Deformable resinConductive coat
(Ni or Au)
or
or
Ag
Deformable resinNi or AuDielectric coat
IC
Chip bonding pads
Passivation
IC
Chip bonding pad
Passivation
Gold bump(single-ended
wirebond)
Substratemetallization
Conductive epoxy(screen-printed or
dispensed or pre-appliedto the gold bump)
Figure 7. Adhesive-based ip-chip technology. The stud bumps(single-ended wirebonds) are placed on the chip using anautomatic wirebonder: (a) standard conductive epoxy attach,(b) double-layer anisotropic adhesive pre-applied to board,(c) conductive ller particle detail, and (d) chip attached to boardwith double-layer anisotropic conducting lm, which also providesa self-underll.
t a v f t a v t fa . Tt d- d t d a lat ta
a t lay f d t v ad v . A t l ft d f t lat , a all a t f t d t vad v ad t a . T t la
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d t at ad a d ld la w lt ad v , lt t t y w F . 7a. i a va a t f t t q , t xy a
-a l d t t t at y t .T d xa l a a t ad v ,
. ., a ad v t at a all l t ally d t va t l dd d a d t a at x.
A d (F . 7 ) t d d w t t
ad v , a t a f w d t a t l twt a d t at d ad t a a t at . Ty al a t l d ta l a w F . 7 .
W t ad v d, a l t al t t ad . Al , t a t ad v ll t t
a tw t a d t t at (F . 7d), ta t a a d ll t d.24 s a t -
q ld a t f f t l w- t - l tat , v d d , a a l-
ty, a d l a l ty a lv d. n t adva d t t
av d v t y a , a f la
Passivation layer
(a)Bonding pad
Substrate with integral compliantbonding fingers
Substrate with integral compliantspiral or “G”-shaped leads
Prebumped fingersolder reflow
Prebumped spiral
or “G”-shapedlead-solder reflow
Compliant“S”-shapedwire
Substrate with “S”-shaped wirelead solder attached at both ends
Substrate with long, straight wirecolumns (posts) solder attached atboth ends (also long solder pillar
replacing wire)
IC
Passivation layer
(b)Bonding pad
IC
Passivation layer
(c)Bonding pad
IC
Passivation layer
(d) Bonding padIC
Figure 8. Schematic views of compliant chip interconnection methods.
a t a y t a al -
l . La a t a yd a la t d t tal t ay d a tal- aa a al d a d tly
t a d t at . W la v l a i/o ( v 600 i/o t t ), t
l x ty f t , l d- t d t ta t d f
t d t , ad t tt v . m a al -l
t t av a a d ft t t . s v al y a a ,
a d f tal d t v l w d
a a la t f w d-. T mems-l t t
v d l ttl att t a tt d f - f a t -
t wa t wa d t -ld j t.T day, l a d v lx l l ad t at atta t - all- d a ay (bgA) ld ad
a d d t a t t dad. T w a y at al a d a , a
f ld w d d “s”- a dl ad t x l t ata t t a t fa at d a al. s l a t l ad ta
cTe at tw ta d (l w cTe) a d t
a t at ( cTe). Ll ad f ld w
( ld atta d at t d ) a al d. s attat f l ad y t a w F
Single-Chip Packagingi d v d al r le- a ka te l y ra
dly ev lv tw maj r d re t : (1) r d array a ka e , a bgA , are ra dly re la rre t -de ty rfa e-m t a ka e , a t e q ad- at
a ka e (QFp; a re ta lar r q are a ka e tyle w ter meter lead all f r de ), a d (2) are em ted d re tly t derly r t ard w t t a
a ka e tr t re. T d re t m t de r ed t e l terat re a e t er d re t- atta (DcA) r -
- ard. c m ared t t e QFp a d t e ld t r -le–m ted d al- -l e a ka e (Dip) t at t ll ex t m t ele tr r d t t day (a t f r well
ver alf f t e le- a ka e ), t e bgA ffera t adva ta e , l d ta t i/o de t
(re ardle f t e t tal m er f i/o ). be a e t ei/o are a ed a r d, t e i/o de ty a rema
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410 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
ta t a t e a ka e ze r i/o m er rea e ,fa l tat ard de a d m m z d ffere e
at le t . T e m rta e f t e bgA ev de edy t ra d r wt t e d la e e d t e Dip a
t e d m a t le- a ka tyle. it al ra -dly aw -de ty ver , a t e m r -
bgA, a well a a w le fam ly f -de ty, m -mal v l me a ka e alled - ale a ka e (csp ).
csp are de ed a a ka e tr t re w t f t r tarea t m lar er t a t e t elf. Ty al cspde t req re t at t e t tal area f t e csp m t ele t a 1.5 t me t e area f t e e l ed . h t r -
ally, a ka ed art are referred t DcA e a e a k-a ed art a e f lly rete ted a d t e atta ed w t
m le lder re w erat w t t av t a dlefra le ic . ot er adva ta e a d d adva ta e f cspver DcA ave ee ve rev ly.25
Multichip PackagesT lt d l (mcm) t t f
f t lt a a a t v t v lv a la d l ly t t a lt d t layt at , a t a t d t d v d ally a a d l
ld d t a pWb. mcm x t t a yf a d t ty f t at d f t t -
t tw t :
1. mcm-c: - t d d t t -t d a d l t lay t - tat
a t26 2. mcm-D: d t d a d t l t a ally at-
t d tal a d lat t - l lay a l - ly l d a a
3. mcm-L: d t la at d t ad l t lay la t pWb t w t t aa d a d ff t t d f d t t lay
t (v a )
c (ic ) a t d a d t t d t t-d ty t at y t w d aft
t a f t a atta d t t t at(d atta ) y - . T mcm a t
t d t v t al t a d ( . ., pWb ) a a a ay ld . s t t
a t, t y av al la d la v fv t al a a a QFp .
i mcm , t a t v d v (ic ) v t a50% f t t at a a, t a t t t t ad t al
a a d ty f 8–10% t d a v . Tt at f a v t (r, c, a d L) t
t t at t t ta t xt d mcmt l y t a ad a f a l at . i t at d
dd d a v a w ll v mcm-c t-l y a d av a v d l t d d t mcm-
D d l . o a - a d d t v a d a a t v(d l t ) lay at l w t mcm-L a d
d v l t. o a - a d t v lay f pWa l at al ady x t.
ea h of th th ajo mcm t h olog ha -ta adva tag a d d adva tag a d b d vou ly.26 Wh h t h ology th o t o ta t foth futu ? ma y a kag g x t f l that, a mcmt h ology volv , o ly two t h olog w ll u v v :mcm-D a d mcm-L. mcm-D w ll u v v b au
t ha th qu d fo a a d t o td ty d d fo th xt-g at o ic ; how v ,t d adva tag th o l x ty of th o a d,
h , h gh o t. mcm-L w ll u v v b au of tlow o t, d t t t la k of d ty. mcm-c
a ddl -g ou d t h ology w th u t d tg at tha tho of mcm-L but l tha tho ofmcm-D. s la ly, a t h ology ty ally o t
o tha th o ga -ba d la at t h ologyu d mcm-L, but u h l tha mcm-D w th
t o l x o g a d att g t . mcm-ct h ology u d w d ly odul fo ll hoa d oth rF a d owav a l at o . it ty ally
off du d z w th lat v ly good th al o du -t v ty fo h gh- ow a l at o . it ajo d adva -tag ov mcm-L a d mcm-D t u of o gad l t lay w th h gh lat v d l t o t(8–10). ev o gla - ll d o ga d l t layu d a o- d t h ology26 t ll hav lat vd l t o ta t th a g of 5–6, a d th y hav
du d th al o du t v ty. Low d l t o ta tlay a a y fo a h v g h gh- d y( t h ) fo a .
Tw t lt a a a w tt . T t t 3-D ta f a w F . 9. T 3-D ta f d d t d
t a d a a f t t f t -d ty tat at t x f v t al t. b a
f t ta d at f t lt l d v a d td f lty f t a d v t a at ad t a d l v l, 3-D ta t d t t law t a all l, lat v ly l w i/o a t t a y.
c tly, a a y a x t t d av v tally ta d z tally lay d. F t j t
t d d ay all w t f d tta t v . if a a ta d d a
a fa l , t t a a ally d a d d. All t a al y t ta d , t t a
ld ta d att d l a t t. T t av t - a d d
a l , all w t i/o f t a d t t d t t xt. T ta d a ly w ld
t la d a ally a lat d t d l t al ta t. if la d, t 3-D a d tald a d.
T d mcm t l y f t t al f tt t a t d w t a dd d
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a a t at w t t t at ’ fa (F .10). T a a d t t ll d t at t
a d a a a a a t l t. m lt -lay t - l t t mcm-D t l ya t d t d t la a / a fa .T lt a l t d l f xt d tya d t t ally v y f a , t l t -
ally a d t ally. T “ - t” t l y aa aj d aw a t at t a t a d. o
a lat d a d v lay d w t t t, t a t v d; t t l x d l
a t waway. r a a d lva l -t at av v t at d. if d lva l t at
T l t t t f a a d all z t t d t f csp a t d a v . c -
tly, waf - al a a (Wsp ) waf -l v l a -a (WLp ) a a all t t f t csp
a t. i Wsp , t a a t t lt t icat t waf l v l. T l d t t v ta
t t a d t d t t f i/o . Wsp WLpff a t f v all z a d
l w t. ot Wsp t l d a d d,d d a a a d t t y l t , v d
f d a t l, a d t d t t a t fw d t . Wsp lt at ly w ll l at t d
f v t al a a at , v d d y ld . i Wsp , t “ a a d” a t w ld t t d a d d (t ally d) t waf
f d , t a t t t day’ a a t , w ly a l f t ic aft t
av a d waf -l v l t t a d av a atT al , f a y, w ld f dt l t ally d a a d a t . A at
tat f t Wsp w F . 11.c tly, Wsp a d t f l w i/o t
d t (
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412 Johns hopkins ApL TechnicAL DigesT, VoLume 26, number 4 (2005)
h. k. chArLes jr .
a a t dat a t d v l t f v y x-l t l ad at d d al . s f at f t
a a l t av d l w 0.1m , td t y t all t adva d at z d-waf a a t l y “ a -Wsp” ( a -
WLp).
PACKAGING TECHNOLOGY ANDITS IMPACT ON APL
el t a a a y a l f t l -tat f all ApL-d v l d l t y t .
W t t a a ly t ld f a -ally a a d a t a pWb t adva d
a l at f a t d t d a x l -t at l t a 25m t , t xt ly ta t
t t l a l ty a d f a f t y t . pa -a t t t v d a t t twa t d l t al al t a d f t , v d
at at t d at x v t al y,v d t t a d t t f a l l t ,
a d t t t f t v t a d -ta a ( a la t ), t v t f t
.ApL a ad a l t y f f l l t
a a .1,25,26 i fa t t La at y a a - adva d l t a a a fl t t t t a a f t
y t f a , a , a d d al . At ApL’f d , t VT f z wa a a v l f adva d a -a .26 T at t y a a d f t a w dva ty f y t t at a ta t t t y a dt at al d f .
T f t ld a y all f ApL tl t a a a a. T av aja ad ft t a a w ld a t d
a v . ApL t t t a t a t a l t a dl f t d v a d t . A ad alt t ady a f a d t a a ly t
t t f t d a f v - d va d t t z . s f f ld a ly w ll
t t ta t f t f a l f t , tw t d a d at al w ll d t dly d.
T a t at al t a all l ad l -t a d ApL, v t t at a all t f t l t d t y, w ll av t f ll w t.T a t l ad-f ld w ll q w q -
t a d . T w d ad f - a dWsp w ll f a a a d a w lla t a dl , a ly, a d t t f a a d
a d a d y t . e dd d t w ll qt d v l t f t - t l
al a v d t x l ty d d tt ApL y t q t . h - w a d -
t at d v at w ll t a at l y v f t , q t t t
a d at at a a l f taf a at t at x d 300°c.
SUMMARYApL a a l a d vat v t y at -
z d l t . T t y a l d , a d w ll t t ly , a t adva d d v l d w
x l , t a a . T a l at f adva dd v f ada ta l ic t cnT q a w -
fa l a ty w t at al , t l y, a d d vd a d f a . i a la v , ApL td v l t a y a a t l y t all wt t at f t adva d d v t y tl v l a l at f t . T tl a , d ta d , d v l t, a d x l ta-t f adva d l t d v a d a a w
v d ApL w t t a y d t t tyy t .
AcknoWLeDgmenTs: ApL’ at z d l -
t t l y w d ly a d, w t y ld t d a t t . T t t t , i a d t d t t a y t t , -
, a d ll d t a t t t Lat y w a d v l a d l t l t
y t . T ff t , t a t a d t, av adApL a ta t lay t a l at f at -
z d l t t t ty y t . i t f t tff t w ll v t al a d v a d a
a t l t t at f a d, vd v l t .
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THE AUTHOR
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ha y k. c a l J .
t h ad f t T al s v D a t t a d a f t p al p f al staff.D . c a l a w d f t a 30 y a t l t a a, a t d t a200 a t l , ld 10 at t , a d a t at ally z d al t l t d v ,
y t , a a , a d l a l ty. h lat t t t l d lt d l d , fa a-t , a d t t ; adva d t t; d al t tat ; a d v l a d mems t l y. h a F ll w a d f p d t f imAps (T m l t a dpa a s ty), a F ll w f t ieee, a d a a t f t b a d f g v f ieee’c t , pa a a d ma fa t T l y (cpmT) s ty. h - a l add
a y. a l @j a l. d .