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1/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Miniaturization and advanced optical
lithography
Francesc Pérez-Murano
Institut de Microelectrònica de Barcelona (CNM-IMB, CSIC)
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Integrated circuits (Microelectronics Industry)
Massive nanofabricationMassive nanofabrication
PanasonicIntel
High production capabilities
Extremely complex and expensive
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Transistor MOS = Miniaturized transistor
Attalla and Kang, 1.960
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
State of the art TMOS transitorIEDM 2009
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
State of the art TMOS transitorIEDM 2009
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
1947W. Shockley, J. Bardeen W. Brattain
FIRST TRANSISTOR
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
1958: First integrated circuit
Jack S. Kilby
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011 10/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Cross Section of Panasonic 65nm CMOSCross Section of Panasonic 65nm CMOS
5th Cu4th Cu3rd Cu2nd Cu1st Cu
Cu
Low-k
STI
6th Cu
7th Cu
Min. hp90nmM2, hp100nm
Cross Section of TransistorCross Section of Transistor
55nmNiSi
O2-
Si4+
0.227nm0.162nm
Θ= 120~180°Si
substrate
1.8nmSiO2
poly-Si
Gate dielectrics film
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011 12/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
CMOS Technology Processes
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
The number of transistors per chip The number of transistors per chip doubles every two yearsdoubles every two years
MOORE’s LAW
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011 16/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Limits of optical lithography
Minimum transfer feature= k1·(wavelength)/(numerical aperture)
k1 depends on technology and instrumental parametersNA: Numerical aperture = n·sin
K1=0.8, = 436 nm, NA=0.4
K1=0.4, = 193 nm, NA=0.7
Resolution= 872 nm
Resolution= 110 nm
1988
2004
K1=0.22, = 193 nm, NA=1.35 Resolution= 32 nm2010
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011 20/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
IC LSI VLSI ULSI Nano-LSI10m
1m
100nm
10nm
ContactAligner
1:1 ProjectionAligner
Stepper Scanner NGL
Device Trends and Exposure Tool
g-line (436nm)i-line (365nm)KrF (248nm)ArF (193nm)ArF Immersion
Device Trend(134nm)
Immersion lithography is introduced from 45nm-node
Half-pitch = k1λNA
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
dry immersion
resist
lens
light light
reflectionAll
reflection
NA limitation(NA<1.0)
fluid (water)
Higher NA(NA 1.0)
waferAir
Incident angle
Using an immersion fluid between the wafer and the lens substantially changes the light path, resulting in two benefits. First, it enhances depth of focus (DOF) for a given Numerical Aperture. Second, immersion allows lens designs with Numerical Apertures significantly larger than 1.0, therefore allowing improved resolution. NA<1: Gain in DoF due to the smaller angles in water.NA>1: Only feasible for immersion. Dry lenses would show total reflection at last surface. With immersion lenses smaller CDs can be resolved. Resolution enhancement !
Principles of Immersion Lithography22/68
Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
http://www.itrs.net
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Double patterning techniques
Pitch doubling Double exposure
11 nm channgel length achievable with immersion lithography
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
11 nm channgel length achievable with immersion lithography
Double patterning techniques
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
32nm half-pitch poly-Si gates etched using double
pattering
© IMEC
Self-aligned double patterning 22 nm half pitch
© Applied Materials
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
© NIKON
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Institut de Microelectrònica de Barcelona
Escuela de verano de Jaca July 2011
Design (Logic) Design (SRAM)(Red Photo GATEline, Green photo GATEcut, yellow is ACTIVE)
Double patterning @ 45 nm