CODE FOR MINI PROJECT CODE FOR CONTROLER MODULE :`timescale 1ns / 1psmodule ddr_ctrl(clk,reset_n,sys_r_wn,sys_add,sys_adsn,sys_dly_200us,sys_init_done,istate, cstate, wren,addr);`include "ddr_par.v"inputclk;reset_n;sys_r_wn;sys_adsn;sys_dly_200us;input [RA_MSB:CA_LSB] sys_add;outputsys_init_done;output [3:0] istate;output [3:0] cstate;output wren;output [RA_MSB:CA_LSB] addr;regsys_init_done; // indicates sdr initialization is donereg [3:0] istate; // INIT_FSM state variablesreg [3:0] cstate; // CMD_FSM state variables

reg [3:0] cs_clkcnt;reg [3:0] i_clkcnt;regi_syncResetClkCNT; // reset i_clkcnt to 0regcs_syncResetClkCNT; // reset cs_clkcnt to 0regload_mrs_done; // Load mode register done during intilaizationregload_mrs_af;regrd_wr_req_during_ref_req;reg [RA_MSB:CA_LSB] addr;reg wren;reg [10:0] q;regref_req_c;regref_req;reglatch_ref_req;regref_ack;regsys_adsn_r;reg [RA_MSB:CA_LSB] sys_add_r ;regsys_r_wn_r;// local definitions`defineendOf_tRP_ii_clkcnt == NUM_CLK_tRP`defineendOf_tRFC_ii_clkcnt == NUM_CLK_tRFC`defineendOf_tMRD_ii_clkcnt == NUM_CLK_tMRD

`defineendOf_tRPcs_clkcnt == NUM_CLK_tRP`defineendOf_tRFCcs_clkcnt == NUM_CLK_tRFC`defineendOf_tMRDcs_clkcnt == NUM_CLK_tMRD`defineendOf_tRCDcs_clkcnt == NUM_CLK_tRCD`defineendOf_Cas_Latencycs_clkcnt == NUM_CLK_CL`defineendOf_Read_Burstcs_clkcnt == NUM_CLK_READ - 1`defineendOf_Write_Burstcs_clkcnt == NUM_CLK_WRITE - 1`defineendOf_tDALcs_clkcnt == NUM_CLK_WAIT// INIT_FSM state machinealways @(posedgeclk or negedgereset_n) beginif (reset_n == 1'b0) beginistate