MIMO Development Efforts at Virginia Tech · Slide 2 Ellingson, Mostafa, & Reed – Sept 19, 2004 MIMO at Virginia Tech Virginia Tech is interested in all aspects of MIMO: MIMO channel

Slide Slide 11Ellingson, Ellingson, MostafaMostafa, & Reed , & Reed –– Sept 19, 2004Sept 19, 2004

MIMO Development EffortsMIMO Development Effortsat Virginia Techat Virginia Tech

S. Ellingson S. Ellingson 11, R. , R. MostafaMostafa 22 & J. Reed & J. Reed 22

ellingson,ramostaf,[email protected],ramostaf,[email protected]

1 1 Virginia Tech Antenna Group (VTAG)Virginia Tech Antenna Group (VTAG)22 Mobile & Portable Radio Research Group (MPRG)Mobile & Portable Radio Research Group (MPRG)

Bradley Dept. of Electrical & Computer EngineeringBradley Dept. of Electrical & Computer EngineeringVirginia Polytechnic Institute & State UniversityVirginia Polytechnic Institute & State University340 340 WhittemoreWhittemore Hall, Blacksburg VA 24061Hall, Blacksburg VA 24061

September 19, 2004September 19, 2004


MIMO at Virginia TechMIMO at Virginia Tech

Virginia Tech is interested in all aspects of MIMO:Virginia Tech is interested in all aspects of MIMO:MIMO channel physicsMIMO channel physicsMIMO communication theory MIMO communication theory Practical implementation Practical implementation (HW, SW, Systems, & Networks)(HW, SW, Systems, & Networks)

Outline of this talk:Outline of this talk:Evolution of a serialEvolution of a serial--bus based data aggregation bus based data aggregation scheme for array receivers scheme for array receivers

SHF Array Experimental (SAX)SHF Array Experimental (SAX)Argus Argus Matrix Channel Measurement System (MCMS)Matrix Channel Measurement System (MCMS)

Experimental MIMO SystemsExperimental MIMO SystemsVTVT--STARSTARSDRSDR--30003000


Preliminaries: A MIMO Comm. SystemPreliminaries: A MIMO Comm. System

((nnTT , , nnRR) = ( # of Tx. Ant., # of Rx. Ant.)) = ( # of Tx. Ant., # of Rx. Ant.)

Rx dataSignal Processing Techniques

Rx

Rx

Rx

•••••

1

2

nR

Info data

Tx

Tx

Tx

Vector Encoder

•••••

ct1

ct2

ctnT

Fading Coefficients

ij

:

α

1

1,2,...,Tn

j i jt ij t t R

ir c ISI MAI j nα η

=

= ⋅ + + + =∑


Array Receiver ArchitecturesArray Receiver Architectures

A MIMO A MIMO communications linkcommunications link or or channel channel measurement systemmeasurement system consists of consists of

An array transmitter An array transmitter An array receiverAn array receiver

Array transmitters are “easy”Array transmitters are “easy”

Array receivers are Array receivers are hardhardData Aggregation (interconnects)Data Aggregation (interconnects)Processing Throughput (logic density)Processing Throughput (logic density)


SHF Array Experimental (SAX)SHF Array Experimental (SAX)

10 MSPS (real)16K FIFO/ch

(PC-hosted)

Downconversionto 7.5 MHz;

BW = 2.5 MHz

(3 48”x19” racks)

2.38-2.49 GHzFront End

Classical“Polled

Bus”Data

Aggregation

MIMOChannel

MeasurementProject

(1999-2000)


SAX: Array ReceiverSAX: Array Receiver

SHF Rack(24xx ↓ 435 MHz)

UHF Rack(435 ↓ 7.5 MHz)

A/D Conditioning,Power, and Cal

Rear View of Rack

16-Channel Digital Receiver (PC with A/D cards)


SAX: OnSAX: On--thethe--Fly Data DisplayFly Data Display


SAX: Field SAX: Field EvalEval of MIMO Capacityof MIMO CapacityIdeal NT=8Ideal NT=2

Measured NT=8Measured NT=2Measured NT=1

(Behind Building)(LOS)


SAX: Lessons LearnedSAX: Lessons Learned

Limitations of Polled Bus ArchitectureLimitations of Polled Bus ArchitectureData AggregationData AggregationProcessing ThroughputProcessing Throughput

MIMO Field StudiesMIMO Field StudiesEasy to be overrun by complexityEasy to be overrun by complexityBrute force approaches are too slow Brute force approaches are too slow --> Time IS money> Time IS moneyNear real time monitoring is GOOD (less wasted effort when thingNear real time monitoring is GOOD (less wasted effort when things go wrong!)s go wrong!)

More info:More info:S.W. Ellingson, "Effects of Angle Spread in a Complex Outdoor EnS.W. Ellingson, "Effects of Angle Spread in a Complex Outdoor Environment At vironment At 2.4 GHz", 2.4 GHz", 2003 IEEE Antennas & Propagation Soc. Int'l Symposium2003 IEEE Antennas & Propagation Soc. Int'l Symposium, Columbus, , Columbus, OH, June 2003 (OH, June 2003 (33:264:264--7). 7). S.W. Ellingson, "Vector Channel Coherence in a Complex Outdoor ES.W. Ellingson, "Vector Channel Coherence in a Complex Outdoor Environment nvironment At 2.4 GHz", At 2.4 GHz", 2003 IEEE Antennas & Propagation Soc. Int'l Symposium2003 IEEE Antennas & Propagation Soc. Int'l Symposium, , Columbus, OH, June 2003 (Columbus, OH, June 2003 (44:208:208--11). 11).

People involved:People involved: S. Ellingson, J. S. Ellingson, J. HetrickHetrick (TRW), K. (TRW), K. AyotteAyotte (OSU), G. (OSU), G. WhippsWhipps (OSU)(OSU)


?

WantBetter,

But HowTo GetBetter?

Some MIMO Channel Measurement Some MIMO Channel Measurement Systems Compared (Version 1)Systems Compared (Version 1)


And Now for Something Completely Different:And Now for Something Completely Different: Argus Argus •• Astrophysical transient search Astrophysical transient search

instrumentinstrument

•• N = 36 element array, 24 N = 36 element array, 24 instrumentedinstrumented

•• 12001200--1700 MHz tuning 1700 MHz tuning

•• TTsyssys ~ 215 K per element~ 215 K per element

•• Digitizes 20 MSPS complex (14 MHz Digitizes 20 MSPS complex (14 MHz BW); processed to 78.125 BW); processed to 78.125 kSPSkSPScomplex & aggregated into a single complex & aggregated into a single 8080--Mb/s serial data streamMb/s serial data stream

•• Data stream broadcast using UDP/IP Data stream broadcast using UDP/IP over Ethernet to PC cluster for all over Ethernet to PC cluster for all subsequent processing subsequent processing

•• Pulse sensitivity ~ 24 Pulse sensitivity ~ 24 kJykJy at zenith in at zenith in 0.2 s0.2 s


What Argus “Sees”What Argus “Sees”

• Eigenvalues of observed spatial covariance matrix (209 ms integration)

• Astrophysical pulse would look like this, but in frequencies not normally occupied


Argus Narrowband ProcessorArgus Narrowband Processor

•• Licks the “corner Licks the “corner turning” problem using turning” problem using serial bus architecture serial bus architecture implemented using implemented using LVDSLVDS

•• Control goes out, Control goes out, timetime--ordered data and ordered data and status comes backstatus comes back

•• Same architecture Same architecture simplifies additional simplifies additional processing & processing & interfaces to other interfaces to other systemssystems


Argus: Lessons LearnedArgus: Lessons Learned

LVDS LVDS serial bus technology is an effective replacement bus technology is an effective replacement for polled bus architectures, for polled bus architectures, especially especially for largefor large--N, lowN, low--BW systemsBW systems

More info:More info:S.W. Ellingson and G.A. Hampson, "Argus: An L-Band Array for Detection of Astronomical Transients," 2003 IEEE Int'l Ant. and Prop. Sym., Columbus, OH, June 2003 (3:256-9).S.W. Ellingson and G.A. Hampson, "Detection and Localization of L-Band Satellites Using an Antenna Array", 2004 IEEE Antennas & Propagation Soc. Int'l Symposium, Monterey, CA, June 2004.Project web site: http://www.ece.vt.edu/~swe/argus

Key involved: S. Ellingson, G. Hampson (CSIRO), many others…


Matrix Channel Measurement System Matrix Channel Measurement System (MCMS)(MCMS)

TAS

MCT - 4Channels

RAS

MCR - 16Channels

4 16

Vector / MatrixChannel

Under Test

Cal

Control/StatusSignal Flow

Key

250 MHz - 6 GHz40 MHz BW

Arbitrary, coherent waveforms

Continuous capture & On-the-fly analysis

•• Portable (2Portable (2--man lift)man lift)•• Battery Powered; 1Battery Powered; 1--hr minimumhr minimum

Application & frequencyspecific

Application & frequencyspecific


ControllerWindows 2000

DigitalTransmitBoard

RF Up ConverterCompact PCI

MCMS Receiver

PXI 6533

EthernetHub

Digital to AnalogBoard

DUT Bulkhead

DigitalReceiverBoard #1

RF Down Converter

Analog to DigitalBoard

DigitalReceiverBoard

#2 - #15

RF Down Converter x 14

Analog to DigitalBoard x 14

DigitalReceiverBoard#16

RF Down Converter

Analog to DigitalBoard

SCSI 68

Card Cage

ClockSource

Ethernet

LO Tray

10 MHz

TCC-1

40 MHz LO 2

LO 3

LO 3 x 16

LO 4 Monitor

LO 3 Monitor

LO 2 Monitor

LO 1

LO 2

LO 3

LO 2

LO 3

LO 4

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

CornorTurner

DSP

PXI 6533Receive Channel #1

Receive Channel #2 to 15

Receive Channel #16

Transmit Channel

Ethernet

Ethernet

DownConverterControl

Ethernet Recv Control #1

Recv Control #2 to 15

Recv Control #16

11 Bits

11 Bits

11 Bits

Recv Control #1

Recv Control #16

Recv Control #2 to 15

LO 1

LO 1 Monitor

LO 4 x 16

LO 2 x 16

LO 1 x 16

Display

Mouse

Keyboard

AUXPanel

Ethernet

Ethernet

200 MHz In

200 MHz Out

TAS I/OLan I/O

LO 1

LO 2

LO 3

LO 4

LO 1

LO 2

LO 3

LO 4

LO 1

MCMS: MCMS: MultichannelMultichannel ReceiverReceiver


MCMS: MCMS: MultichannelMultichannel ReceiverReceiver


MCMS: MCMS: DownconverterDownconverter / Digitizer/ Digitizer

12 bit A/D 104MHz clock

Dual RJ45 ConnectorFor 1.248 Gb/sLVDS output

IF input(78 MHz center)


MCMS: Digital IF + AggregationMCMS: Digital IF + Aggregation

Digital IF (DIF)(one per antenna)

4 DIFs per serial bus loopx 4 loops= 16 antenna capability


MCMS: Digital IF BoardMCMS: Digital IF Board

DB37 BackplaneConnector•3.3V, 1.5V, GND•Daisy Chain•Clock, Reset•DDC Sync signals

Analog Devices AD6620 Digital Downconverter (DDC)For narrowband signal processing

LVDS Transceiverfor daisy chain serial bus

LVDS Receivers for odd and even A/D data

Wideband signal processingon Altera Stratix FPGA

Memory board locatedOn rear of PCB

1.248 Gb/sdatafrom A/D


MCMS: DIF Board CapabilitiesMCMS: DIF Board Capabilities

FFSS/4 Conversion Stage /4 Conversion Stage 104 MSPS real @ 78 MHz 104 MSPS real @ 78 MHz →→ 52 MSPS complex @ 52 MSPS complex @ basebandbasebandProgrammable 63 tap FIR with 12Programmable 63 tap FIR with 12--bit coefficientsbit coefficients

Decimation by 2 Decimation by 2 Outputs 26 MSPS complex @ Outputs 26 MSPS complex @ basebandbaseband (16 bits)(16 bits)Can be bypassed (unless AD6620 DDC is to be used)Can be bypassed (unless AD6620 DDC is to be used)Programmable 46 tap FIR with 12Programmable 46 tap FIR with 12--bit coefficients bit coefficients

Digital Digital DowncoverterDowncoverter (DDC)(DDC)AD6620 input/output/control through FPGAAD6620 input/output/control through FPGAVery large decimations & fine tunings possibleVery large decimations & fine tunings possibleUser programmable through software interfacesUser programmable through software interfaces


BGA form-factor FPGA PCB is 6 layer FR4

MCMS: DIF Board LayoutMCMS: DIF Board Layout


MCMS: Serial Bus ValidationMCMS: Serial Bus Validation

Demonstrationback plane is a simple2-layer FR-4 PCB.

PC Interface(to Nat. Instr.PCI-DIO-32HS)- Controls corner turner FPGA

Corner-Turner FPGAcontains daisy-chain receive and transmitstate machines to control data flow.

104 MHz System clock

Digital IF Processorcontains daisy-chain Receive and Transmitstate machines to control data flow.

LVDS datafrom each ADC


MCMS: Data Acquisition and DSPMCMS: Data Acquisition and DSP

Dedicated Windows PCs in Dedicated Windows PCs in cPCIcPCI chassischassisBittwareBittware “Hammerhead” quad ADSP“Hammerhead” quad ADSP--21160 DSP board for on21160 DSP board for on--thethe--fly processingfly processingConnected to corner turner through 4 100Connected to corner turner through 4 100--MB/s “link port” MB/s “link port” cablescables


MCMS Validation: Raw A/D OutputMCMS Validation: Raw A/D Output

LabWindowsCVI Interface

Time Domain104 MSPS real(AD9432 is 12-bitso full scaleis +/-2048)

27 MHz IF input

Frequency Domain

Observed SNR is >65dB (Specification is 67dB)

Blue: 1Yellow: 100, averageYellow: 100, average


MCMS Validation: After MCMS Validation: After ↓↓FFSS/4, /4, ↓↓22

-FS/4 Spectral Shift(104 / 4 = 26 MHz)

+27 MHz shifts to +1MHz

Filter Specs:•63-tap FIR,•12-bit coeff.,•12-bit in,•16-bit out,•20 MHz LP

Frequency Domain

Time Domain52 MSPS complexOutput of Fs/4 Downconversionis 16-bits (+/-32K)



MCMS Validation: Second MCMS Validation: Second ↓↓22

Output BW is now 40/2=20MHz

Filter Specs:•31-tap FIR,•12-bit coeff.•12-bit in•16-bit out•10 MHz LP

Frequency Domain

Time Domain26 MSPS complex



MCMS Validation: DDC OutputMCMS Validation: DDC Output

DDC Filter:• Dec by 200•128-tap FIR•16-bit in•16-bit out•50 kHz LPF

Frequency Domain

Time Domain130 kSPS



PXI 6533

PXI 6533

ControllerWindows 2000


RF UP Converter

Compact PCI

MCMS Transmit

PXI 6533

PXI 6533

Eth

erne

t

EthernetHub


DUT Bulkhead

SCSI 68


RF UP Converter



RF UP Converter



RF UP Converter


SCSI 68

SCSI 68

SCSI 68

Card Cage

ClockSource

Ethernet

LO Tray

10 MHz

TCC-1

40 MHz

200 MHz

LO 1LO 1LO 1LO 1

LO 2LO 2LO 2LO 2

LO 3LO 3LO 3LO 3

LO 3 Monitor

LO 2 Monitor

LO 1 Monitor

LO 1

LO 2

LO 3

LO 1

LO 2

LO 3

LO 1

LO 2

LO 3

LO 1

LO 2

LO 3

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

250-2000 MHz

1600-3500 MHz

3500-6000 MHz

Transmit Channel #1

Transmit Channel #2

Transmit Channel #3

Transmit Channel #4

IF Mon

IF Mon

IF Mon

IF Mon

Sync

Sync

Sync

AuxPanelEthernet

Ethernet

200 MHz In

200 MHz Out

TAS I/O

Lan I/O

Display

Mouse

Keyboard

MCMS: MCMS: MultichannelMultichannel TransmitterTransmitter


MCMS: 4MCMS: 4--Channel Digital Channel Digital UpconverterUpconverter

Analog Devices AD9857 QDUCsClocked at 200 MSPS

Data +Control

DataDataData


MCMS: AD9857 QDUC ChipMCMS: AD9857 QDUC Chip


Measured Output

I/F board in “Circulate Mode”• I/Q symbols (noise) @ 12.5 Mbaud

AD9857 in “Quadrature Mode”• Interpolation by 4 x 4, to 200 MSPS• NCOM upconversion to 50 MHz• Observing D/A output

GUI-based Control Software

Running in C using LabWindows/CVI

MCMS Validation : Digital MCMS Validation : Digital UpconverterUpconverter


Some MIMO Channel Measurement Some MIMO Channel Measurement Systems Compared (Version 2)Systems Compared (Version 2)


Project Status:Project Status:Mass build of subsystems & final assembly underway Mass build of subsystems & final assembly underway at industry partner’s facilityat industry partner’s facilityDelivery expected October 2004Delivery expected October 2004Long & extensive commissioning process to followLong & extensive commissioning process to follow

Planned First Uses:Planned First Uses:2.4 GHz x 40 MHz indoor channel meas. campaign2.4 GHz x 40 MHz indoor channel meas. campaign2.4 GHz 4 x 16 MIMO/OFDM simplex 2.4 GHz 4 x 16 MIMO/OFDM simplex testbedtestbed

Project Web Site:Project Web Site: http://www.ece.vt.edu/~swe/mcms/http://www.ece.vt.edu/~swe/mcms/

Key people:Key people: S. Ellingson, G. S. Ellingson, G. HampsonHampson (CSIRO), B. (CSIRO), B. Reynolds (Reynolds (AeroflexAeroflex), P. ), P. BohleyBohley ((AeroflexAeroflex), S. Fisher ), S. Fisher ((AeroflexAeroflex),…),…

MCMS Summary MCMS Summary


VTVT--STAR: A 2x2 MIMO STAR: A 2x2 MIMO CommComm TestbedTestbed

5050ΩΩTransmitter/Receiver Input/Output Transmitter/Receiver Input/Output ImpedanceImpedance

26dBm / 0 26dBm / 0 dBmdBmTransmit Power (Maximum/Nominal)Transmit Power (Maximum/Nominal)

Baseband I/Q, 140 mV Baseband I/Q, 140 mV RMSRMS

Receiver OutputReceiver Output

Baseband I/Q, 35 mV RMSBaseband I/Q, 35 mV RMSTransmitter InputTransmitter Input

60 dB60 dBSpuriousSpurious--Free Dynamic Range (SFDR)Free Dynamic Range (SFDR)

--50 50 dBmdBmMaximum Receiver Input PowerMaximum Receiver Input Power--110 110 dBmdBmReceiver Noise FloorReceiver Noise Floor

750 kHz750 kHzMaximum Signal BandwidthMaximum Signal Bandwidth2050 MHz2050 MHzCenter FrequencyCenter Frequency

ValueValueRF ParameterRF Parameter


VTVT--STAR TransmitterSTAR Transmitter

C67DSK

DACTHS5661

DACTHS5661

DACTHS5661

DACTHS5661

RFSECTION

RFSECTION

I1

Q1

I2

Q1

I1

Q1

I2

Q1

DigitalBaseband

AnalogBaseband

CLOCK

C67DSK

DACTHS5661

DACTHS5661

DACTHS5661

DACTHS5661

RFSECTION

RFSECTION

I1

Q1

I2

Q1

I1

Q1

I2

Q1

DigitalBaseband

AnalogBaseband

CLOCK

λ/4 monopole antennas

on a Ground plane

4 THS5661 DAC boards

RF Tx Front End

Interface Hardware


VTVT--STAR ReceiverSTAR Receiver

RF SECTION

RF SECTION

ADC

ADC

ADC

ADC

TI-C67 DSP

THS1206

I1

Q1

I2

Q2

I1

Q1

I2

Q2

Analog Baseband

Digital Baseband

CLOCK


on a Ground plane

RF Rx Front End

THS 1206 ADC boardMated to C67 DSP EVM

Host PC


VTVT--STAR Capacity MeasurementsSTAR Capacity Measurements

2 4 6 8 10 12 140

0.02

0.04

0.06

0.08

0.1

0.12

0.14

PD

F

Capacity [bps/Hz]

SISO Channel: nT = 1; nR = 1 MISO Channel: nT = 2; nR = 1 SIMO Channel (SD): nT = 1; nR = 2 SIMO Channel (OC): nT = 1; nR = 2 MIMO Channel: nT = 2; nR = 2

0 10 20 30 40 50 60 70 802

4

6

8

10

12

14 VT-STAR Channel Capacity per path; nT = 2; nR = 2; Non-Line-of-Sight Measurements

Time [sec]

Cap

acity

[bps

/Hz]

Ch11

Ch12

Ch21

Ch22

CMIMO

HistogramChannel Capacity over time

A key result for flat Rayleigh fading channels (Foschini and Gans)(nT , nR): ( # of Tx. Ant., # of Rx. Ant.)H: Channel matrix of fade coefficients

†2log det

RnT

SNRC I H Hn

⎡ ⎤⎛ ⎞= + ⋅⎢ ⎥⎜ ⎟

⎝ ⎠⎣ ⎦


SDR 3000 Software Radio SystemSDR 3000 Software Radio System


SDRSDR--3000 2x2 Configuration3000 2x2 Configuration

SDR 3000 based Base band and IF

Signia 9136 receiver

16.25 MHZIF

2.05 GHz RF

IF sampling frequency : 65 MHz ( 4 times over sampled )Bandwidth used : 17.56 MHz


VTSTAR RF front end

16.25 MHZIF

2.05 GHz RF Transmit chain

Receive chain


Virginia Tech SummaryVirginia Tech Summary

Current MIMO Initiatives:MCMS VT-STARSDR-3000

The testbeds have strong potential for research contribution in MIMO area:

MIMO measurements and validation of performance improvementDemonstration of existing air interfaces with MIMO technology

These testbeds impart significant value and greater outreach to education:

Used by students to support wireless course projectsDifferent smart antenna algorithms have been demonstrated by studentsEmphasis on programmable, software-defined hardware


Supplemental Slides:Supplemental Slides:

MIMO Testbed Development at MIMO Testbed Development at the MPRG Labthe MPRG LabRaqibul MostafaRaqibul MostafaJeffrey H. ReedJeffrey H. Reed


OverviewOverview

Space Time Coding (STC) OverviewSpace Time Coding (STC) OverviewVirginia Tech Space Time Adaptive Radio Virginia Tech Space Time Adaptive Radio (VT(VT--STAR) description:STAR) description:

System Architecture, RF Specs, TX/RX system, System Architecture, RF Specs, TX/RX system, Interface, DSP Implementation, Indoor Interface, DSP Implementation, Indoor channel measurements channel measurements

SDRSDR--30003000


Space Time Coding (STC) OverviewSpace Time Coding (STC) Overview


STC FundamentalsSTC Fundamentals

((nnTT , , nnRR) ) -- ( # of Tx. Ant., # of Rx. Ant.)( # of Tx. Ant., # of Rx. Ant.)

Rx dataSignal Processing Techniques

Rx

Rx

Rx

•••••

1

2

nR

Info data

Tx

Tx

Tx

Vector Encoder

•••••

ct1

ct2

ctnT

Fading Coefficients

ij

:

α

1

1,2,...,Tn

j i jt ij t t R

ir c ISI MAI j nα η

=

= ⋅ + + + =∑


STC FundamentalsSTC Fundamentals

BackgroundBackgroundSpaceSpace--time codes were proposed by time codes were proposed by TarokhTarokh et. al. in the 1997 et. al. in the 1997 International Symposium on Information Theory (ISIT).International Symposium on Information Theory (ISIT).Capacity analysis of the MIMO channel was proposed by Capacity analysis of the MIMO channel was proposed by FoschiniFoschiniand and GansGans of Lucent Technologies in 1997.of Lucent Technologies in 1997.

Features of STCFeatures of STCMove diversity burden from mobile to base stationMove diversity burden from mobile to base stationDiversity advantageDiversity advantageCoding gainCoding gainIncreased bandwidth efficiencyIncreased bandwidth efficiency


STBC OperationSTBC Operation

S*S*oo--S*S*11

Time Time t+Tt+T

SS11SSoo

Time tTime t

Transmit Transmit Antenna 2Antenna 2

Transmit Transmit Antenna 1Antenna 1

Space

Time

Combiner

Channel Estimation

Maximum Likelihood Detector

Channel Estimation

Space-Time Block Encoding

2222 22

jh e θα=

1212 12

jh e θα=

2121 21

jh e θα=

1111 11

jh e θα=

0s%

1s%

0s

1s1

2

1

2

( )20,min k

ki d s s⎡ ⎤= ⎣ ⎦%

22h12h

21h11h


STBC PerformanceSTBC Performance

mutually uncorrelated mutually uncorrelated Rayleigh fading Rayleigh fading channels channels Channel flat for one Channel flat for one block of STBCblock of STBCperfect knowledge of perfect knowledge of channel state channel state information (CSI) at the information (CSI) at the receiver receiver Total Tx power sameTotal Tx power sameRx Signal power for Rx Signal power for MRRC 3 dB more than MRRC 3 dB more than CC--STBCSTBC


VTVT--STAR: A 2STAR: A 2××2 MIMO Testbed2 MIMO Testbed


IntroductionIntroduction

Objective:Objective:To build a testbed to demonstrate the utility of MIMO techniquesTo build a testbed to demonstrate the utility of MIMO techniquesand to provide with MIMO indoor channel measurementsand to provide with MIMO indoor channel measurements

Testbed development based on software defined radio Testbed development based on software defined radio (SDR) approach for flexibility and reconfigurability(SDR) approach for flexibility and reconfigurabilityDSP processing platform for both the transmitter and the DSP processing platform for both the transmitter and the receiverreceiverImplemented MIMO technique based on Space Time Implemented MIMO technique based on Space Time Block Code (STBC)Block Code (STBC)Other MIMO techniques also possible through DSP Other MIMO techniques also possible through DSP programmingprogramming


VTVT--STAR System ArchitectureSTAR System Architecture

RF Section

Data Conversion

DSP Core

Application Layer (Host)

DSK


RF SpecificationsRF Specifications

5050ΩΩTransmitter/Receiver Input/Output Transmitter/Receiver Input/Output ImpedanceImpedance

26dBm / 0 26dBm / 0 dBmdBmTransmit Power (Maximum/Nominal)Transmit Power (Maximum/Nominal)

Baseband I/Q, 140 mV Baseband I/Q, 140 mV RMSRMS

Receiver OutputReceiver Output

Baseband I/Q, 35 mV RMSBaseband I/Q, 35 mV RMSTransmitter InputTransmitter Input

60 dB60 dBSpuriousSpurious--Free Dynamic Range (SFDR)Free Dynamic Range (SFDR)

--50 50 dBmdBmMaximum Receiver Input PowerMaximum Receiver Input Power--110 110 dBmdBmReceiver Noise FloorReceiver Noise Floor

750 kHz750 kHzMaximum Signal BandwidthMaximum Signal Bandwidth2050 MHz2050 MHzCenter FrequencyCenter Frequency

ValueValueRF ParameterRF Parameter


MultiMulti--Channel RF TransmitterChannel RF Transmitter


MultiMulti--Channel RF ReceiverChannel RF Receiver


Synchronization of 4 DAC Synchronization of 4 DAC EVMsEVMs

•CDC

•• XWE

• DSK J1 interface

•D11-D4•CLK•D11-D4•CLK•D11-D4 •CLK•D11-D4 •CLK

•XD31-XD24 •XD23-XD16 •XD15-XD8 •XD7-XD0

•DAC1•I1

•DAC2•Q1

•DAC3•I2

•DAC4•Q2


C6701 DSPC6701 DSP

32 bit Floating point DSP 32 bit Floating point DSP Advanced Advanced VelociTIVelociTI VLIW architectureVLIW architecture133 MHz133 MHz1064 1064 MFLOPsMFLOPs2 2 MACsMACs per cycle per cycle 32 general32 general--purpose registers purpose registers Eight highly independent functional unitsEight highly independent functional unitsIntegrated Development Environment (IDE) Integrated Development Environment (IDE) Code ComposerCode Composer


VTVT--STAR ReceiverSTAR Receiver

RF SECTION

RF SECTION

ADC

ADC

ADC

ADC

TI-C67 DSP

THS1206

I1

Q1

I2

Q2

I1

Q1

I2

Q2

Analog Baseband

Digital Baseband

CLOCK


on a Ground plane

RF Rx Front End

THS 1206 ADC boardMated to C67 DSP EVM

Host PC


Transmitter: DSP ImplementationTransmitter: DSP ImplementationFlowchart


Receiver: DSP ImplementationReceiver: DSP Implementation


DSP Host CommunicationDSP Host Communication

RealReal--time data exchange (RTDX)time data exchange (RTDX)bibi--directional realdirectional real--time transfer between DSP time transfer between DSP and the host PC and the host PC

Application Layer of radioApplication Layer of radioDisplay key parameters of physical layer in Display key parameters of physical layer in MATLABMATLABCollect data for offline postCollect data for offline post--processing processing Modify a video sequence on a video EmulatorModify a video sequence on a video Emulator


Validation: Back to Back testingValidation: Back to Back testing

• The TX and RX subsystems were connected back-to-back: The DACs and the ADCs were directly connected• Channel estimates showed that direct components (h11 and h22) were much stronger than the cross components (h21 and h12): about 25 dB higher• This setup validates the system.


Measurement set upMeasurement set up

•MPRG DSP LAB AREA LOS and NLOS dry-wood column partition

•Durham Hall 4th Floor Corridor

•Receiver

•Transmitter

•MPRG Student’s

Cubicle Area

Lab with desks Lab with desks workbenches and workbenches and metallic shelvesmetallic shelvesLine Of Sight & Line Of Sight & Non line of sight Non line of sight (NLOS) considered(NLOS) consideredTransmitter and Transmitter and receiver placed in receiver placed in fixed locations fixed locations before before measurementmeasurement


Measured Channel capacityMeasured Channel capacity

2 4 6 8 10 12 140

0.02

0.04

0.06

0.08

0.1

0.12

0.14

PD

F

Capacity [bps/Hz]

SISO Channel: nT = 1; nR = 1 MISO Channel: nT = 2; nR = 1 SIMO Channel (SD): nT = 1; nR = 2 SIMO Channel (OC): nT = 1; nR = 2 MIMO Channel: nT = 2; nR = 2

0 10 20 30 40 50 60 70 802

4

6

8

10

12

14 VT-STAR Channel Capacity per path; nT = 2; nR = 2; Non-Line-of-Sight Measurements

Time [sec]

Cap

acity

[bps

/Hz]

Ch11

Ch12

Ch21

Ch22

CMIMO

HistogramChannel Capacity over time

A key result for flat Rayleigh fading channels (Foschini and Gans)(nT , nR): ( # of Tx. Ant., # of Rx. Ant.)H: Channel matrix of fade coefficients

†2log det

RnT

SNRC I H Hn

⎡ ⎤⎛ ⎞= + ⋅⎢ ⎥⎜ ⎟

⎝ ⎠⎣ ⎦


SDR 3000 Software Radio System SDR 3000 Software Radio System


IntroductionIntroduction

SDRSDR--3000 is a versatile wideband multi3000 is a versatile wideband multi--channel transceiver channel transceiver testbed:testbed:

RealReal--time implementation of communications systemstime implementation of communications systemsBaseband algorithm development and verificationBaseband algorithm development and verificationWideband MIMO algorithm demonstrationWideband MIMO algorithm demonstrationMIMO channel measurement and characterizationMIMO channel measurement and characterization

SDRSDR--3000 offers communications system design and 3000 offers communications system design and implementation using implementation using software defined radiosoftware defined radio (SDR) (SDR) conceptsconcepts


SDRSDR--3000 Basic Features3000 Basic Features

Combines Combines XilinxXilinx VertixVertix FPGA with MPC7410 G4s in a single systemFPGA with MPC7410 G4s in a single system

Supports 4 ADC at 80MHzSupports 4 ADC at 80MHz

Supports 4 DACs at 80/160MHzSupports 4 DACs at 80/160MHz

Support high density and/or high performance software defined raSupport high density and/or high performance software defined radios dios

SDR can support 10s of separate transmit and receive channels, eSDR can support 10s of separate transmit and receive channels, each with ach with independent air interface protocol. independent air interface protocol.

Multiple air interface supported by softwareMultiple air interface supported by software

Software Communications Architecture (SCA) compliant multiSoftware Communications Architecture (SCA) compliant multi--channel channel software radio transceiver systemsoftware radio transceiver system


SCA OverviewSCA Overview

Now a joint project of JTRS and SDR Forum Now a joint project of JTRS and SDR Forum –– most most participants are members of bothparticipants are members of both

An attempt to develop a “universal” SDR architecture An attempt to develop a “universal” SDR architecture (five identified domains)(five identified domains)

•• Emerging standard for software radio complianceEmerging standard for software radio compliance

Still a work in progress Still a work in progress -- Currently v2.2Currently v2.2

SCASCA-- Important step to enable widespread use of Important step to enable widespread use of software radiossoftware radios

Develops an object oriented approach to radio designDevelops an object oriented approach to radio designEnables independent vendors to develop software modules that Enables independent vendors to develop software modules that are compatible with each otherare compatible with each other


System DescriptionSystem Description

3 3 cPCIcPCI--based boardsbased boardsTM1TM1--3300: Analog I/O 3300: Analog I/O board supporting 2 board supporting 2 80MHz ADCs and DACs80MHz ADCs and DACsPROPRO--3100: High speed 3100: High speed processing board with 4 processing board with 4 user programmable user programmable XilinxXilinx VirtexVirtex--II II FPGAsFPGAs, , and 1 MPC7410 and 1 MPC7410 PowerPCPowerPCProPro--3500: Signal 3500: Signal processing board with 2 processing board with 2 G4 PowerPCs and 1 G4 PowerPCs and 1 MPC7410 PowerPC for MPC7410 PowerPC for controlling the boardcontrolling the board


SDRSDR--3000 Functional Block Diagram3000 Functional Block Diagram

Air Interface

High Frequency

Ana log

Intermed iate

Frequency

Digita l

Intermed iate

Frequency

Baseband Data,

Encoded

Chnnelizer

SDR-3000 T ransceiver Subsystem

Baseband processing

Stage 1 Stage 2 Stage 3 Stage 4 Stage 5

Single Board

Computer

Analog-to -DigitalConve rsion

DigitalDown Conversion

Signa lProcessingRF Analog-to -Digital

Conve rsionDigital

Down ConversionSigna l

ProcessingRF

Digital-to-AnalogConve rsion

DigitalUp Conversion

Signa lProcessingRF Digital-to-Analog

Conve rsionDigital

Up ConversionSigna l

ProcessingRF

Baseband Data,

Decoded

FPGA

PPC

PPC

PRO-3500

FPGA

PPC

PPC

PRO-3500

FPGAFPGAFPGAFPGAI/O

Framer

PRO-3100

FPGAFPGAFPGAFPGAI/O

Framer

PRO-3100

ADCADC

ADCADC

DACDAC

DACDAC

TM1-3300

ADCADC

ADCADC

DACDAC

DACDAC

ADCADC

ADCADC

DACDAC

DACDAC

TM1-3300

(From Sp ectrum signal Processin g)


SDRSDR--3000 Testbed Goals3000 Testbed Goals

Build a testbed based on SDR 3000 for MIMO testingBuild a testbed based on SDR 3000 for MIMO testing

Perform IF digital up and down conversion operations Perform IF digital up and down conversion operations within the PROwithin the PRO--3500.3500.

Signaling format: OFDM based physical layer.Signaling format: OFDM based physical layer.

TX RF frontTX RF front--end: VTSTAR transmitterend: VTSTAR transmitter

RX RF frontRX RF front--end: SIGNIA 9136 receiver end: SIGNIA 9136 receiver


SystemSystem


Signia 9136 receiver

16.25 MHZIF

2.05 GHz RF

IF sampling frequency : 65 MHz ( 4 times over sampled )Bandwidth used : 17.56 MHz


VTSTAR RF front end

16.25 MHZIF

2.05 GHz RF Transmit chain

Receive chain


Current statusCurrent status

Implemented 802.11a based OFDM physical layer Implemented 802.11a based OFDM physical layer baseband on PRObaseband on PRO--35003500

Validated on SDRValidated on SDR--3000 using TX/RX loop back3000 using TX/RX loop back

Digital up and down conversion from base band to IF Digital up and down conversion from base band to IF tested on SDRtested on SDR--3000 through loop back.3000 through loop back.

RF front end tested through loop back.RF front end tested through loop back.

IF to RF integration in progress.IF to RF integration in progress.

Documents

MIMO Development Efforts at Virginia Tech · Slide 2 Ellingson, Mostafa, & Reed – Sept 19, 2004 MIMO at Virginia Tech Virginia Tech is interested in all aspects of MIMO: MIMO channel