EE 200 Midterm Exam 19 March 2015

Last Name (Print):

First Name (Print):

ID number (Last 4 digits):

Section:

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

Problem Weight Score

1 25

2 25

3 25

4 25

Total 100

INSTRUCTIONS

1. You have 2 hours to complete this exam.

2. This is a closed book exam. You may use one 8.5”× 11” note sheet.

3. Calculators are allowed.

4. Solve each part of the problem in the space following the question. If you need more space, continue your solutionon the reverse side labeling the page with the question number; for example, Problem 1.2 Continued. NOcredit will be given to solutions that do not meet this requirement.

5. DO NOT REMOVE ANY PAGES FROM THIS EXAM. Loose papers will not be accepted and agrade of ZERO will be assigned.

6. The quality of your analysis and evaluation is as important as your answers. Your reasoning must be preciseand clear; your complete sentences should convey what you are doing. To receive credit, you must showyour work.

7. Any student caught cheating on an exam will receive a grade of zero for the exam. Additional sanctions,including assigning an XF grade, will be pursued following university guidelines.

1

Problem 1: (25 Points)

1. (8 points) Consider a Moore finite state machine with two inputs, w and x, and a single output y.

(a) (6 points) Using the state diagram in Figure 1, complete the state table in Table 1. Where appropriate,mark don’t care conditions for the inputs using the symbol ×.

Figure 1: State diagram for a Moore finite state machine with inputs w and x, and output y.

Present State Inputs Next State OutputQA QB w x QA QB y

S0 0 0 S0 0 0S0 0 0 S1 0 1

S1 0 1 S2 1 0S2 1 0 S1 0 1

S2 1 0 S0 0 0

Table 1: State table for the Moore finite state machine in Figure 1.

(b) (2 points) How many D-type flip-flops are required to realize the finite state machine in part 1? To receivecredit, you must justify your answer using one or two short sentences.

2

2. (8 points) Consider another Moore finite state machine, where the three-variable Karnaugh map in Figure 2corresponds to the D-type flip-flop input DA.

Figure 2: Three-variable Karnaugh map for determining DA.

(a) (4 points) Using the three-variable Karnaugh map in Figure 2, determine a simplified expression for DA.To receive partial credit, you must circle the minterms that you grouped together in the Karnaugh mapshown in Figure 2.

(b) (4 points) Assuming that the expression for DB is

DB = x̄Q̄B + QB ,

and that the signals x, QB , and Q̄B are available, realize the signal DB using 2-input NAND gates andneatly sketch your circuit below.

3

3. (9 points) Figure 3 represents a Moore finite state machine that has inputs x and y and output z. Completethe state diagram of the finite state machine in Figure 4.

/* *************** INPUT PINS *********************/

PIN 1 = CLK;

PIN 2 = x;

PIN 3 = y;

/* *************** OUTPUT PINS ********************/

PIN 21 = QA;

PIN 22 = QB;

PIN 23 = z;

/* *************** DEFINE STATES FOR FSM **********/

FIELD state_n = [QA, QB];

$define S0 ’b’00

$define S1 ’b’01

$define S2 ’b’10

/* *************** FLIP-FLOP CONTROL SIGNALS ******/

[QA, QB].SP = ’b’0;

[QA, QB].AR = ’b’0;

[QA, QB].OE = ’b’1;

[QA, QB].CK = CLK;

/* *************** FSM OUTPUT SIGNAL ******************/

z = QA # QB;

/* *************** IMPLEMENT FSM ******************/

SEQUENCED state_n {

PRESENT S0

IF !x & !y NEXT S0;

IF x $ y NEXT S1;

IF x & y NEXT S2;

PRESENT S1

IF x & y NEXT S2;

DEFAULT S1;

PRESENT S2

IF x & !y NEXT S0;

IF !x & y NEXT S1;

DEFAULT S2;

}

Figure 3: WinCUPL code for implementing a Moore finite state machine.

4

Figure 4: State diagram for a Moore finite state machine realized using the HDL code in Figure 3.

5

Problem 2: (25 Points)

1. (9 points) Figure 5(A) shows a mixed-signal circuit, with input Vin(t) and output Vout(t), that uses two CMOSNOT gates and one CMOS XOR gate. The low-state output voltage VL = VSS = 0 V while the high-stateoutput voltage VH = VDD. The circuit is driven by the pulse in Figure 5(B). Immediately prior to the changein the input at time t = 0, there is no energy stored in the capacitor. Neatly sketch the resulting waveformsvC(t) and vout(t) in Figure 6. To receive full credit:

• Carefully label the maximum and minimum values of the waveforms vC(t) and vout(t).

• Determine the width of any pulse appearing in the output vout(t) in terms of the parameters R and C.

• Show the calculations used to derive the pulse width in terms of the parameters R and C.

• Indicate the pulse width in Figure 6.

Figure 5: (A) CMOS circuit with input vin(t) and output vout(t) and (B) the input waveform vin(t).

6

Figure 6: Waveforms for the circuit in Figure 5.

7

2. (8 points) The passive RL circuit in Figure 7 realizes a filter network with input voltage f(t) and output voltagey(t). Determine the frequency response function in terms of R and L and express your answer in the form

H(ω) =Ỹ

F̃=

K

ω/ωc + 1.

Figure 7: Passive filter network.

8

3. (8 points) An EE 200 students designs an active low-pass filter whose frequency response function has the form

H(ω) =Ỹ

F̃=

K

ω/ωc + 1.

In response to the inputf(t) = 2 + 2

√2 cos(10t + 135◦),

the active filter produces the sinusoidal steady-state response

y(t) = 4 + 4 cos(10t + 90◦).

Determine the numeric value of the constant parameters K and ωc. Justify your answer using one or two shortsentences, or by showing appropriate calculations.

9

Problem 3: (25 Points)

1. (7 points) The Concatenate Strings function node concatenates input strings and 1D arrays of strings into asingle output string. For example, the indicator labeled Output displays the string ”Hello World” after the VIin Figure 8 executes. Now consider the VI in Figure 9, noting there is a blank space after each name in the

Figure 8: LabVIEW code demonstrating the Concatenate Strings function node.

string constants.

Figure 9: Block diagram for Problem 3 Part 1.

(a) (2 points) What does the indicator labeled Output display when the value of the control labeled Input Nis 0? Justify your answer in a short sentence.

(b) (5 points) What does the indicator labeled output display when the value of the control labeled Input Nis 2? To receive partial credit, show how you derived your answer.

10

2. (8 points) Consider the VI in Figure 10. Determine the number of rows and columns in the 2D array displayedby the indicator labeled ResultArray. To receive partial credit, justify your answer.

Figure 10: Block diagram for Problem 3 Part 2.

11

3. (6 points) An engineer wishes to accomplish the following sequential tasks using the VI in Figure 11:

• Step 1: Display a dialog box requesting the user to connect the device under test (DUT) to the myDAQ.

• Step 2: Write to the digital output lines DI0 0 through DI0 3 the pattern FTTF

• Step 3: Write to the digital output lines DI0 0 through DI0 3 the pattern TFFT

• Step 4: Display a dialog box requesting the user to disconnect the DUT from the myDAQ.

• Step 5: Stop execution of the VI

When the engineer executes the code, after completing Step 1 the code terminates and displays the error code 0.Help the engineer debug the code by identifying the two programming errors and the corresponding corrections.

12

Figure 11: Block diagram for Problem 3 Part 3.

13

4. (4 points) The block diagram in Figure 12 violates several coding standards. Identify any four of codingguideline violations.

Figure 12: Block diagram for Problem 3 Part 4.

14

Problem 4: (25 Points)

1. (13 points) Given the SPICE model in Figure 13, draw the corresponding circuit diagram. To receive fullcredit:

• Indicate the node labels in your diagram.

• For each resistor and capacitor, indicate both the literal name (for example L1) and its numeric valuealong with correct units (for example, 10 µH).

• If the diagram contains dependent sources, clearly label the controlling voltages as well as the gain value.

.SUBCKT Amp 1 2 6

rRin 1 2 10MEG

cC2 1 6 10P

eE1 3 0 1 2 100k

rR1 3 4 1k

cC1 4 0 1n

rRo 5 6 100M

eE2 5 0 4 0 1

.ENDS Amp

Figure 13: SPICE model for a Multisim component that realizes an amplifier.

15

2. (12 points) Figure 14 shows an active filter circuit captured in MULTISIM while Figure 15 shows the ULTI-BOARD layout.

Figure 14: Circuit diagram of an active filter.

Figure 15: Realization of the active filter using a single copper layer on the bottom of the printed circuit board.

16

(a) (6 points) Is the printed circuit board layout in Figure 15 consistent with the circuit diagram in Figure14? If not, state the differences.

(b) (6 points) Regardless of whether or not the printed board circuit layout is consistent with the circuitdiagram, critique the layout in Figure 15 with respect to trace routing. Suggest changes to improve theprinted circuit board layout.

17

EE 200 Midterm Exam 19 March 2015

Last Name (Print):

First Name (Print):

ID number (Last 4 digits):

Section:

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

Problem Weight Score

1 25

2 25

3 25

4 25

Total 100

INSTRUCTIONS

1. You have 2 hours to complete this exam.

2. This is a closed book exam. You may use one 8.5”× 11” note sheet.

3. Calculators are allowed.

4. Solve each part of the problem in the space following the question. If you need more space, continue your solutionon the reverse side labeling the page with the question number; for example, Problem 1.2 Continued. NOcredit will be given to solutions that do not meet this requirement.

5. DO NOT REMOVE ANY PAGES FROM THIS EXAM. Loose papers will not be accepted and agrade of ZERO will be assigned.

6. The quality of your analysis and evaluation is as important as your answers. Your reasoning must be preciseand clear; your complete sentences should convey what you are doing. To receive credit, you must showyour work.

7. Any student caught cheating on an exam will receive a grade of zero for the exam. Additional sanctions,including assigning an XF grade, will be pursued following university guidelines.

1

Problem 1: (25 Points)

1. (8 points) Consider a Moore finite state machine with two inputs, w and x, and a single output y.

(a) (6 points) Using the state diagram in Figure 1, complete the state table in Table 1. Where appropriate,mark don’t care conditions for the inputs using the symbol ×.

Figure 1: State diagram for a Moore finite state machine with inputs w and x, and output y.

Present State Inputs Next State OutputQA QB w x QA QB y

S0 0 0 S0 0 0S0 0 0 S1 0 1

S1 0 1 S2 1 0S2 1 0 S1 0 1

S2 1 0 S0 0 0

Table 1: State table for the Moore finite state machine in Figure 1.

(b) (2 points) How many D-type flip-flops are required to realize the finite state machine in part 1? To receivecredit, you must justify your answer using one or two short sentences.

2

2. (8 points) Consider another Moore finite state machine, where the three-variable Karnaugh map in Figure 2corresponds to the D-type flip-flop input DA.

Figure 2: Three-variable Karnaugh map for determining DA.

(a) (4 points) Using the three-variable Karnaugh map in Figure 2, determine a simplified expression for DA.To receive partial credit, you must circle the minterms that you grouped together in the Karnaugh mapshown in Figure 2.

(b) (4 points) Assuming that the expression for DB is

DB = x̄Q̄B + QB ,

and that the signals x, QB , and Q̄B are available, realize the signal DB using 2-input NAND gates andneatly sketch your circuit below.

3

3. (9 points) Figure 3 represents a Moore finite state machine that has inputs x and y and output z. Completethe state diagram of the finite state machine in Figure 4.

/* *************** INPUT PINS *********************/

PIN 1 = CLK;

PIN 2 = x;

PIN 3 = y;

/* *************** OUTPUT PINS ********************/

PIN 21 = QA;

PIN 22 = QB;

PIN 23 = z;

/* *************** DEFINE STATES FOR FSM **********/

FIELD state_n = [QA, QB];

$define S0 ’b’00

$define S1 ’b’01

$define S2 ’b’10

/* *************** FLIP-FLOP CONTROL SIGNALS ******/

[QA, QB].SP = ’b’0;

[QA, QB].AR = ’b’0;

[QA, QB].OE = ’b’1;

[QA, QB].CK = CLK;

/* *************** FSM OUTPUT SIGNAL ******************/

z = QA # QB;

/* *************** IMPLEMENT FSM ******************/

SEQUENCED state_n {

PRESENT S0

IF !x & !y NEXT S0;

IF x $ y NEXT S1;

IF x & y NEXT S2;

PRESENT S1

IF x & y NEXT S2;

DEFAULT S1;

PRESENT S2

IF x & !y NEXT S0;

IF !x & y NEXT S1;

DEFAULT S2;

}

Figure 3: WinCUPL code for implementing a Moore finite state machine.

4

Figure 4: State diagram for a Moore finite state machine realized using the HDL code in Figure 3.

5

Problem 2: (25 Points)

1. (9 points) Figure 5(A) shows a mixed-signal circuit, with input Vin(t) and output Vout(t), that uses two CMOSNOT gates and one CMOS XOR gate. The low-state output voltage VL = VSS = 0 V while the high-stateoutput voltage VH = VDD. The circuit is driven by the pulse in Figure 5(B). Immediately prior to the changein the input at time t = 0, there is no energy stored in the capacitor. Neatly sketch the resulting waveformsvC(t) and vout(t) in Figure 6. To receive full credit:

• Carefully label the maximum and minimum values of the waveforms vC(t) and vout(t).

• Determine the width of any pulse appearing in the output vout(t) in terms of the parameters R and C.

• Show the calculations used to derive the pulse width in terms of the parameters R and C.

• Indicate the pulse width in Figure 6.

Figure 5: (A) CMOS circuit with input vin(t) and output vout(t) and (B) the input waveform vin(t).

6

Figure 6: Waveforms for the circuit in Figure 5.

7

2. (8 points) The passive RL circuit in Figure 7 realizes a filter network with input voltage f(t) and output voltagey(t). Determine the frequency response function in terms of R and L and express your answer in the form

H(ω) =Ỹ

F̃=

K

ω/ωc + 1.

Figure 7: Passive filter network.

8

3. (8 points) An EE 200 students designs an active low-pass filter whose frequency response function has the form

H(ω) =Ỹ

F̃=

K

ω/ωc + 1.

In response to the inputf(t) = 2 + 2

√2 cos(10t + 135◦),

the active filter produces the sinusoidal steady-state response

y(t) = 4 + 4 cos(10t + 90◦).

Determine the numeric value of the constant parameters K and ωc. Justify your answer using one or two shortsentences, or by showing appropriate calculations.

9

Problem 3: (25 Points)

1. (7 points) The Concatenate Strings function node concatenates input strings and 1D arrays of strings into asingle output string. For example, the indicator labeled Output displays the string ”Hello World” after the VIin Figure 8 executes. Now consider the VI in Figure 9, noting there is a blank space after each name in the

Figure 8: LabVIEW code demonstrating the Concatenate Strings function node.

string constants.

Figure 9: Block diagram for Problem 3 Part 1.

(a) (2 points) What does the indicator labeled Output display when the value of the control labeled Input Nis 0? Justify your answer in a short sentence.

(b) (5 points) What does the indicator labeled output display when the value of the control labeled Input Nis 2? To receive partial credit, show how you derived your answer.

10

2. (8 points) Consider the VI in Figure 10. Determine the number of rows and columns in the 2D array displayedby the indicator labeled ResultArray. To receive partial credit, justify your answer.

Figure 10: Block diagram for Problem 3 Part 2.

11

3. (6 points) An engineer wishes to accomplish the following sequential tasks using the VI in Figure 11:

• Step 1: Display a dialog box requesting the user to connect the device under test (DUT) to the myDAQ.

• Step 2: Write to the digital output lines DI0 0 through DI0 3 the pattern FTTF

• Step 3: Write to the digital output lines DI0 0 through DI0 3 the pattern TFFT

• Step 4: Display a dialog box requesting the user to disconnect the DUT from the myDAQ.

• Step 5: Stop execution of the VI

When the engineer executes the code, after completing Step 1 the code terminates and displays the error code 0.Help the engineer debug the code by identifying the two programming errors and the corresponding corrections.

12

Figure 11: Block diagram for Problem 3 Part 3.

13

4. (4 points) The block diagram in Figure 12 violates several coding standards. Identify any four of codingguideline violations.

Figure 12: Block diagram for Problem 3 Part 4.

14

Problem 4: (25 Points)

1. (13 points) Given the SPICE model in Figure 13, draw the corresponding circuit diagram. To receive fullcredit:

• Indicate the node labels in your diagram.

• For each resistor and capacitor, indicate both the literal name (for example L1) and its numeric valuealong with correct units (for example, 10 µH).

• If the diagram contains dependent sources, clearly label the controlling voltages as well as the gain value.

.SUBCKT Amp 1 2 6

rRin 1 2 10MEG

cC2 1 6 10P

eE1 3 0 1 2 100k

rR1 3 4 1k

cC1 4 0 1n

rRo 5 6 100M

eE2 5 0 4 0 1

.ENDS Amp

Figure 13: SPICE model for a Multisim component that realizes an amplifier.

15

2. (12 points) Figure 14 shows an active filter circuit captured in MULTISIM while Figure 15 shows the ULTI-BOARD layout.

Figure 14: Circuit diagram of an active filter.

Figure 15: Realization of the active filter using a single copper layer on the bottom of the printed circuit board.

16

(a) (6 points) Is the printed circuit board layout in Figure 15 consistent with the circuit diagram in Figure14? If not, state the differences.

(b) (6 points) Regardless of whether or not the printed board circuit layout is consistent with the circuitdiagram, critique the layout in Figure 15 with respect to trace routing. Suggest changes to improve theprinted circuit board layout.

17

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