MiDAS Family SeJong Family - CORERIVER · PDF fileSeJong Family CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, ... SeJong200

MiDAS Family

www.coreriver.com (E-mail : [email protected])

SeJong Family

CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time.

CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a service through its homepage.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

The CORERIVER products listed in this document are intended for usage in general electronics applications. These CORERIVER products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury.

Brief Manual of SeJong200 Family

V1.9

September, 2012

Flash /ISP / IAP 16-bit DSP

with Capacitive Touch Sensors and LCD Driver

BM-SeJong200-V1.9

SeJong200 Family [2]

7. Absolute Maximum Ratings

8. DC Characteristics

9. AC Characteristics

10.Package Dimensions

11.Supporting Tools

Appendix A. Revision History

Contents

1. Product Overview

2. Features

3. Block Diagram

4. Pin Configurations

5. Pin Descriptions

6. Function Descriptions

CPU Descriptions - Memory Organization - Memory Descriptions - Reset Sequence - Operating Modes - Clock Network

Peripheral Descriptions - I/O Ports - The ESD Structure of Pads - LVR (Low Voltage Reset) - WDT (Watchdog Timer) - Timer/Counter : PTC0/1/2/3/4 - UART (Universal Async. RX/TX) - I2C, I2S, PWMA

- UR,LCDC,RTC - Touch Sensor - ADC (Analog-to-Digital Converter) - Interrupt Controller - Reset Circuit - Power Management - IAP


1. Product Overview

CORERIVER’s SeJong200 Family is a group of fast 16-bit Digital Signal Processor.

The DSP of SeJong200 Family supports 160 instructions.

Additional peripherals of SeJong200 Family: I2C / SPI / UART / I2S / UR / RTC / LCDC /WDT / LVD / POR.

Power saving modes

Noise tolerant scheme

Provides Easy-to-Use training-kit system


1. Product Overview (Cont’d)

A. SeJong200 Family

Product FLASH [Byte]

EEPROM

[Byte]

RAM [Byte]

Volt [V]

Freq [MHz]

T/C [16 bits]

COM I/O WDT RTC ADC

(bit X Ch) PWM

(bit X ch) Touch

Channel Special

Function Package Others

SEJONG200

32k (2k) 2k 2.2 ~

3.6 48 5

2 UART 2 I2C 1 SPI

1 1

24 X 21 8 X 32 26 OP AMP + ADC

(Differential ADC) Universal Remote

Controller (8 X 8)

LCD Driving Controller (4COM X 32Seg.)

I2S

88-MLF

IAP ISP

JTAG LVR POR RTC POSC DSP

SEJONG210 24 X 14 8 X 27 26 68-MLF

SEJONG220 24 X 8 8 X 17 16

OP AMP + ADC (Differential ADC) Universal Remote

Controller (8 X 8)

LCD Driving Controller (4COM X 24Seg.)

I2S

48-MLF


2. Features CPU

Digital Signal Processor (DSP) Signal Processing 160 Instructions 16 / 32 / 48-bit Variable Length Instructions MAC with 17 bits X 17 bits Multipliers

32kB Flash (Including 2kB User EEPROM)

2kB Internal RAM 1kB for SRAM Code Fetch (Timing Critical Function) or Data 1kB for Data, Stack, & Etc

Operating Voltage : +2.2V to +3.6V Operating Frequency

Max. 24MHz @+3.0V & FLASH Max. 48MHz @+3.0V & RAM

Internal Ring OSC with Calibration function 24MHz @+3.0V (+/- 1%) 32kHz @+1.62V (+/- 10%) : Low Power OSC.

26-Chanel (SJ200,SJ210), 16-Chanel (SJ220) Touch Sensing Capacitive Type Touch Sensing Digital Sensing 16-bit Level Resolution

Supporting ISP/IAP/MDS Five 16-bit Timer/Counters 32-bit Programmable Watchdog Timer 1-channel I2S(Master) RTC (BCD) 2-channel I2C Communication (Master/Slave)

1-channel SPI Communication (Master/Slave) 2-channel UART Communication 8-channel (SJ220), 14-channel (SJ210), 21-channel (SJ200)

OP-AMP + 12-bit ADC (24-bit resolution) 17-channel (SJ220), 27-channel (SJ210), 32-channel(SJ200)

8-bit High Speed PWM for LED Dimming Universal Remote Controller (8x8) 4comx32seg (SJ200,SJ210), 4comx24seg (SJ220)

LCD controller 28 Interrupt Sources

Timer0/1/2/3/4, WDT, SPI, I2C0/1, UART0/1, I2S,TS, ADC, RTC 14 External Interrupt Sources : Both Edge/Level Two-level Interrupt Priority

Reset Sources On-chip Power-On-Reset (POR) External Reset Low Voltage Detector Reset (LVR) Watchdog Timer Reset

Power Down Wake-up Sources Reset Sources + 14 External Interrupt (Both Levels) WDT interrupt

Power Consumption Active Current : Max. 1mA @+3.3V, 2MHz Idle Current : Max. 0.5mA @+3.3V, 2MHz Stop Current : Max. 5uA @+3.3V

E.S.D. Protection up to 2,000V for All Pin

Latch-up Protection Up to ±200mA Package

48-MLF (SJ220), 64-MLF (SJ210), 88-MLF (SJ200)

SeJong200 Family

3. Block Diagram

[6]

Clock Circuit

CPU BUS

Interrupt Controller (EINT:14)

VDDIO

Port

JTAG Controller

XTAL1

DSP Core

External Osc.

Internal OSC.

(48MHz) UART0

PWM (32ch)

VDDINT

POR LVR

Vol. Reg.

TCLK TMS TRST TDI TDO

UART1

I2C0

I2C1 SPI ADC

(21 ch)

XTAL2

VSS VDDA VDDINTA VSSA

RAM (2KB)

FLASH (32kB)

Timer0

Timer1

Timer2 EEPROM

(2kB)

WDT (32-bit)

Stop Timer

Vol. Reg. (TS)

P0[15:0] P1[15:0] P2[15:0] P3[6:0]

Touch Sensor (26ch)

TC[25:0]

Timer3

Timer4

P4[14:0]

OP AMP

(D:21 ch)

RTC

I2S

RTC_XTAL1

External Osc.

Internal Osc.(32KHz)

RTC_XTAL2

LCDC UR (8x8)


4. Pin Configurations : 48-MLF

ISP / MDS Pin Configuration

VDDIO #10, #30)

VSS (Bottom PAD)

TDI (#48, with 10kΩ Pull-up R)

TDO (#1, with 10kΩ Pull-up R)

TCLK (#2, with 10kΩ Pull-up R)

TMS (#3, with 10kΩ Pull-up R)

TRST (#4, with 10kΩ Pull-up R) [ 48-pin MLF : 6mm X 6mm ]

28

27

26

25

36

35

34

33

32

31

30

29

48

47

46

45

44

43

42

41

40

39

38

37

13

14

15

16

17

18

19

20

21

22

23

24

9

10

11

12

1

2

3

4

5

6

7

8

SEJONG220-ML48IP

VSS (Bottom PAD)

P0.03 / PWM

0.03 / TS0.03 / COM

0

P4.1

0 /

REM

OU

T /

ADC4

.10(

VN20

,S14

)

P4.0

9 /

I2S_

DAT

A /

TXD

1_A

/ AD

C4.0

9(VP

20,S

13)

P4.0

8 /

I2S_

CLK

/ RX

D1_

A /

ADC4

.08(

VN19

,S12

)

P4.0

7 /

I2S_

WS

/ RT

COU

T /

ADC4

.07(

VP19

,S11

)

P4.0

2 /

ADC4

.02(

VN16

) /

SEG

3

P4.0

1 /

ADC4

.01(

VP16

) /

SEG

2

P4.0

0 /

ADC4

.00(

VN15

) /

SEG

1

P2.1

5 /

INT1

5 /

ADC2

.15(

VP15

) /

SEG

0

P2.1

4 /

INT1

4 /

ADC2

.14(

VN14

) /

SEG

23

VDDIO

P2.08 / INT12 / ADC2.08(VN11) / SEG21

P2.07 / INT11 / ADC2.07(VP11) / SEG20

P2.06 / INT10 / ADC2.06(VN10) / SEG19

P2.04 / INT8 / TS2.04 / SEG17

P1.11 / PWM1.11 / ADC1.11(VN6) / SEG16

P1.10 / PWM1.10 / ADC1.10(VP6) / SEG15

P1.09 / PWM1.09 / TS1.09 / SEG14 VDDIO

VDDA

VDDINTA

VSSA

CEB

XTAL1 / TXD1 / I2C1_SDA / CLO / P3.06

XTAL2 / RXD1 / I2C1_SCL / INT5 / P3.05

TRST / RESETB / INT4 / P3.04

VDDINT P1.08 / PWM1.08 / TS1.08 / SEG13

P1.07 / PWM1.07 / TS1.07 / SEG12

P2.05 / INT9 / ADC2.05(VP10) / SEG18

P4.1

3 /

RTC_

XTAL

2

P4.1

4 /

RTC_

XTAL

1

TMS / SPI_MOSI / I2C0_SDA / INT3 / P3.03

TCLK / SPI_MISO / I2C0_SCL / INT2 / P3.02

P3.0

0 /

INT0

/ TI

MER

2 /

RXD

0 /

SPI_

SSB

/ T

DI

TDO / SPI_SCK / TXD0 / TIMER4 / INT1 / P3.01

P0.04 / PWM

0.04 / TS0.04 / COM

1

P0.05 / PWM

0.05 / TS0.05 / COM

2

P0.06 / PWM

0.06 / TS0.06 / COM

3

P0.07 / PWM

0.07 / TS0.07 / SEG4

P1.00 / PWM

1.00 / TS1.00 / SEG5

P1.01 / PWM

1.01 / TS1.01 / SEG6

P1.02 / PWM

1.02 / TS1.02 / SEG7

P1.03 / PWM

1.03 / TS1.03 / SEG8

P1.04 / PWM

1.04 / TS1.04 / SEG9

P1.05 / PWM

1.05 / TS1.05 / SEG10

P1.06 / PWM

1.06 / TS1.06 / SEG11

P2.13 / INT13 / ADC2.13(VP14) / SEG22


4. Pin Configurations : 68-MLF (1 of 2)

Pin No. Pin Name

1 T_MOD 2 P3.00 / INT0 / TIMER2/ RXD0 / SPI_SSB / TDI

3 P3.01 / INT1 / TIMER4/ TXD0 / SPI_SCK / TDO

4 P3.02 / INT2 / I2C0_SCL / SPI_MISO / TCLK

5 P3.03 / INT3 / I2C0_SDA / SPI_MOSI / TMS

6 P3.04 / INT4 / RESETB / TRST

7 P3.05 / INT5 / I2C1_SCL / RXD1 / XTAL2

8 P3.06 / CLO / I2C1_SDA / TXD1 / XTAL1

9 VSSA

10 VDDINTA

11 VDDA

12 VDDIO 13 VDDINT

14 CEB

15 P0.00 / PWM0.00 / ADC0.00(VP1) / SEG24 16 P0.01 / PWM0.01 / ADC0.01(VN1) / SEG25 17 P0.02 / PWM0.02 / TS0.02 / SEG26 18 P0.03 / PWM0.03 / TS0.03 / COM0

19 P0.04 / PWM0.04 / TS0.04 / COM1 20 P0.05 / PWM0.05 / TS0.05 / COM2 21 P0.06 / PWM0.06 / TS0.06 / COM3 22 P0.07 / PWM0.07 / TS0.07 / SEG4 23 P0.08 / PWM0.08 / ADC0.08(VP2) / SEG27 24 P0.09 / PWM0.09 / ADC0.09(VN2) / SEG28 25 VDDIO 26 P0.14 / PWM0.14 / ADC0.14(VP5) / SEG29 27 P0.15 / PWM0.15 / ADC0.15(VN5) / SEG30

68

67

66

54

53

52

18

19

20

32

33

34

51

50

49

37

36

35

1

2

3

15

16

17

SEJONG210-ML68IP

VSS (Bottom PAD)

[ 68-pin MLF : 8mm X 8mm ]


VDDIO (#12, #25, #43, #60)

VSS (Bottom PAD)





TRST (#6, with 10kΩ Pull-up R)



Pin No. Pin Name

28 P1.00 / PWM1.00 / TS1.00 / SEG5 29 P1.01 / PWM1.01 / TS1.01 / SEG6 30 P1.02 / PWM1.02 / TS1.02 / SEG7 31 P1.03 / PWM1.03 / TS1.03 / SEG8 32 P1.04 / PWM1.04 / TS1.04 / SEG9 33 P1.05 / PWM1.07 / TS1.05 / SEG10 34 P1.06 / PWM1.06 / TS1.06 / SEG11 35 P1.07 / PWM1.07 / TS1.07 / SEG12 36 P1.08 / PWM1.08 / TS1.08 / SEG13 37 P1.09 / PWM1.09 / TS1.09 / SEG14

38 P1.10 / PWM1.10 / ADC1.10(VP6) / SEG15 39 P1.11 / PWM1.11 / ADC1.11(VN6) / SEG16 40 P1.12 / PWM1.12 / ADC1.12(VP7) / SEG31 41 P1.13 / PWM1.13 / SPI_SSB_A / ADC1.13(VN7) / TS1.13 42 P1.14 / PWM1.14 / SPI_SCK_A / TS1.14 / 43 VDDIO 44 P2.03 / SPI_MOSI_A / ADC2.02(S6) /T S2.03 45 P2.04 / INT8 / TS2.04 / SEG17 46 P2.05 / INT9 / ADC2.05(VP10) / SEG18 47 P2.06 / INT10 / ADC2.06(VN10) / SEG19 48 P2.07 / INT11 / ADC2.07(VP11) / SEG20 49 P2.08 / INT12 / ADC2.08(VN11) / SEG21 50 P2.09 / SPI_MISO_A /TS2.09 51 P2.12 / ADC2.12 / TS2.12

Pin No. Pin Name

52 P2.13 / INT13 / ADC2.13(VP14) / SEG22 53 P2.14 / INT14 / ADC2.14(VN14) / SEG23 54 P2.15 / INT15 / ADC2.15(VP15) / SEG0 55 P4.00 / ADC4.00(VN15) / SEG1 56 P4.01 / ADC4.01(VP16) / SEG2 57 P4.02 / ADC4.02(VN16) / SEG3 58 P4.03 / I2S_CLK_A / I2C1_SCL_A / ADC4.03(VP17) / TS4.03 59 P4.04 / I2S_DATA_A / I2C1_SDA_A / ADC4.04(VN17) / TS4.04 60 VDDIO 61 P4.13 / RTC_XTAL2 62 P4.14 / RTC_XTAL1 63 P4.07 / I2S_WS / RTCOUT / ADC4.07(VP19,S11) 64 P4.08 / I2S_CLK / RXD1_A / ADC4.08(VN19,S12) 65 P4.09 / I2S_DATA / TXD1_A / ADC4.09(VP20,S13) 66 P4.10 / REMOUT/ ADC4.10(VN20,S14) 67 P4.11 / I2S_DATA_IN / ADC4.10(VP21) / TS4.11 68 P4.12 / ADC4.10(VN21) / TS4.12



Pin No. Pin Name

1 P4.12 / ADC4.10(VN21) / TS4.12 2 T_MOD 3 P3.00 / INT0 /TIMER2/ RXD0 / SPI_SSB / TDI/

4 P3.01 / INT1 /TIMER4/ TXD0 / SPI_SCK / TDO

5 P3.02 / INT2 / I2C0_SCL / SPI_MISO / TCLK

6 P3.03 / INT3 / I2C0_SDA / SPI_MOSI / TMS

7 P3.04 / INT4 / RESETB / TRST

8 P3.05 / INT5 / I2C1_SCL / RXD1 / XTAL2

9 P3.06 / CLO / I2C1_SDA / TXD1 / XTAL1

10 VSSA

11 VDDINTA

12 VDDA

13 VDDIO 14 VDDINT

15 VSS 16 VSS

17 CEB

18 P0.00 / PWM0.00 / ADC0.00(VP1) / SEG24 19 P0.01 / PWM0.01 / ADC0.01(VN1) / SEG25 20 P0.02 / PWM0.02 / TS0.02 / SEG26 21 P0.03 / PWM0.03 / TS0.03 / COM0

22 P0.04 / PWM0.04 / TS0.04 / COM1 23 P0.05 / PWM0.05 / TS0.05 / COM2 24 P0.06 / PWM0.06 / TS0.06 / COM3 25 P0.07 / PWM0.07 / TS0.07 / SEG4 26 P0.08 / PWM0.08 / ADC0.08(VP2) / SEG27 27 P0.09 / PWM0.09 / ADC0.09(VN2) / SEG28 28 P0.10 / PWM0.10 / ADC0.10(VP3,S1)

29 P0.11 / PWM0.11 / ADC0.11(VN3,S2) 30 P0.12 / PWM0.12 / ADC0.12(VP4,S3) 31 P0.13 / PWM0.13 / ADC0.13(VN4,S4) 32 VSS 33 VSS

88

87

86

69

68

67

23

24

25

42

43

44

66

65

64

47

46

45

1

3

5

20

21

22

SEJONG200-ML88IP

[ 88-pin MLF : 10mm X 10mm ]


VDDIO (#13, #34, #58, #79)

VSS (#15,#16,#32,#33,#56,#57,#80,#81)





TRST (#7, with 10kΩ Pull-up R)



Pin No. Pin Name

34 VDDIO 35 P0.14 / PWM0.14 / ADC0.14(VP5) / SEG29 36 P0.15 / PWM0.15 / ADC0.15(VN5) / SEG30 37 P1.00 / PWM1.00 / TS1.00 / SEG5 38 P1.01 / PWM1.01 / TS1.01 / SEG6 39 P1.02 / PWM1.02 / TS1.02 / SEG7 40 P1.03 / PWM1.03 / TS1.03 / SEG8 41 P1.04 / PWM1.04 / TS1.04 / SEG9 42 P1.05 / PWM1.07 / TS1.05 / SEG10 43 P1.06 / PWM1.06 / TS1.06 / SEG11 44 P1.07 / PWM1.07 / TS1.07 / SEG12 45 P1.08 / PWM1.08 / TS1.08 / SEG13 46 P1.09 / PWM1.09 / TS1.09 / SEG14

47 P1.10 / PWM1.10 / ADC1.10(VP6) / SEG15 48 P1.11 / PWM1.11 / ADC1.11(VN6) / SEG16 49 P1.12 / PWM1.12 / ADC1.12(VP7) / SEG31 50 P1.13 / PWM1.13 / SPI_SSB_A / ADC1.13(VN7) / TS1.13 51 P1.14 / PWM1.14 / SPI_SCK_A / ADC1.14(VP8) / TS1.14 52 P1.15 / PWM1.15 / ADC1.15(VN8) / LVDD 53 P2.00 / ADC2.00(VP9) / VLCD3 54 P2.01 / ADC2.01(VN9) / VLCD2 55 P2.02 / ADC2.02(S5) / VLCD1 56 VSS 57 VSS 58 VDDIO 59 P2.03 / SPI_MOSI_A / ADC2.02(S6) / TS2.03 / 60 P2.04 / INT8 / TS2.04 / SEG17 61 P2.05 / INT9 / ADC2.05(VP10) / SEG18 62 P2.06 / INT10 / ADC2.06(VN10) / SEG19 63 P2.07 / INT11 / ADC2.07(VP11) / SEG20

Pin No. Pin Name

64 P2.08 / INT12 / ADC2.08(VN11) / SEG21 65 P2.09 / SPI_MISO_A / ADC2.09(VP12) /TS2.09 66 P2.10 / ADC2.10(VN12,S7) 67 P2.11 / ADC2.11(VP13,S8) 68 P2.12 / ADC2.12(VN13) / TS2.12 69 P2.13 / INT13 / ADC2.13(VP14) / SEG22 70 P2.14 / INT14 / ADC2.14(VN14) / SEG23 71 P2.15 / INT15 / ADC2.15(VP15) / SEG0 72 P4.00 / ADC4.00(VN15) / SEG1 73 P4.01 / ADC4.01(VP16) / SEG2 74 P4.02 / ADC4.02(VN16) / SEG3 75 P4.03 / I2S_CLK_A / I2C1_SCLK_A / ADC4.03(VP17) / TS4.03 76 P4.04 / I2S_DATA_A / I2C1_SDA_A / ADC4.04(VN17) / TS4.04 77 P4.05 / ADC4.05(VP18,S9) 78 P4.06 / ADC4.06(VN18,S10) 79 VDDIO 80 VSS 81 VSS 82 P4.13 / RTC_XTAL2 83 P4.14 / RTC_XTAL1 84 P4.07 / I2S_WS / RTCOUT / ADC4.07(VP19,S11) 85 P4.08 / I2S_CLK / RXD1_A / ADC4.08(VN19,S12) 86 P4.09 / I2S_DATA / TXD1_A / ADC4.09(VP20,S13) 87 P4.10 / REMOUT/ ADC4.10(VN20,S14) 88 P4.11 / I2S_DATA_IN / ADC4.10(VP21) / TS4.11


5. Pin Descriptions

Symbol Direction Description Share Pins VDDIO Input Digital I/O Power -

VDDINT Output Digital Power Input/Output (+1.8V) -

VSS Input Ground for Digital I/O Power (Bottom PAD of Device Package) -

VDDA Input Touch Sensor Power

VDDINTA Output Touch Sensor Power Input/Output (+1.8V)

VSSA Input Ground for Touch Sensor Power -

CEB Input Chip Enable (Active Low) -

RESETB Input External Reset (Active Low) • P3.04 : INT4 / RESETB / TRST

TDI Input JTAG Data Input • P3.00 : INT0 / RXD0 / SPI_SSB / TDI

TDO Output JTAG Data Output • P3.01 : INT1 / TXD0 / SPI_SCK / TDO

TCLK Input JTAG Clock Input • P3.02 : INT2 / I2C0_SCL / SPI_MISO / TCLK

TMS Input JTAG Mode Input • P3.03 : INT3 / I2C0_SDA / SPI_MOSI / TMS

TRST Input JTAG Reset Input • P3.04 : INT4 / RESETB / TRST

XTAL1 Input Input to the Inverting Oscillator Amplifier • P3.06 : CLO / I2C1_SDA / TXD1 / XTAL1

XTAL2 Output Output to the Inverting Oscillator Amplifier • P3.05 : INT5 / I2C1_SCL / RXD1 / XTAL2

T_MOD Input Test Mode Pin -


5. Pin Descriptions

Symbol Direction Description Share Pins

P0[15:0] Input/Output

An 16-bit open-Drain or push-pull I/O port. Note that the output is fully driven (push-pull) when P0 drives PWM0 output. Each port must be used only one among ADC, LCDC and Touch

• P0.00 PWM0.00 : PWM output 0.00 • P0.15 PWM0.15 : PWM output 0.15 • P0.00 ADC0.00 : A/D Converter Input 0.00 • P0.15 ADC0.15 : A/D Converter Input 0.15 • P0.02 TS0.02 : Self Touch channel 0.02 • P0.07 TS0.07 : Self Touch channel 0.07 • P0.00 SEG24 : LCDC SEG output • P0.03 COM0 : LCDC COM output • P0.15 SEG30 : LCDC SEG output

•P0.00 / PWM0.00 / ADC0.00(VP1) / / SEG24 •P0.01 / PWM0.01 / ADC0.01(VN1) / / SEG25 •P0.02 / PWM0.02 / / TS0.02 / SEG26 •P0.03 / PWM0.03 / / TS0.03 / COM0 •P0.04 / PWM0.04 / / TS0.04 / COM1 •P0.05 / PWM0.05 / / TS0.05 / COM2 •P0.06 / PWM0.06 / / TS0.06 / COM3 •P0.07 / PWM0.07 / / TS0.07 / SEG4 •P0.08 / PWM0.08 / ADC0.08(VP2) / / SEG27 •P0.09 / PWM0.09 / ADC0.09(VN2) / / SEG28 •P0.10 / PWM0.10 / ADC0.10(VP3,S1) / / •P0.11 / PWM0.11 / ADC0.11(VN3,S2) / / •P0.12 / PWM0.12 / ADC0.12(VP4,S3) / / •P0.13 / PWM0.13 / ADC0.13(VN4,S4) / / •P0.14 / PWM0.14 / ADC0.14(VP5) / /SEG29 •P0.15 / PWM0.15 / ADC0.15(VN5) / /SEG30


5. Pin Descriptions



An 16-bit open-Drain or push-pull I/O port. Note that the output is fully driven (push-pull) when P1 drives PWM1 output. Each port must be used only one among ADC, LCDC and Touch

• P1.00 PWM1.00 : PWM output 1.00 • P1.15 PWM1.15 : PWM output 1.15 • P1.13 SPI_SSB : SPI SSB second path • P1.14 SPI_SCK : SPI SCK second path • P1.10 ADC1.10 : A/D Converter Input 1.10 • P1.15 ADC1.15 : A/D Converter Input 1.15 • P1.00 TS1.00 : Self Touch channel 1.00 • P1.14 TS1.14 : Self Touch channel 1.14 • P1.00 SEG5 : LCDC SEG output • P1.15 LVDD : LCDC LVDD output

P1.00 / PWM1.00 / / TS1.00 / SEG5 P1.01 / PWM1.01 / / TS1.01 / SEG6 P1.02 / PWM1.02 / / TS1.02 / SEG7 P1.03 / PWM1.03 / / TS1.03 / SEG8 P1.04 / PWM1.04 / / TS1.04 / SEG9 P1.05 / PWM1.07 / / TS1.05 / SEG10 P1.06 / PWM1.06 / / TS1.06 / SEG11 P1.07 / PWM1.07 / / TS1.07 / SEG12 P1.08 / PWM1.08 / / TS1.08 / SEG13 P1.09 / PWM1.09 / / TS1.09 / SEG14 P1.10 / PWM1.10 / ADC1.10(VP6) / / SEG15 P1.11 / PWM1.11 / ADC1.11(VN6) / / SEG16 P1.12 / PWM1.12 / ADC1.12(VP7) / / SEG31 P1.13 / PWM1.13 / ADC1.13(VN7) / TS1.13 / / SPI_SSB_A P1.14 / PWM1.14 / ADC1.14(VP8) / TS1.14 / / SPI_SCK_A P1.15 / PWM1.15 / ADC1.15(VN8) / / LVDD


5. Pin Descriptions



An 16-bit open-Drain or push-pull I/O port. Each port must be used only one among ADC, LCDC and Touch • P2.03 SPI_MOSI_A: SPI MOSI second path • P2.04 INT8 : Ext. interrupt 8 • P2.09 SPI_MISO_A: SPI MISO second path • P2.15 INT15 : Ext. interrupt 15 • P2.00 ADC2.00 : A/D Converter Input 2.00 • P2.15 ADC2.15 : A/D Converter Input 2.15 • P2.03 TS2.03 : Self Touch channel 2.03 • P2.12 TS2.12 : Self Touch channel 2.12 • P2.00 VLCD3 : VLCD3 output • P2.15 SEG : SEG0 output

P2.00 / /ADC2.00(VP9) / / VLCD3 P2.01 / /ADC2.01(VN9) / / VLCD2 P2.02 / /ADC2.02(S5) / / VLCD1 P2.03 / SPI_MOSI_A / ADC2.02(S6) /TS2.03 / P2.04 / INT8 / /TS2.04 / SEG17 P2.05 / INT9 / ADC2.05(VP10) / / SEG18 P2.06 / INT10 / ADC2.06(VN10) / / SEG19 P2.07 / INT11 / ADC2.07(VP11) / / SEG20 P2.08 / INT12 / ADC2.08(VN11) / / SEG21 P2.09 / SPI_MISO_A / ADC2.09(VP12) /TS2.09 / P2.10 / / ADC2.10(VN12,S7) / / P2.11 / / ADC2.11(VP13,S8) / / P2.12 / / ADC2.12(VN13,S8) / TS2.12 / P2.13 / INT13 / ADC2.13(VP14) / / SEG22 P2.14 / INT14 / ADC2.14(VN14) / / SEG23 P2.15 / INT15 / ADC2.15(VP15) / / SEG0


5. Pin Descriptions



An 15-bit open-Drain or push-pull I/O port. Each port must be used only one among ADC, LCDC and Touch • P4.03 I2S_CLK_A : I2S CLK second path I2C1_SCL_A: I2C1 SCL second path • P4.04 I2S_DATA_A : I2S DATA second path I2C1_SDA_A : I2C1 SDA second path • P4.07 I2S_WS : I2S WS first path RTCOUT : RTC clock path • P4.08 I2S_CLK : I2S CLK first path RXD1_A : UART1 RXD second path • P4.09 I2S_DATA : I2S DATA out first path TXD1_A : UART1 TXD second path • P4.10 REMOUT : UR output • P4.11 I2S_DATA_IN: I2S DATA IN • P4.13 RTC_XTAL2 : RTC_XTAL output • P4.14 RTC_XTAL1 : RTC_XTAL input • P4.00 ADC4.00 : A/D Converter Input 4.00 • P4.15 ADC4.15 : A/D Converter Input 4.15 • P2.03 TS2.03 : Self Touch channel 2.03 • P2.12 TS2.12 : Self Touch channel 2.12 • P4.00 SEG1 : SEG1 output • P4.02 SEG3 : SEG3 output

P4.00 / / ADC4.00(VN15) / / SEG1 P4.01 / / ADC4.01(VP16) / / SEG2 P4.02 / / ADC4.02(VP16) / / SEG3 P4.03 / I2S_CLK_A / ADC4.03(VP17) / TS4.03 / /I2C1_SCL_A P4.04 / I2S_DATA_A / ADC4.04(VN17) / TS4.04 / /I2C1_SDA_A P4.05 / / ADC4.05(VP18,S9) / / P4.06 / / ADC4.06(VN18,S10) / / P4.13 / RTC_XTAL2 / / / P4.14 / RTC_XTAL1 / / / P4.07 / I2S_WS / / ADC4.07(VP19,S11) / / /RTCOUT P4.08 / I2S_CLK / ADC4.08(VN19,S12) / / /RXD1_A P4.09 / I2S_DATA / ADC4.09(VP20,S13) / / /TXD1_A P4.10 / REMOUT / ADC4.10(VN20,S14) / / P4.11 / I2S_DATA_IN / ADC4.10(VP21) / TS4.11 / P4.12 / / ADC4.10(VN21) / TS4.12 /


6.1. Memory Organization

Stack

TCF and/or .data or .bss

(SRAM)

Reserved

Application Codes

Boot Initialization

Boot-up

Interrupt Vectors

IAP Hard-Codes

Peripherals

Code MMR

SRAM

0x0000

0x00FF 0x0100

0x06FF 0x0700

0x07FF 0x0800

0x47FF 0x4800

0xDFFF 0xE000

0xE3FF

Embedded FLASH Memory

Reserved 0xFFFF

0xE200


6.1. Memory Descriptions (1 of 2)

CORE MMR the internal registers of the core This area is used solely by the core. The user application may refer to the value of this area. However, it is strictly prohibited for the user application to modify this area.

Peripherals Each peripheral is allocated its own memory space in this area. Refer to the provided header file to identify the base address of each peripheral interface. In the following sections, only the offset addresses from the base address are specified in the section of each peripheral.

IAP hard-codes The program codes for IAP (In-Application Programming) reside in this area. If the application calls the function for writing to the embedded flash memory directly which are IAP operations, the core

executes the functions residing in this area.

Interrupt vectors The interrupt vector table for the core resides in this area. Programmers may set the function pointer for the interrupt vector in this area. By default, there are several pre-defined function names for interrupt service routines

Boot-up and Boot Initialization For the programmers, we provide boot-up and boot initialization routines. During boot-up, the processor state registers and stack are initialized. The boot initialization routine moves .data and .bss sections stored in the embedded flash memory into the SRAM area.


6.1. Memory Descriptions (2 of 2)

Application codes The area for application code include several types of data. First, the application codes include the code and read-only data for the core. Second, the application codes include the copy of the Time-Critical Function (TCF)'s code. The code for TCF resides in the application codes area during the programming of embedded flash memory and then copied

to the SRAM area just after entering the main function.

TCF or .data or .bss The SRAM area includes Time-Critical Function (TCF), .data, or .bss sections which are inherently readable and writable. The TCF is the time-critical function area where the function which has time-critical operations would be located. By locating TCF in SRAM area, programmers may enhance the function's execution speed. The .data section is the global data with initialization value. The compiler would locate .data section initially in the embedded flash memory area and then the boot initialization routine

would copy them to SRAM area. The .bss section is the global data which are not initialized. No initialization operation is needed for .bss.

Stack The stack are should be assigned in any compiled application code. In the current implementation, there is no exception handling for stack overflow or underflow. Therefore, programmers should be careful to set sufficient amount of stack area so that no stack overflow or underflow

occurs.

SeJong200 Family

Op. Mode ACTIVE By default, Op. mode becomes ACTIVE.

[20]

6.2. Reset Sequence (1 of 2)

POR Sequence The PoR macro generates PoR signal. PoR subsequently makes PoR_l signal which is several-clock-cycle wide. PoR_l triggers i_reset which persists for at least 32ms. During i_reset

• VDD, the power should be stabilized. • External crystal clock oscillators are stabilized through XTAL stabilizers.

VDD

PoR

PoR_I

i_reset

32ms


6.2. Reset Sequence (2 of 2)

Global Reset Sequence Power on reset by POR macro External reset pin : Setting ‘H’ and ‘L’ on the external reset pin does internal global reset of the

chip Reset from WDT (Watch-Dog Timer) : If Register of WDT is programmed accordingly, WDT

triggers the internal global reset. JTAG reset command : The reset command triggered by JTAG triggers the internal global reset.

PoR_I

i_reset

32ms

Op. Mode ACTIVE

PoR from PoR Macro

External Reset Pin

Reset from WDT

JTAG Reset Command

SeJong200 Family

6.3. Operating Modes

Active mode The processor core and all the peripherals configured accordingly by the firmware are active. The firmware of the core decides the peripherals to be active. The GPIOs are configured accordingly by the firmware.

Idle mode The clock of CPU is disabled. The clocks of peripherals are active. The clock of WDT is decided by the firmware. Wake-up source : an interrupt from any peripheral.

Weak Sleep mode The clock of CPU is disabled. The clocks of peripherals are disabled. The clock of WDT is active. Wake-up source : I2C / WDT / External 8-bit interrupts

Sleep mode The clock of CPU is disabled. The clocks of peripherals are disabled. The clock of WDT is disabled. Wake-up source : I2C / External 8-bit interrupts

[22]

SeJong200 Family

6.4. Clock Network : Block Diagram (1 of 2)

[23]

CPU Clock

Peripheral Clock

IDLE_ON

Internal 96MHz

XTAL

DIV

ISCLK_OFF

PD_ON

TSCLK_OFF

XTAL_EN XTUP

FOSC

TS Clock

IRDIV

TSDIV

0

1

TSCLK_SW

ISCLK_SW

DIV

ADCDIV

ADCLK_EN

TSCLK_OFF

Clock Stable Counter

0

1

ADCLK_EN

PD_ON

DIV

FDIV_TS

FDIV_SYS

FXTAL

FTS

ADC Clock

0

1

ADCLK_SW

FDIV_ADC

FADC

FSYS

PCK_DIS[0]

peri0

peri1

periN

PCK_DIS[1]

PCK_DIS[N]

UART Clock

0

1

UCLK_SW

FDIV_SYS

FUART

SeJong200 Family

6.4. Clock Network : Block Diagram (2 of 2)

[24]

Internal 32KHz

IR32K_ON

STOP Timer Clock

RTC_SLEEP_OFF

0

1

F32KHz

RTC_XTAL

RTC_XTAL_EN RTC_XTUP

0

1

ST_CLK_SW

Clock Stable Counter

RTC_XTAL setup time : ~ 200 us

0

1

RTC_CLK_SW

0

RTC Clock

RTC_SLEEP_OFF

0

1

0

SeJong200 Family

6.4. Clock Network : Registers (1 of 6)

- - - - - - - - - - - - - STPD_ON PD_ON IDLE_ON

R/W(0) R/W(0) R/W(0)

PCON (0100h) : Power Control Register

STPD_ON : Stop Timer Clock Enable/Disable ([0] : Disable [1] : Enable) PD_ON : Power down mode On ([0] : Not power down mode [1] : Power down mode) IDLE_ON : Idle mode On ([0] : Not idle mode [1] : Idle mode)

IRCLK_DIV (0101h) : Internal Ring Clock Divisor Register

- - - - - - - - - - - - - IRDIV2 IRDIV1 IRDIV0

R/W(0) R/W(0) R/W(0)

IRDIV[2:0] [000] : FOSC / 128 [001] : FOSC / 64 [010] : FOSC / 32 [011] : FOSC / 16 [100] : FOSC / 8 [101] : FOSC / 4 [110] : FOSC / 2 (only TCF mode) [111] : Reserved

TSCLK_DIV (0102h) : Touch Sensor Clock Divisor Register

- - - - - - - - - - - - - TSDIV2 TSDIV1 TSDIV0

R/W(0) R/W(0) R/W(0)

TSDIV[2:0] [000] : FOSC / 128 [001] : FOSC / 64 [010] : FOSC / 32 [011] : FOSC / 16 [100] : FOSC / 8 [101] : FOSC / 4 [110] : FOSC / 2 [111] : FOSC

SOFT_CNT (0103h) : SOFT_EN Period Counter

- - - - - SOFT_CNT10

SOFT_CNT9

SOFT_CNT8

SOFT_CNT7

SOFT_CNT6

SOFT_CNT5

SOFT_CNT4

SOFT_CNT3

SOFT_CNT2

SOFT_CNT1

SOFT_CNT0

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1)

R/W(1) SOFT_CNT : SOFT CNT period for Main LDO valid after sleep min 32 us

[25]

SeJong200 Family


- - - - - - - - - - - - - - ISCLK_OFF TSCLK_OFF

R/W(0) R/W(0)

CLK_OFF (0104h) : Internal System Clock & Touch Sensor Clock OFF Register

ISCLK_OFF : Internal System Clock on/off ([0] : clock on [1] : clock off) TSCLK_OFF : Touch Sensor Clock on/off ([0] : clock on [1] : clock off)

ISCLK_SW (0106h) : Internal System Clock Switch Register

- - - - - - - - - - - - - - - ISCLK_SW

R/W(0)

ISCLK_SW : Internal system clock switching ([0] : internal ring [1] : external crystal)

XTAL_ST (0107h) : External Crystal Status Register

- - - - - - - - - - - - - - - XTUP

R(0)

XTUP : External crystal stabilization flag ([0] : not stabilized [1] : stabilized)

XTAL_EN (0108h) : External Crystal Enable Register

- - - - - - - - - - - - - STAB_EN - XTAL_EN

R/W(1) R/W(0)

STAB_EN : External Stabilizer enable flag ([0] : disable [1] : enable) XTAL_EN : External crystal enable flag ([0] : disable [1] : enable)

[26]

SeJong200 Family


IRING_TRIM (0105h) : Internal Ring Clock Trimming Register

- - - - - - - - IRTRIM7 IRTRIM6 IRTRIM5 IRTRIM4 IRTRIM3 IRTRIM2 IRTRIM1 IRTRIM0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

[27]

OSC_ON S[7:0] OSC_OUT

IN IN OUT

0 XXh 0

1 00h

(maximum) 140MHz CLOCK (matched duty)

1 78h

(default) 96MHz CLOCK

(matched duty)

1 FFh

(minimum) 26MHz CLOCK

(matched duty)

SeJong200 Family


- - - - - - - - - - - - - - - IR32K_ON

R/W(0)

IR32K_ON (0109h) : Internal 32K Ring Clock Control Register

IR32K_ON : Internal 32K Ring Clock on/off ([0] : clock off [1] : clock on)

IRCLK_OE (010Bh) : Internal Ring Clock Output Enable Register

- - - - - - - - - - - - - - IR96M_OE IR32K_OE

R/W(0) R/W(0) IR96M_OE : Internal 96M Ring Clock PAD output enable ([0] : disable [1] : enable @ P6.0) IR32K_OE : Internal 32K Ring Clock PAD output enable ([0] : disable [1] : enable @ P6.0)

- - - - - - - - - - - - - - - TSCLK_SW

R/W(0)

TSCLK_SW (010Ah) : Touch Sensor Clock Switch Register

TSCLK_SW : Touch Sensor clock switching ([0] : internal ring [1] : external crystal)

- - - - - - - - - - - - - - UCLK_SW ADCLK_SW

R/W(0) R/W(0)

PERICLK_SW (010Fh) : UART & ADC Clock Switch Register

UCLK_WN : UART clock switching ([0] : internal ring [1] : extern crystal) ADCLK_SW : ADC clock switching ([0] : internal ring [1] : external crystal)

[28]

SeJong200 Family


PCK_DIS15 PCK_DIS14 PCK_DIS13 PCK_DIS12 PCK_DIS11 PCK_DIS10 PCK_DIS9 PCK_DIS8 PCK_DIS7 PCK_DIS6 PCK_DIS5 PCK_DIS4 PCK_DIS3 PCK_DIS2 PCK_DIS1 PCK_DIS0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

PCLK_DIS1 (010Ch) : Peripheral Clock Control 1 Register

PCK_DIS0 : Interrupt Controller Clock on/off ([0] : clock on [1] : clock off) PCK_DIS1 : I2C 0 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS2 : I2C 1 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS3 : SPI Clock on/off ([0] : clock on [1] : clock off) PCK_DIS4 : Stop Timer Clock on/off ([0] : clock on [1] : clock off) PCK_DIS5 : UART 0 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS6 : UART 1 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS7 : Touch Sensor Clock on/off ([0] : clock on [1] : clock off) PCK_DIS8 : WDT Clock on/off ([0] : clock on [1] : clock off) PCK_DIS9 : Timer 0 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS10 : Timer 1 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS11 : Timer 2 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS12 : Timer 3 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS13 : Timer 4 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS14 : LCDC Clock on/off ([0] : clock on [1] : clock off) PCK_DIS15 : PWM 0 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS16 : PWM 1 Clock on/off ([0] : clock on [1] : clock off) PCK_DIS17 : Reserved PCK_DIS18 : ADC Clock on/off ([0] : clock on [1] : clock off) PCK_DIS19 : GPIO Clock on/off ([0] : clock on [1] : clock off) PCK_DIS20 : I2S Clock on/off ([0] : clock on [1] : clock off) PCK_DIS21 : RTC Clock on/off ([0] : clock on [1] : clock off) PCK_DIS22 : UR Clock on/off ([0] : clock on [1] : clock off)

- - - - - - - - - PCK_DIS22 PCK_DIS21 PCK_DIS20 PCK_DIS19 PCK_DIS18 Reserved PCK_DIS16

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

PCLK_DIS2 (010Dh) : Peripheral Clock Control 2 Register

[29]

SeJong200 Family


RTC_CLK_SW (0112h) : RTC Clock Switch Register

- - - - - - - - - - - - - - RTC_CLK_SW1

ST_CLK_SW0

R/W(0) R/W(0) ST_CLK_SW0 : STOP Timer clock switching ([0] : internal 32K ring [1] : external RTC crystal) RTC_CLK_SW1 : RTC clock switching ([0] : internal 32K ring [1] : external RTC crystal)

RTC_XTAL_ST (0110h) : External RTC Crystal Status Register

- - - - - - - - - - - - - - - RXTUP

R(0)

RXTUP : External crystal stabilization flag ([0] : not stabilized [1] : stabilized)

RTC_XTAL_EN (0111h) : External RTC Crystal Enable Register

- - - - - - - - - - - - - RSTAB_EN - RXTAL_EN

R/W(1) R/W(0)

RXTAL_EN : External RTC crystal enable flag ([0] : disable [1] : enable) RSTAB_EN : External RTC Stabilizer enable flag ([0] : disable [1] : enable)

[30]


6.4. Clock Network : Guideline for Configuration

Oscillator Module

OSC

Oscillator Module

Crystal Oscillator Internal Ring Oscillator

SJ200 XTAL2

XTAL1

SJ200 XTAL2

XTAL1

SJ200 XTAL2

XTAL1 RING OSC

RC Oscillator

1 MΩ

SeJong200 Family

Open-drain or push-pull output, pull-up control (Default : Pull-up OFF).

The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”. The corresponding IOENB bit is “1”. The only one among ADCSELx for ADC, TSCHEN bit for Touch Sensor and LCD_IO_ENx bit for LCD must be selected exclusively to avoid collision each other

The alternative functions P0.00 / PWM0.00 / ADC0.00(VP1) / / SEG24 P0.01 / PWM0.01 / ADC0.01(VN1) / / SEG25 P0.02 / PWM0.02 / / TS0.02 / SEG26 P0.03 / PWM0.03 / / TS0.03 / COM0 P0.04 / PWM0.04 / / TS0.04 / COM1 P0.05 / PWM0.05 / / TS0.05 / COM2 P0.06 / PWM0.06 / / TS0.06 / COM3 P0.07 / PWM0.07 / / TS0.07 / SEG4 P0.08 / PWM0.08 / ADC0.08(VP2) / / SEG27 P0.09 / PWM0.09 / ADC0.09(VN2) / / SEG28 P0.10 / PWM0.10 / ADC0.10(VP3,S1) / / P0.11 / PWM0.11 / ADC0.11(VN3,S2) / / P0.12 / PWM0.12 / ADC0.12(VP4,S3) / / P0.13 / PWM0.13 / ADC0.13(VN4,S4) / / P0.14 / PWM0.14 / ADC0.14(VP5) / /SEG29 P0.15 / PWM0.15 / ADC0.15(VN5) / /SEG30

[32]

6.5. I/O Ports : PORT0[15:0]

P0.01

P0.01 Register

Q

QB

CPU BUS

P0PENB.01

Alternative Output

P0TYPE.01

P0DIR.01

1 0

Digital Input

P0HD.01

Strong Normal

ADC Input

IOENB0.01

Touch Input

ADCSEL = 0001h

TSCHEN0.01

P0HD.01

MUX

COM_SEG[1:0]

LCD_IO_EN

VLCD3

VLCD2

VLCD1

VSS


6.5. I/O Ports : PORT0[15:0]

P0DR.15 P0DR.14 P0DR.13 P0DR.12 P0DR.11 P0DR.10 P0DR.9 P0DR.8 P0DR.7 P0DR.6 P0DR.5 P0DR.4 P0DR.3 P0DR.2 P0DR.1 P0DR.0


P0DR (0300h) : Port 0 Data Register (Write : P0DR, Read : P0 port)

P0PENB.15 P0PENB.14 P0PENB.13 P0PENB.12 P0PENB.11 P0PENB.10 P0PENB.9 P0PENB.8 P0PENB.7 P0PENB.6 P0PENB.5 P0PENB.4 P0PENB.3 P0PENB.2 P0PENB.1 P0PENB.0


P0PENB (0307h) : Port 0 Pull-up Control Register

0 = Pull-up resistor ON / 1 = OFF (Default)

P0DIR.15 P0DIR.14 P0DIR.13 P0DIR.12 P0DIR.11 P0DIR.10 P0DIR.9 P0DIR.8 P0DIR.7 P0DIR.6 P0DIR.5 P0DIR.4 P0DIR.3 P0DIR.2 P0DIR.1 P0DIR.0


P0DIR (0308h) : Port 0 Direction Control Register

0 = Output / 1 = Input (Default)

P0TYPE.15 P0TYPE.14 P0TYPE.13 P0TYPE.12 P0TYPE.11 P0TYPE.10 P0TYPE.9 P0TYPE.8 P0TYPE.7 P0TYPE.6 P0TYPE.5 P0TYPE.4 P0TYPE.3 P0TYPE.2 P0TYPE.1 P0TYPE.0


P0TYPE (0309h) : Port 0 Type Control Register

0 = Push-pull Output / 1 = Open-drain Output (Default)

P0HDEN.15 P0HDEN.14 P0HDEN.13 P0HDEN.12 P0HDEN.11 P0HDEN.10 P0HDEN.9 P0HDEN.8 P0HDEN.7 P0HDEN.6 P0HDEN.5 P0HDEN.4 P0HDEN.3 P0HDEN.2 P0HDEN.1 P0HDEN.0


P0HDEN (030Ah) : Port 0 High Driving Control Register

0 = High Current Driving OFF (Default) / 1 = ON

IOENB0 & ADCSEL &ADCSEL2 : refer to ADC section

TSCHEN : refer to Touch section

SEG_IO_EN & COM_IO_EN : refer to LCDC section

SeJong200 Family

Open-drain or push-pull output, pull-up control.


The alternative functions P1.00 / PWM1.00 / / TS1.00 / SEG5 P1.01 / PWM1.01 / / TS1.01 / SEG6 P1.02 / PWM1.02 / / TS1.02 / SEG7 P1.03 / PWM1.03 / / TS1.03 / SEG8 P1.04 / PWM1.04 / / TS1.04 / SEG9 P1.05 / PWM1.07 / / TS1.05 / SEG10 P1.06 / PWM1.06 / / TS1.06 / SEG11 P1.07 / PWM1.07 / / TS1.07 / SEG12 P1.08 / PWM1.08 / / TS1.08 / SEG13 P1.09 / PWM1.09 / / TS1.09 / SEG14 P1.10 / PWM1.10 / ADC1.10(VP6) / / SEG15 P1.11 / PWM1.11 / ADC1.11(VN6) / / SEG16 P1.12 / PWM1.12 / ADC1.12(VP7) / / SEG31 P1.13 / PWM1.13 / ADC1.13(VN7) / TS1.13 // SPI_SSB_A P1.14 / PWM1.14 / ADC1.14(VP8) / TS1.14 // SPI_SCK_A P1.15 / PWM1.15 / ADC1.15(VN8) / / LVDD

[34]

6.5. I/O Ports : PORT1[15:0]

P1.01

P1.01 Register

Q

QB

CPU BUS

P1PENB.01

Alternative Output

P1TYPE.01

P1DIR.01

1 0

Digital Input

P1HD.01

Strong Normal

ADC Input

IOENB1.01

Touch Input

ADCSEL = 0011h

TSCHEN1.01

P1HD.01

MUX

COM_SEG[1:0]

LCD_IO_EN

VLCD3

VLCD2

VLCD1

VSS


6.5. I/O Ports : PORT1[15:0]






P1PENB (030Bh) : Port 1 Pull-up Control Register




P1DIR (030Ch) : Port 1 Direction Control Register




P1TYPE (030Dh) : Port 1 Type Control Register




P1HDEN (030Eh) : Port 1 High Driving Control Register


IOENB1 & ADCSEL & ADCSEL2: refer to ADC section

TSCHEN : refer to Touch section SEG_IO_EN & COM_IO_EN : refer to LCDC section

SeJong200 Family



The alternative functions P2.00 / /ADC2.00(VP9) / / VLCD3 P2.01 / /ADC2.01(VN9) / / VLCD2 P2.02 / /ADC2.02(S5) / / VLCD1 P2.03 / SPI_MOSI_A / ADC2.02(S6) /TS2.03 / P2.04 / INT8 / /TS2.04 / SEG17 P2.05 / INT9 / ADC2.05(VP10) / / SEG18 P2.06 / INT10 / ADC2.06(VN10) / / SEG19 P2.07 / INT11 / ADC2.07(VP11) / / SEG20 P2.08 / INT12 / ADC2.08(VN11) / / SEG21 P2.09 / SPI_MISO_A / ADC2.09(VP12) / TS2.09 / P2.10 / / ADC2.10(VN12,S7) / / P2.11 / / ADC2.11(VP13,S8) / / P2.12 / / ADC2.12(VN13,S8) / TS2.12 / P2.13 / INT13 / ADC2.13(VP14) / / SEG22 P2.14 / INT14 / ADC2.14(VN14) / / SEG23 P2.15 / INT15 / ADC2.15(VP15) / / SEG0

[36]

6.5. I/O Ports : PORT2[15:0]

P2.01

P2.01 Register

Q

QB

CPU BUS

P2PENB.01

Alternative Output

P2TYPE.01

P2DIR.01

1 0

Digital Input

P2HD.01

Strong Normal

ADC Input

IOENB2.01

Touch Input

ADCSEL = 0021h

TSCHEN2.01

P2HD.01

MUX

COM_SEG[1:0]

LCD_IO_EN

VLCD3

VLCD2

VLCD1

VSS


6.5. I/O Ports : PORT2[15:0]






P2PENB (030Fh) : Port 2 Pull-up Control Register












P2HDEN (0312h) : Port 2 High Driving Control Register


IOENB2 & ADCSEL &ADCSEL2 : refer to ADC section


SeJong200 Family


The alternative functions are available under the conditions The corresponding Data Register bit is “1”. The corresponding DIR bit is “1”. The corresponding PENB bit is “1”.

The alternative functions P3.00 = INT0 / RXD0 / SPI_SSB / TDI P3.01 = INT1 / TXD0 / SPI_SCK / TDO P3.02 = INT2 / I2C0_SCL / SPI_MISO / TCLK P3.03 = INT3 / I2C0_SDA / SPI_MOSI / TMS P3.04 = INT4 / RESETB / TRST P3.05 = INT5 / I2C1_SCL / RXD1 / XTAL2 P3.06 = CLO / I2C1_SDA / TXD1 / XTAL1

[38]

6.5. I/O Ports : PORT3[6:0]

`

P3.1

P3.1 DR

Q

QB

CPU BUS

P3PENB.1

Alternative Output

P3TYP.01

P3DIR.01

1 0

Digital Input

P3HD.1

high low

P3HD.01


6.5. I/O Ports : PORT3[6:0]

- - - - - - - - - P3DR.6 P3DR.5 P3DR.4 P3DR.3 P3DR.2 P3DR.1 P3DR.0

R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)

P3DR (0303h) : Port 3Data Register (Write : P3DR, Read : P3 port)

- - - - - - - - - P3PENB.6 P3PENB.5 P3PENB.4 P3PENB.3 P3PENB.2 P3PENB.1 P3PENB.0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

P3PENB (0313h) : Port 3Pull-up Control Register


- - - - - - - - - P3DIR.6 P3DIR.5 P3DIR.4 P3DIR.3 P3DIR.2 P3DIR.1 P3DIR.0

R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)

P3DIR (0314h) : Port 3Direction Control Register


- - - - - - - - - P3TYPE.6 P3TYPE.5 P3TYPE.4 P3TYPE.3 P3TYPE.2 P3TYPE.1 P3TYPE.0

R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)

P3TYPE (0315h) : Port 3Type Control Register


- - - - - - - - - - - P3HDEN.4 P3HDEN.3 P3HDEN.2 P3HDEN.1 P3HDEN.0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

P3HDEN (0316h) : Port 3High Driving Control Register


- - - - - - - - - - - - - RTC_XTAL_IOEN_B

XTAL_IOENB RST_IOENB

R/W(1) R/W(1) R/W(0)

ALTIOENB (0323h) : Alternative IO Control Register

RTC_ XTAL_IOENB : 1 = enable P4.13~14 IO function, 0 = disable P4.13~14 IO function (enable RTC_XTAL function) XTAL_IOENB : 1 = enable P3.7~6 IO function, 0 = disable P3.7~6 IO function (enable XTAL function) RST_IOENB : 1 = enable P3.3 IO function, 0 = disable P3.3 IO function (enable RESETB function)

SeJong200 Family



The alternative functions P4.00 / / ADC4.00(VN15) / / SEG1 P4.01 / / ADC4.01(VP16) / / SEG2 P4.02 / / ADC4.02(VP16) / / SEG3 P4.03 / I2S_CLK_A/ ADC4.03(VP17)/ TS4.03 / I2C1_SCLK_A P4.04 / I2S_DATA_A / ADC4.04(VN17)/TS4.04/I2C1_SDA_A P4.05 / / ADC4.05(VP18,S9) / P4.06 / / ADC4.06(VN18,S10) / P4.07 / I2S_WS / / ADC4.07(VP19,S11)/RTCOUT P4.08 / I2S_CLK / ADC4.08(VN19,S12)/RXD1_A P4.09 / I2S_DATA / ADC4.09(VP20,S13)/TXD1_A P4.10 / REMOUT / ADC4.10(VN20,S14)/ P4.11 / I2S_DATA_IN/ ADC4.10(VP21) / TS4.11 / P4.12 / / ADC4.10(VN21) / TS4.12 / P4.13 / RTC_XTAL2 / P4.14 / RTC_XTAL1 /

[40]

6.5. I/O Ports : PORT4[14:0]

P4.01

P4.01 Register

Q

QB

CPU BUS

P4PENB.01

Alternative Output

P4TYPE.01

P4DIR.01

1 0

Digital Input

P4HD.01

Strong Normal

ADC Input

IOENB4.01

Touch Input

ADCSEL = 0041h

TSCHEN4.01

P4HD.01

MUX

COM_SEG[1:0]

LCD_IO_EN

VLCD3

VLCD2

VLCD1

VSS


6.5. I/O Ports : PORT4[14:0]

- P4DR.14 P4DR.13 P4DR.12 P4DR.11 P4DR.10 P4DR.9 P4DR.8 P4DR.7 P4DR.6 P4DR.5 P4DR.4 P4DR.3 P4DR.2 P4DR.1 P4DR.0

R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)


- P4PENB.14 P4PENB.13 P4PENB.12 P4PENB.11 P4PENB.10 P4PENB.9 P4PENB.8 P4PENB.7 P4PENB.6 P4PENB.5 P4PENB.4 P4PENB.3 P4PENB.2 P4PENB.1 P4PENB.0


P4PENB (0317Fh) : Port 4 Pull-up Control Register


- P4DIR.14 P4DIR.13 P4DIR.12 P4DIR.11 P4DIR.10 P4DIR.9 P4DIR.8 P4DIR.7 P4DIR.6 P4DIR.5 P4DIR.4 P4DIR.3 P4DIR.2 P4DIR.1 P4DIR.0




- P4TYPE.14 P4TYPE.13 P4TYPE.12 P4TYPE.11 P4TYPE.10 P4TYPE.9 P4TYPE.8 P4TYPE.7 P4TYPE.6 P4TYPE.5 P4TYPE.4 P4TYPE.3 P4TYPE.2 P4TYPE.1 P4TYPE.0




P4HDEN.12 P4HDEN.11 P4HDEN.10 P4HDEN.9 P4HDEN.8 P4HDEN.7 P4HDEN.6 P4HDEN.5 P4HDEN.4 P4HDEN.3 P4HDEN.2 P4HDEN.1 P4HDEN.0


P4HDEN (031Ah) : Port 4 High Driving Control Register


IOENB & ADCSEL & ADCSEL2 : refer to ADC section



6.6. The ESD Structure of Pads

Two ESD diodes and one ESD resister are contained in all pads except VDD.

One ESD diode are contained in VDD.

[VDD]

• Two ESD Diodes (VDD side, VSS side) • One ESD Resister

• One ESD Diode (GND side) • One ESD Resister

[All pads except VDD]


6.7. ST (Stop Timer)

Timer to wake up from stop mode

Use the internal 32 KHz oscillator or External crystal for saving power consumption

ST_CON (01C0h) : Stop Timer Control Register

ST_CLR : initialize Stop Timer Count , H/W clear it automatically (0 : not initialize , 1 : initialize) ST_OVF : Overflow event signal which internal stop timer match with ST_RT[15:0] value , H/W set and clear it (0 : not overflow, 1: overflow) ST_IF : Stop Timer Interrupt flag, S/W clear it , The interrupt is occurred when internal stop counter match with ST_RT[15:0] (0 : interrupt inactive, 1 : interrupt occurred) ST_EN : Stop Timer enable (0 : disable , 1 : enable)

- - - - - - - - - - - - ST_CLR ST_OVF ST_IF ST_EN

R/W(0) R(0) R/W(0) R/W(0)

ST_RTH (01C2h) : Stop Timer Timeout MSB Value Register

ST_RT[15:8] : Stop Timer MSB value

- - - - - - - - ST_RT15 ST_RT14 ST_RT13 ST_RT12 ST_RT11 ST_RT10 ST_RT9 ST_RT8


ST_RTL(01C1h) : Stop Timer Timeout LSB Value Register

ST_RT[7:0] : Stop Timer LSB value

- - - - - - - - ST_RT7 ST_RT6 ST_RT5 ST_RT4 ST_RT3 ST_RT2 ST_RT1 ST_RT0



6.8. WDT (Watchdog Timer)

Detects software upset due to external noise or other causes

Allows an automatic recovery using WDT interrupt or reset

WDMOD[2] WDMOD[1] WDMOD[0] Interrupt / Reset Time-out

0 0 0 233 clocks

0 0 1 235 clocks

0 1 0 237 clocks

0 1 1 239 clocks

1 0 0 241 clocks

1 0 1 243 clocks

1 1 0 245 clocks

1 1 1 247 clocks

WDTCON (0240h) : WDT Control Register

WDMOD[2:0] : WDT time-out period mode ResWDT : Restart WDT RunWDT : Run WDT EnWDT : Enable WDT WDIF : WDT interrupt flag

- - - - - - - - - WDIF EnWDT RunWDT ResWDT WDMOD2 WDMOD1 WDMOD0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WDTCNTL (0241h) : WDT Counter Low Register

WDTCNT15 WDTCNT14 WDTCNT13 WDTCNT12 WDTCNT11 WDTCNT10 WDTCNT9 WDTCNT8 WDTCNT7 WDTCNT6 WDTCNT5 WDTCNT4 WDTCNT3 WDTCNT2 WDTCNT1 WDTCNT0


WDTCNTH (0242h) : WDT Counter High Register

WDTCNT31 WDTCNT30 WDTCNT29 WDTCNT28 WDTCNT27 WDTCNT26 WDTCNT25 WDTCNT24 WDTCNT23 WDTCNT22 WDTCNT21 WDTCNT20 WDTCNT19 WDTCNT18 WDTCNT17 WDTCNT16



6.8. WDT (Watchdog Timer)

Block Diagram

32-bit Counter

RunWDT

EnWDT WDT Reset

WDIF WDTCNTL[15:0] WDTCNTH[15:0] OVF

007

006

005

004

003

002

001

000

1

1/8192

1/2048

1/512

1/256

1/64

1/32

1/8

1/2

peri_clk

WDTCNT[31:0] ResWDT

WDT interrupt ResWDT

Clear

reload

WDMOD[2:0]


6.9. Timer/Counter : PTC 0/1/2/3/4

Up counting Timer/Counter

Three 32-bit Timer/Counter

Support Auto-reset, Single and Capture mode

1. 32-bit timer auto-reset mode [CNT_ENx=0,PTC_MDx=0,CAP_ENx=0]

32-bit Timer with auto-reset (Timer 0/1/2/3/4)

2. 32-bit timer single mode [CNT_ENx=0,PTC_MDx=1,CAP_ENx=0]

32-bit Timer with single mode (Timer 0/1/2/3/4)

3. 32-bit counter auto-reset mode [CNT_ENx=1,PTC_MDx=0,CAP_ENx=0]

32-bit Counter with auto-reset (Timer2/4)

4. 32-bit counter single mode [CNT_ENx=1,PTC_MDx=1,CAP_ENx=0]

32-bit Counter with single mode (Timer2/4)

5. 32-bit capture mdoe [CAP_ENx=1]

32-bit Timer/Counter with Capture (Timer2/4 : PTCLOAD PTCCOUNT)


6.9. Timer/Counter : PTC 0

- - - - - - - EDGE_SEL0 - CNT_EN0 CAP_EN0 RST_CNT0 TF0 TIEN0 PCT_MD0 TR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

PTC0CON (0264h) : PTC0 Control Register

EDGE_SEL0 : Capture and Count using each edge in PTC0 (0 : positive, 1 : negative) CNT_EN0 : Enable Counter mode in PTC0 (0 : disable, 1 : enable) CAP_EN0 : Enable Capture mode in PTC0 (0 : disable, 1 : enable) RST_CNT0 : Reset PTCCOUNT in PTC0 (0 : reset, 1 : no reset) TF0 : Timer interrupt flag in PTC0 (0 : no interrupt, 1 : interrupt) TIEN0 : Enable Timer interrupt in PTC0 (0 : disable, 1 : enable) PCT_MD0 : PTC0 mode (0 : auto-reset, 1 : single mode) TR0 : Run PTC0 (0 : stop 1 : run)

PTC0COUNT_L (0260h) : PTC0 Counter Low Register

PTCCNT15 PTCCNT14 PTCCNT13 PTCCNT12 PTCCNT11 PTCCNT10 PTCCNT9 PTCCNT8 PTCCNT7 PTCCNT6 PTCCNT5 PTCCNT4 PTCCNT3 PTCCNT2 PTCCNT1 PTCCNT0


PTC0COUNT_H (0261h) : PTC0 Counter High Register



PTC0LOAD_L (0262h) : PTC0 Capture Low Register

PTCLD15 PTCLD14 PTCLD13 PTCLD12 PTCLD11 PTCLD10 PTCLD9 PTCLD8 PTCLD7 PTCLD6 PTCLD5 PTCLD4 PTCLD3 PTCLD2 PTCLD1 PTCLD0


PTC0LOAD_H (0263h) : PTC0 Capture High Register








EDGE_SEL1 : Capture and Count using each edge in PTC1 (0 : positive, 1 : negative) CNT_EN1 : Enable Counter mode in PTC1 (0 : disable, 1 : enable) CAP_EN1 : Enable Capture mode in PTC1 (0 : disable, 1 : enable) RST_CNT1 : Reset PTCCOUNT in PTC1 (0 : reset, 1 : no reset) TF1 : Timer interrupt flag in PTC1 (0 : no interrupt, 1 : interrupt) TIEN1 : Enable Timer interrupt in PTC1 (0 : disable, 1 : enable) PCT_MD1 : PTC1 mode (0 : auto-reset, 1 : single mode) TR1 : Run PTC1 (0 : stop 1 : run)

















PTC2CON (026Eh) : PTC2 Control Register

EDGE_SEL2 : Capture and Count using each edge in PTC2 (0 : positive, 1 : negative) CNT_EN2 : Enable Counter mode in PTC2 (0 : disable, 1 : enable) CAP_EN2 : Enable Capture mode in PTC2 (0 : disable, 1 : enable) RST_CNT2 : Reset PTCCOUNT in PTC2 (0 : reset, 1 : no reset) TF2 : Timer interrupt flag in PTC2 (0 : no interrupt, 1 : interrupt) TIEN2 : Enable Timer interrupt in PTC2 (0 : disable, 1 : enable) PCT_MD2 : PCT2 mode (0 : auto-reset, 1 : single mode) TR2 : Run PTC2 (0 : stop 1 : run)

PTC2COUNT_L (026Ah) : PTC2 Counter Low Register



PTC2COUNT_H (026Bh) : PTC2 Counter High Register



PTC2LOAD_L (026Ch) : PTC2 Capture Low Register



PTC2LOAD_H (026Dh) : PTC2 Capture High Register









PTC3COUNT_L (026Fh) : PTC3 Counter Low Register































6.9. Timer/Counter : Timer Mode Description

[Capture Mode : Timer2]

FSYS

TR2

CONTROL

EDGE_SEL2

CONTROL

Transition Detection

P3.0/P3.1 PIN

Capture

[Auto Reset Mode : Timer0/1/2]

TRx

CONTROL

Overflow (load_match)

Timer 0/1/2/3/4 Interrupt

Reset

CAP_EN2

PTC2COUNT_H PTC2COUNT_L

PCT2LOAD_H PCT2LOAD_L

FSYS

PCTxLOAD_H PCTxLOAD_L

PTCxCOUNT_H PTCxCOUNT_L

EDGE_SEL2 : for timer2

Transition Detection

P3.0/P3.1 PIN

CNT_EN2 : for timer2

TF2

PCT_MDx

CONTROL

Timer 2/4 Interrupt

TF2

Overflow (load_match)

TIEN2

TIEN2

P3.0 : Timer 2, P3.1 : Timer 4 , Timer 0,1 and 3 doesn’t have external count or capture pin


6.10. UART

FIFO only operating : Selectable FIFO trigger level Compatible with standard 16550 chip except for FIFO mode Various asynchronous data format

DSP Bus

Interface

CPU Bus


6.10. UART : Registers (1 of 8)

- - - - - - - - - - - - Reserved

0 RSIF TEIF RXIF

R/W(0) R/W(0) R/W(0) R/W(0)

IER0 (01E1h) : Serial interface0 Interrupt Enable Register

RXIF : Received data available interrupt enable (0 : disable, 1 : enable) TEIF : TBR0 empty interrupt enable and RX FIFO timeout interrupt enable (0 : disable, 1 : enable) RSIF : Receiver line status interrupt enable (0 : disable, 1 : enable) Reserved 0 : Always 0

- - - - - - - - RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

RBR0 (01E0h) : Serial interface0 Receiver Buffer Register

- - - - - - - - TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

W(0) W(0) W(0) W(0) W(0) W(0) W(0) W(0)

TBR0 (01E0h) : Serial interface0 Transmitter Buffer Register

- - - - - - - - DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0


DLLR0 (01E0h) : Serial interface0 Divisor Latch Low Register (when DLA bit in LCR0 register is set to ‘1’)


R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)

DLHR0 (01E1h) : Serial interface0 Divisor Latch High Register (when DLA bit in LCR0 register is set to ‘1’)

The firmware may set LC register bits to access Divisor Latch. The offset addresses of Divisor Latch are 0 for the LSB 8-bit and 1 for the MSB 8-bit. LSB and MSB comprise a whole 16-bit register. The firmware should turn off LC register bits to access normal registers. The Divisor Latch is set to ‘0’ on reset. In other words, all serial IO operations are disabled in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed)/(16x desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.



- - - - - - - - RF_TR1 RF_TR0 - - - RST_TXF RST_RXF -

W(1) W(1) W(0) W(0)

FCR0 (01E2h) : Serial interface0 FIFO Control Register

RST_RXF : Clear Rx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RST_TXF : Clear Tx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RF_TR[1:0] : Receiver FIFO interrupt trigger level (00 : 1byte, 01 : 4bytes, 10 : 8bytes, 11 : 14bytes)

- - - - - - - - - - - - SID2 SID1 SID0 SIF

R (1) R (1) R(0) R(0) R(0) R(1)

IIR0 (01E2h) : Serial interface0 Interrupt Identification Register

SIF : Serial interface0 interrupt flag (0 : interrupt pending, 1 : no interrupt pending) SID[2:0] : Serial interface0 interrupt identification (011) Priority : 1st Interrupt type : Receiver line status Interrupt source : Parity overrun or Framing errors or Break interrupt Interrupt reset control : Reading the Line Status Register (010) Priority : 2nd Interrupt type : Receiver data available Interrupt source : FIFO trigger level reached Interrupt reset control : FIFO drops below trigger level (110) Priority : 2nd Interrupt type : Timeout indication Interrupt source : There’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times Interrupt reset control : Reading the Line Status Register (001) Priority : 4th Interrupt type : Transmitter Holding Register Empty Interrupt source : Transmit FIFO empty Interrupt reset control : Writing TX data to FIFO or Reading IIR0 when Transmitter Holding Register Empty interrupt is occurred (000) Reserved



- - - - - - - - DLA BC SP EP PE NSB NCH1 NCH0


LCR0 (01E3h) : Serial interface0 Line Control Register

NCH[1:0] : Select number of bits in each character (00 : 5bits, 01 : 6bits, 10 : 7bits, 11 : 8bits) NSB : Specify the number of generated stop bits (0 : 1 stop bit, 1 : 1.5 stop bits @ 5-bit char / 2 stop bits @ otherwise char) PE : Parity Enable (0 : no parity, 1 : parity in both Rx and Tx) EP : Select Even Parity (0 : odd parity, 1 : even parity) SP : Stick Parity (0 : stick parity disabled, 1 : If bits 3, 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.) BC : Break Control bit (0 : break is disabled, 1 : the serial out is forced into logic ‘0’) DLA : Divisor Latch Access (0 : the divisor latches can be accessed, 1 : the normal registers are accessed)

- - - - - - - - ERRI TEI TFE BII FEI PEI OEI DRI

R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)

LSR0 (01E5h) : Serial interface0 Line Status Register

DRI : Data Ready (DR) indicator (0 : No char, 1 : At least one char is in FIFO ) OEI : Overrun Error (OE) indicator (0 : No overrun, 1 : If the FIFO is full and another character has been received in the receiver shifter register. If another character is starting to arrive, it will overwrite the data in the shifter register but the FIFO will remain intact. The bit is cleared upon reading from the register. This generates ‘receiver line status’ interrupt. ) PEI : Parity Error (PE) indicator (0 : No PE, 1 : The character currently at the top of FIFO has been received with parity error. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) FEI : Framing Error (FE) indicator (0 : No FE, 1 : The character currently at the top of FIFO did not have a valid stop bit. It might be all the following data is corrupt. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt.) BII : Break Interrupt (BI) indicator (0 : No BI, 1 : A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character, i.e., start bit + data + parity + stop bit. In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive the next character. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) TFE : Transmitter Ready Indicator (0 : No, 1 : The transmitter FIFO is empty. It generates ‘transmitter holding register empty’ interrupt. The bit is cleared when data is being been written to the transmitter FIFO. ) TEI : Divisor Latch Access (0 : No, 1 : Both the transmitter FIFO and transmitter shifter register are empty. The bit is cleared when data is being written to the transmitter FIFO. ) ERRI : Error Indicator (0 : No, 1 : At least one parity error, framing error or break indications have

been received and are inside the FIFO. The bit is cleared upon reading from the register. )



- - - - - - - - - - - - - - Reserved IOPATHEN0

R/W(0) R/W(0)

IOEN0(01EAh) : UART Path Enable Register

IOPATHEN0 : 1st UART PATH enable (0 : disable, 1 : enable)

- - - - - - - - - - - - - - - UART_BK_EN

R/W(0)

ENR0(01E8h) : UART Block Enable Register

UART_BK_EN : UART block enable (0 : disable, 1 : enable)

- - - - - - - - - - - TF_CNT4 TF_CNT3 TF_CNT2 TF_CNT1 TF_CNT0

R(0) R(0) R(0) R(0) R(0)

TCR0(01E9h) : UART TX FIFO Counter Register

TF_CNT[4:0] : UART TX FIFO data counter value (0 : empty, others : the number of TX data to transmit)



- - - - - - - - - - - - Reserved

0 RSIF TEIF RXIF

R/W(0) R/W(0) R/W(0) R/W(0)

IER1 (0201h) : Serial interface1 Interrupt Enable Register

RXIF : Received data available interrupt enable (0 : disable, 1 : enable) TEIF : TBR1 empty interrupt enable and RX FIFO Timeout interrupt enable (0 : disable, 1 : enable) RSIF : Receiver line status interrupt enable (0 : disable, 1 : enable) Reserved 0 : Always 0

- - - - - - - - RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

RBR1 (0200h) : Serial interface1 Receiver Buffer Register

- - - - - - - - TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

W(0) W(0) W(0) W(0) W(0) W(0) W(0) W(0)

TBR1 (0200h) : Serial interface1 Transmitter Buffer Register



DLLR1 (0200h) : Serial interface1 Divisor Latch Low Register (when DLA bit in LCR1 register is set to ‘1’)


R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)

DLHR1 (0201h) : Serial interface1 Divisor Latch High Register (when DLA bit in LCR1 register is set to ‘1’)

The firmware may set LC register bits to access Divisor Latch. The offset addresses of Divisor Latch are 0 for the LSB 8-bit and 1 for the MSB 8-bit. LSB and MSB comprise a whole 16-bit register. The firmware should turn off LC register bits to access normal registers. The Divisor Latch is set to ‘0’ on reset. In other words, all serial IO operations are disabled in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed)/(16x desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.



- - - - - - - - RF_TR1 RF_TR0 - - - RST_TXF RST_RXF -

W(1) W(1) W(0) W(0)

FCR1 (0202h) : Serial interface1 FIFO Control Register

RST_RXF : Clear Rx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RST_TXF : Clear Tx FIFO and reset its logic except for shift register (0 : not reset, 1 : reset) RF_TR[1:0] : Receiver FIFO interrupt trigger level (00 : 1byte, 01 : 4bytes, 10 : 8bytes, 11 : 14bytes)

- - - - - - - - - - - - SID2 SID1 SID0 SIF

R (1) R (1) R(0) R(0) R(0) R(1)

IIR1 (0120h) : Serial interface1 Interrupt Identification Register

SIF : Serial interface0 interrupt flag (0 : interrupt pending, 1 : no interrupt pending) SID[2:0] : Serial interface0 interrupt identification (011) Priority : 1st Interrupt type : Receiver line status Interrupt source : Parity overrun or Framing errors or Break interrupt Interrupt reset control : Reading the Line Status Register (010) Priority : 2nd Interrupt type : Receiver data available Interrupt source : FIFO trigger level reached Interrupt reset control : FIFO drops below trigger level (110) Priority : 2nd Interrupt type : Timeout indication Interrupt source : There’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times Interrupt reset control : Reading the Line Status Register (001) Priority : 3rd Interrupt type : Transmitter Holding Register Empty Interrupt source : Transmit FIFO empty Interrupt reset control : Writing TX data to FIFO or Reading IIR1 when Transmitter Holding Register Empty interrupt is occurred . (000) Reserved



- - - - - - - - DLA BC SP EP PE NSB NCH1 NCH0


LCR1 (0203h) : Serial interface1 Line Control Register

NCH[1:0] : Select number of bits in each character (00 : 5bits, 01 : 6bits, 10 : 7bits, 11 : 8bits) NSB : Specify the number of generated stop bits (0 : 1 stop bit, 1 : 1.5 stop bits @ 5-bit char / 2 stop bits @ otherwise char) PE : Parity Enable (0 : no parity, 1 : parity in both Rx and Tx) EP : Select Even Parity (0 : odd parity, 1 : even parity) SP : Stick Parity (0 : stick parity disabled, 1 : If bits 3, 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.) BC : Break Control bit (0 : break is disabled, 1 : the serial out is forced into logic ‘0’) DLA : Divisor Latch Access (0 : the divisor latches can be accessed, 1 : the normal registers are accessed)

- - - - - - - - ERRI TEI TFE BII FEI PEI OEI DRI

R (0) R (0) R (0) R (0) R (0) R (0) R (0) R (0)

LSR1 (0205h) : Serial interface1 Line Status Register

DRI : Data Ready (DR) indicator (0 : No char, 1 : At least one char is in FIFO ) OEI : Overrun Error (OE) indicator (0 : No overrun, 1 : If the FIFO is full and another character has been received in the receiver shifter register. If another character is starting to arrive, it will overwrite the data in the shifter register but the FIFO will remain intact. The bit is cleared upon reading from the register. This generates ‘receiver line status’ interrupt. ) PEI : Parity Error (PE) indicator (0 : No PE, 1 : The character currently at the top of FIFO has been received with parity error. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) FEI : Framing Error (FE) indicator (0 : No FE, 1 : The character currently at the top of FIFO did not have a valid stop bit. It might be all the following data is corrupt. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt.) BII : Break Interrupt (BI) indicator (0 : No BI, 1 : A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character, i.e., start bit + data + parity + stop bit. In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive the next character. The bit is cleared upon reading from the register. It generates ‘receiver line status’ interrupt. ) TFE : Transmitter Ready Indicator (0 : No, 1 : The transmitter FIFO is empty. It generates ‘transmitter holding register empty’ interrupt. The bit is cleared when data is being been written to the transmitter FIFO. ) TEI : Divisor Latch Access (0 : No, 1 : Both the transmitter FIFO and transmitter shifter register are empty. The bit is cleared when data is being written to the transmitter FIFO. ) ERRI : Error Indicator (0 : No, 1 : At least one parity error, framing error or break indications have

been received and are inside the FIFO. The bit is cleared upon reading from the register. )



- - - - - - - - - - - - - - IOPATHEN1

IOPATHEN0

R/W(0) R/W(0)

IOEN1 (020Ah) : UART Path Enable Register

IOPATHEN0 : 1st UART PATH enable (0 : disable, 1 : enable) IOPATHEN1 : 2ND UART PATH enable (0 : disable, 1 : enable)

- - - - - - - - - - - - - - - UART_BK_EN

R/W(0)

ENR1(0208h) : UART Block Enable Register

UART_BK_EN : UART block enable (0 : disable, 1 : enable)

- - - - - - - - - - - TF_CNT4 TF_CNT3 TF_CNT2 TF_CNT1 TF_CNT0

R(0) R(0) R(0) R(0) R(0)

TCR1(0209h) : UART TX FIFO Counter Register

TF_CNT[4:0] : UART TX FIFO data counter value (0 : empty, others : the number of TX data to transmit)

SeJong200 Family

6.11. I2C : Registers (1 of 6)

Two-wire Interface Two I2C

I2C0 : Master or Slave Operation I2C1 : Master or Slave Operation

Transmitter or Receiver Operation 100kbps (Min. FSYS = 1MHz),

400kbps (Min. FSYS = 4MHz) 7-bit / 10-bit (Extended 15-bit) Address Mode

Transfer Wait State Fully Programmable Slave Address SDA/SCL Schmitt-trigger input 256 Programmable Bit Rates Wake-up from IDLE mode Compatible with Phillips I2C protocol

[62]

- - - - - SDAHDT_OVF SCLHDT_OVF I2CBB I2CIF I2COF I2CACK I2CRW I2CDA I2CP I2CS I2CBF

R/W(0) R/W(0) R(0) R/W(0) R/W(0) R (0) R (0) R (0) R (0) R (0) R (0)

I2C0ST (0160h) : I2C0 Status Register

SDAHDT_OVF : I2C SDA Hold Timer Overflow (0 : No overflow, 1 : Overflow) SCLHDT_OVF : I2C SCL Hold Timer Overflow (0 : No overflow, 1 : Overflow) I2CBB : I2C byte transmission busy flag (0 : Not busy, 1 : Busy) I2CIF : I2C Master Interrupt Flag in slave & master mode. (0 : Idle, 1 : Interrupt occurred) It is set each time a byte is received or transmitted. If SP_IE flag in I2C_CFG register is set, it is set at Start/Stop condition. The flag is set by H/W and cleared by S/W. I2COF : I2C Overflow Flag in slave & master mode. (0 : Idle, 1 : Overflow occurred) It is set when a byte is received while I2C_BUF register is still holding the previous byte. It is set by H/W and cleared by S/W. I2CACK : I2C Acknowledge flag in slave & master mode. (0 : Receiving Acknowledge bit, 1 : Receiving Not Acknowledge bit) I2CRW : I2C Read/Write flag in slave mode (0 : Write state, 1 : Read state) I2CDA : Data / Address flag in slave mode

(0 : the last byte received or transmitted was Data, 1 : Indicates the last byte received or transmitted was Address) I2CP : Stop flag in slave & master mode (0 : Stop bit was not detected, 1 : Stop bit was detected) This flag is cleared when I2CS is set or I2CEN is cleared. I2CS : Start flag in slave & master mode (0 : Start bit was not detected, 1 : Start bit was detected) This flag is cleared when I2CP is set or I2CEN is cleared. I2CBF : Busy flag in slave & master mode

(0 : RX not complete (Receiver), TX not complete (Transmitter), 1 : RX complete (Receiver), TX complete (Transmitter))

SeJong200 Family


[63]

- - - - - - - - Reserved SLA2ME SCLHD LASTB PGEN SGEN I2CIOENB0 I2CEN


I2C0CON (0161h) : I2C0 Control Register

SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode (0 : 2nd Byte SLA Match Disable, 1 : 2nd SLA Byte Match Enable) SCLHD : Hold SCL ‘low’ for Wait State in Slave mode. (0 : Hold SCL ‘low’. The flag is cleared automatically by H/W, 1 : Release SCL ‘float’. The flag is set by S/W) LASTB : Indicate last byte in Master Receiver mode. (0 : Send Ack after last byte, 1 : Send Not Ack after last byte) In Master Receiver mode, before receiving last byte, the flag must be set. PGEN : Generate Stop bit. (0 : Start or Idle state, 1 : Generate Stop bit.) The flag is cleared automatically after Stop bit in Master mode and when I2CEN is cleared. SGEN : Generate Start bit (0 : Stop or Idle state, 1 : Generate Start bit) If the bus is not free, it waits for Stop bit condition. The flag is cleared automatically after Start bit in Master mode and when I2CEN is cleared. I2CIOENB0 : Enable I2C 1st PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) I2CEN : Enable I2C module (0 : Disable I2C module, 1 : Enable I2C module)

- - - - - - - - HDINTR_EN SDAHDT_EN SCL_HDT_EN TXDBUT_EN MSSEL ADSEL SP_IE GCE


I2C0CFG (0162h) : I2C0 Configuration Register

HDINTR_EN : Hold timer interrupt enable flag (0 : Disable, 1 : Enable) SDAHDT_EN : SDA hold release timer enable flag (0 : Disable, 1 : Enable) SCLHDT_EN : SCL hold release timer enable flag (0 : Disable, 1 : Enable) TXDBUF_EN : TX double buffer enable flag (0 : Disable, 1 : Enable) MSSEL: I2C Master/Slave Mode Selection (0 : Slave mode, 1 : Master mode) ADSEL : 7-bit / 10-bit Address Mode Selection in Slave mode (0 : 7-bit mode, 1 : 10-bit mode) SP_IE : Start/Stop Interrupt Enable (0 : Start/Stop Interrupt Disable, 1 : Start/Stop Interrupt Enable) GCE : General Call Enable in Slave mode (1 : Respond to the general call address (0x00))

SeJong200 Family


[64]

- - - - - - - - MDAT.7 MDAT.6 MDAT.5 MDAT.4 MDAT.3 MDAT.2 MDAT.1 MDAT.0


I2C0DAT (0164h) : I2C0 Address / Data Register

- - - - - - - - MSCL.7 MSCL.6 MSCL.5 MSCL.4 MSCL.3 MSCL.2 MSCL.1 MSCL.0


I2C0SCL (0165h) : I2C0 SCL Clock Scale Register

MSCL[7:0] : Frequency Scaler of I2C Master : FI2C = FSYS / (2 * (MSCL[7:0] + 2))

- - - - - - - - SLA1.7 SLA1.6 SLA1.5 SLA1.4 SLA1.3 SLA1.2 SLA1.1 SLA1.0


I2C0SLA (0163h) : I2C0 Slave Address Register

SLA[7:0] : I2C Slave Address Register. In 7-bit address mode and in 10-bit address mode (1st SLA), I2C_SLA[7:1] is used for matching address and I2C_SLA[0] is masked. In 10-bit address mode (2nd SLA), I2C_SLA[7:0] is used for matching address.

SDAHDT15 SDAHDT14 SDAHDT13 SDAHDT12 SDAHDT11 SDAHDT10 SDAHDT9 SDAHDT8 SDAHDT7 SDAHDT6 SDAHDT5 SDAHDT4 SDAHDT3 SDAHDT2 SDAHDT1 SDAHDT0


I2C0SDAHDT (0167h) : I2C0 SDA Hold Timer Register

SDAHDT : I2C SDA Hold Timer Register. After the timer is overflowed, SDA pin held during communication is released.

SCLHDT15 SCLHDT14 SCLHDT13 SCLHDT12 SCLHDT11 SCLHDT10 SCLHDT9 SCLHDT8 SCLHDT7 SCLHDT6 SCLHDT5 SCLHDT4 SCLHDT3 SCLHDT2 SCLHDT1 SCLHDT0


I2C0SCLHDT (0166h) : I2C0 SCL Hold Timer Register

SCLHDT : I2C SCL Hold Timer Register. After the timer is overflowed, SCL pin held during communication is released.

SeJong200 Family


[65]

- - - - - - - - I2CIF I2COF I2CACK I2CRW I2CDA I2CP I2CS I2CBF

R/W(0) R/W(0) R (0) R (0) R (0) R (0) R (0) R (0)

I2C1ST (0180h) : I2C1 Status Register

I2CIF : I2C Master Interrupt Flag in slave & master mode. (0 : Idle, 1 : Interrupt occurred) It is set each time a byte is received or transmitted. If SP_IE flag in I2C_CFG register is set, it is set at Start/Stop condition. The flag is set by H/W and cleared by S/W. I2COF : I2C Overflow Flag in slave & master mode. (0 : Idle, 1 : Overflow occurred) It is set when a byte is received while I2C_BUF register is still holding the previous byte. It is set by H/W and cleared by S/W I2CACK : I2C Acknowledge flag in slave & master mode. (0 : Receiving Acknowledge bit, 1 : Receiving Not Acknowledge bit) I2CRW : I2C Read/Write flag in slave mode (0 : Write state, 1 : Read state) I2CDA : Data / Address flag in slave mode

(0 : the last byte received or transmitted was Data, 1 : Indicates the last byte received or transmitted was Address) I2CP : Stop flag in slave & master mode (0 : Stop bit was not detected, 1 : Stop bit was detected) This flag is cleared when I2CS is set or I2CEN is cleared. I2CS : Start flag in slave & master mode (0 : Start bit was not detected, 1 : Start bit was detected) This flag is cleared when I2CP is set or I2CEN is cleared. I2CBF : Busy flag in slave & master mode

(0 : RX not complete (Receiver), TX not complete (Transmitter), 1 : RX complete (Receiver), TX complete (Transmitter))

SeJong200 Family


[66]

- - - - - - - - I2CIOENB

1 SLA2ME SCLHD LASTB PGEN SGEN I2CIOENB0 I2CEN


I2C1CON (0181h) : I2C1 Control Register

I2CIOENB1 : Enable I2C 2nd PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode (0 : 2nd Byte SLA Match Disable, 1 : 2nd SLA Byte Match Enable) SCLHD : Hold SCL ‘low’ for Wait State in Slave mode. (0 : Hold SCL ‘low’. The flag is cleared automatically by H/W, 1 : Release SCL ‘float’. The flag is set by S/W) LASTB : Indicate last byte in Master Receiver mode. (0 : Send Ack after last byte, 1 : Send Not Ack after last byte) In Master Receiver mode, before receiving last byte, the flag must be set. PGEN : Generate Stop bit. (0 : Start or Idle state, 1 : Generate Stop bit.) The flag is cleared automatically after Stop bit in Master mode and when I2CEN is cleared. SGEN : Generate Start bit (0 : Stop or Idle state, 1 : Generate Start bit) If the bus is not free, it waits for Stop bit condition. The flag is cleared automatically after Start bit in Master mode and when I2CEN is cleared. I2CIOENB0 : Enable I2C 1st PATH IO (0 : Disable I2C IO, 1 : Enable I2C IO) I2CEN : Enable I2C module (0 : Disable I2C module, 1 : Enable I2C module)

- - - - - - - - HDINTR_EN SDAHDT_EN SCL_HDT_EN TXDBUT_EN MSSEL ADSEL SP_IE GCE


I2C1CFG (0182h) : I2C1 Configuration Register

HDINTR_EN : Hold timer interrupt enable flag (0 : Disable, 1 : Enable) SDAHDT_EN : SDA hold release timer enable flag (0 : Disable, 1 : Enable) SCLHDT_EN : SCL hold release timer enable flag (0 : Disable, 1 : Enable) TXDBUF_EN : TX double buffer enable flag (0 : Disable, 1 : Enable) MSSEL: I2C Master/Slave Mode Selection (0 : Slave mode, 1 : Master mode) ADSEL : 7-bit / 10-bit Address Mode Selection in Slave mode (0 : 7-bit mode, 1 : 10-bit mode) SP_IE : Start/Stop Interrupt Enable (0 : Start/Stop Interrupt Disable, 1 : Start/Stop Interrupt Enable) GCE : General Call Enable in Slave mode (1 : Respond to the general call address (0x00))

SeJong200 Family


[67]

- - - - - - - - MDAT.7 MDAT.6 MDAT.5 MDAT.4 MDAT.3 MDAT.2 MDAT.1 MDAT.0


I2C1DAT (0184h) : I2C1 Address / Data Register

- - - - - - - - MSCL.7 MSCL.6 MSCL.5 MSCL.4 MSCL.3 MSCL.2 MSCL.1 MSCL.0


I2C1SCL (0185h) : I2C1 SCL Clock Scale Register

MSCL[7:0] : Frequency scaler of I2C Master : FI2C = FSYS / (2 * (MSCL[7:0] + 2))

- - - - - - - - SLA1.7 SLA1.6 SLA1.5 SLA1.4 SLA1.3 SLA1.2 SLA1.1 SLA1.0


I2C1SLA (0183h) : I2C1 Slave Address Register

SLA[7:0] : I2C Slave Address Register. In 7-bit address mode and in 10-bit address mode (1st SLA), I2C_SLA[7:1] is used for matching address and I2C_SLA[0] is masked. In 10-bit address mode (2nd SLA), I2C_SLA[7:0] is used for matching address.

SeJong200 Family [68] [68]

6.11. I2C : Block Diagram

FPERI

Clock D

ivider

Clock Selection

Logic

Fspi

I2C_SDA

Internal BUS

MSSEL

I2CIF I2C Interrupt

SDA_OE

I2C_SCL

I2C_SLA

Address Match Detector

I2C_ST

Address match

Upload I2C_DAT

EI2C

I2C_CFG

I2C_DAT

Download I2C_DAT

8bit Shift Register

I2C_CON

SCL_OE

FPERI : Peripheral Clock

I2C Control Logic


6.11. I2C : Overview (1 of 2)

Addressing I2C devices 7-bit Address Format

S A7 A6 A5 A4 A3 A2 A1 R/W /ACK

MSb LSb

Slave Address (SLA)

10-bit / Extended 15-bit Address Format

S A15 A14 A13 A12 A11 A10 A9 R/W /ACK A7 A6 A5 A4 A3 A2 A1 A0 /ACK

MSb LSb

SLA SLA

Transfer Acknowledge Slave-Receiver generates an acknowledge bit after Master transfers each byte. If not, Master aborts the transfer. Master-Receiver generates an acknowledge bit after Slave transfers each byte except last byte. Transfer Wait State 1) If Slave needs to delay the transmission of the next byte, it can hold the SCL ‘low’ 2) Master must enter the wait state, if the SCL is held ‘low’. 3) When Slave releases the SCL, Master starts the transfer again.

Not A0

Not A8

S 1 2 3~6 7 8 9 1 2 3~8 9 P

SDA

SCL

SLA R/W /ACK Wait State Data /ACK

Slave holds SCL Slave releases SCL

Not ACK

ACK


[7-bit Address Mode] [10-bit / Extended 15-bit Address Mode]

6.11. I2C : Overview (2 of 2)

Master-Transmitter Sequence

S SLA R/W (0)

A Data A Data

A P

/A S SLA1

R/W (0)

A SLA2 A Data A Data A

P /A

S SLA R/W (1)

A Data A Data /A P S SLA1

R/W (0)

A SLA2 A

Sr SLA1 R/W (1)

A Data A Data /A P

From Slave to Master From Master to Slave

~

~

~

~

~

~

~

~

[7-bit Address Mode] [10-bit / Extended 15-bit Address Mode]

Master-Receiver Sequence

~

~

~

~

~

~

~

~

Combined Format When Master does not want to release the bus, a repeated start condition must be generated without a stop condition. The condition is identical to a start condition The condition must occurs after a data transfer acknowledge pulse.

A : Acknowledge /A : Nor Acknowledge S : Start Sr : Repeated Start P : Stop SLA : Slave Address


6.12. SPI : Registers (1 of 2)

Full-duplex, Three-wire Synchronous Data Transfer Slave Operation LSB First or MSB First Data Transfer Eight Programmable Bit Rates

Clock Polarity & Phase Selection Support Write Collision Protection Wake-up from IDLE mode

- - - - - - - - DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0


SPIDR (01A3h) : SPI TX / RX Data Register

- - - - - - - - - - - - TXBV SPIF SPICOL SPIOF

R(0) R/W(0) R/W(0) R/W(0)

SPIST (01A0h) : SPI Status Register

TXBV : TX buffer of SPIDR holds valid data. [1] : Set by H/W when user write SPIDR while SPI is enabled. [0] : Cleared by H/W when the data is moved to TX shift register or SPI is disabled. SPIF : SPI Interrupt Flag [1] : Serial transfer is complete. If SPIE is set and EA is set, SPI interrupt is generated. [0] : no interrupt SPICOL : SPI Write Collision Flag [1] : SPIDR is written when TXBV is set. The previous data is lost. [0] : no collision

SPIOF : SPI Read Overflow Flag [1] : If a new data is received while SPIDR is still holding the previous data, the flag is set. SPIF must be cleared before receiving a data again. [0] : no overflow


6.12. SPI : Registers (2 of 2)

- - - - - - - - SPIOEN1 MODE BORD MSSEL CKPOL CKPHA SPIOEN0 SPIEN

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

SPICON (01A1h) : SPI Control Register

SPIOEN1 : SPI 2nd Path Output Enable (0 : SPI Output Disable, 1 : SPI Output Enable) MODE : SPI mode selection (0 : 4-wire mode, 1 : 3-wire mode) BORD : SPI Transfer Bit Order (0 : First MSB, Last LSB, 1 : First LSB, Last MSB) MSSEL : SPI Master/Slave Selection (0 : SPI Slave Mode, 1 : SPI Master Mode) CKPOL, CKPHA : SPI clock Polarity & Phase [0,0] : Leading edge Rising, Leading edge Sampling [0,1] : Leading edge Rising, Trailing edge Sampling [1,0] : Leading edge Falling, Leading edge Sampling [1,1] : Leading edge Falling, Trailing edge Sampling SPIOEN0 : SPI 1st Path Output Enable (0 : SPI Output Disable, 1 : SPI Output Enable) SPIEN : SPI Enable Flag (0 : SPI Disable, 1 : SPI Enable)

- - - - - - - - - - - - - SPICK2 SPICK1 SPICK0

R/W(0) R/W(0) R/W(0)

SPICK (01A2h) : SPI Clock Control Register

SPICK[2:0] : SPI Master Clock Divider [0,0,0] : FSYS / 2 [0,0,1] : FSYS / 4 [0,1,0] : FSYS / 8 [0,1,1] : FSYS / 16 [1,0,0] : FSYS / 32 [1,0,1] : FSYS / 64 [1,1,0] : FSYS / 128 [1,1,1] : FSYS / 256


6.12. SPI : Block Diagram

Internal BUS

FPERI

Clock D

ivider

8bit Shift Register (SPI Write Data Buffer)

SPI Read Data Buffer

Fspi

Load SPIDR

MISO

MOSI

1 0

SPI Control Logic

Internal BUS

Write SPIDR

Read SPIDR

SPICK[2:0]

MSSEL

SCK

MSSEL

CKPOL CKPHA

BORD

SPI Register SPIF

ESPI SPI Interrupt

SPIOENB

Clock Selection

Logic

FPERI : Peripheral Clock


6.12. SPI : Overview

SPI Slave Interconnection

8 BIT SHIFT REGISTER

CLOCK GENERATOR

MISO MISO

MOSI MOSI

SCK SCK

GPIO /SS /SS

Master Slave

SPI Pin Description

8 BIT SHIFT REGISTER

Slave Enable

Pin Description Direction, Master Direction, Slave

MOSI Master Output Slave Input User Defined Input

MISO Master Input Slave Output Input User Defined

SCK SPI Clock User Defined Input

/SS Slave Select Bar User Defined Input


6.12. SPI : Mode 0/1

SPI Mode 0 CKPOL = 0 : Leading Edge Rising CKPHA = 0 : Leading Edge Sampling

sampling

MOSI (Master) / MISO (Slave)

/SS

SPI Mode 1 CKPOL = 0 : Leading Edge Rising CKPHA = 1 : Trailing Edge Sampling

1 2 3 4 5 6 7 8

MISO (Master) / MOSI (Slave)

sampling

SCK


/SS

1 2 3 4 5 6 7 8


SCK


6.12. SPI : Mode 2/3

SPI Mode 2 CKPOL = 1 : Leading Edge Falling CKPHA = 0 : Leading Edge Sampling

SPI Mode 3 CKPOL = 1 : Leading Edge Falling CKPHA = 1 : Trailing Edge Sampling

sampling

SCK


/SS

1 2 3 4 5 6 7 8


sampling

SCK


/SS

1 2 3 4 5 6 7 8


SeJong200 Family

6.13. PWMA (PWM Arrays)

PWMA Two 8-bit PWM generation with 16 modules (Compatible to M1.0A 8-bit mode) PWM Data buffer Update (8-bit Counter Overflow Update) PWM Counter can be cleared by S/W. PWM is stopped or started (resumed) by S/W.

PWM0/1 MODULE0 P0.00 / PWM0.00 P1.00 / PWM1.00

PWM0/1 Counter






[77]

SeJong200 Family

6.13. PWMA : Block Diagram

PWMCNT PWMA Interrupt

PWNEN

FSYS CPS2,

CPS1, CPS0 PWMOVF Overflow

PWM0.00 (P0.00)

PWMD0 Buffer PWMD0

Comparator

PWM Pulse

Generation

[PWM Module 0]

[PWM Counter]

CPU Write Date CPU Read Date

PWMOEN.0

[78]

SeJong200 Family

6.13. PWMA : PWMA0 Register (1 of 2)

- - - - - - - - - CPS2 CPS1 CPS0 - - PWMOVF PWMEN


PWM0CON (02A0h) : PWMA CH0 Control Register

CPS2, CPS1, CPS0 : PWMA counter frequency selection. [0,0,0] = FSYS / 1 [0,0,1] = FSYS / 2 [0,1,0] = FSYS / 4 [0,1,1] = FSYS / 8 [1,0,0] = FSYS / 16 [1,0,1] = FSYS / 32 [1,1,0] = FSYS / 64 [1,1,1] = FSYS / 128 PWMOVF : PWMA counter overflow flag. Set by hardware and cleared by software. PWMOVF flags an interrupt. PWMEN : PWMA counter run control bit. [0] = Stop the PWMA counter. [1] = Run the PWMA counter.

- - - - - - - - CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0


PWM0CNT (02A1h) : PWMA CH0 Counter Register

Software can write this register for the initialization of the counter.

OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0


PWM0OEN (02A2h) : PWMA CH0 Module Output Enable

OE15 : Module 15 PWM output enable OE14 : Module 14 PWM output enable OE13 : Module 13 PWM output enable OE12 : Module 12 PWM output enable OE11 : Module 11 PWM output enable OE10 : Module 10 PWM output enable OE9 : Module 9 PWM output enable OE8 : Module 8 PWM output enable


[79]

SeJong200 Family


- - - - - - - - PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 PWMD.1 PWMD.0


PWM0D0 (02A3h) : PWMA CH0 Duty Data Register of Module 0

Each Module has a internal buffer register for the duty data register. The buffer register is updated with the new data whenever the PWMA counter rolls over. When user write, the data register is written. When user read, the contents of buffer register is read out.







PWM0D7 (02AAh) : PWMA CH0 Duty Data Register of Module 7

PWM0D8 (02ABh) : PWMA CH0 Duty Data Register of Module 8

PWM0D9 (02ACh) : PWMA CH0 Duty Data Register of Module 9

PWM0D10 (02ADh) : PWMA CH0 Duty Data Register of Module 10

PWM0D11 (02AEh) : PWMA CH0 Duty Data Register of Module 11

PWM0D12 (02AFh) : PWMA CH0 Duty Data Register of Module 12

PWM0D13 (02B0h) : PWMA CH0 Duty Data Register of Module 13



[80]

SeJong200 Family


- - - - - - - - - CPS2 CPS1 CPS0 - - PWMOVF PWMEN


PWM1CON (02C0h) : PWMA CH1 Control Register

CPS2, CPS1, CPS0 : PWMA counter frequency selection. [0,0,0] = FSYS / 1 [0,0,1] = FSYS / 2 [0,1,0] = FSYS / 4 [0,1,1] = FSYS / 8 [1,0,0] = FSYS / 16 [1,0,1] = FSYS / 32 [1,1,0] = FSYS / 64 [1,1,1] = FSYS / 128 PWMOVF : PWMA counter overflow flag. Set by hardware and cleared by software. PWMOVF flags an interrupt. PWMEN : PWMA counter run control bit. [0] = Stop the PWMA counter. [1] = Run the PWMA counter.

- - - - - - - - CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0


PWM1CNT (02C1h) : PWMA CH1 Counter Register

Software can write this register for the initialization of the counter.

OE15 OE14 OE13 OE12 OE11 OE10 OE9 OE8 OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0


PWM1OEN (02C2h) : PWMA CH1 Module Output Enable



[81]

SeJong200 Family


- - - - - - - - PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 PWMD.1 PWMD.0


PWM1D0 (02C3h) : PWMA CH1 Duty Data Register of Module 0

Each Module has a internal buffer register for the duty data register. The buffer register is updated with the new data whenever the PWMA counter rolls over. When user write, the data register is written. When user read, the contents of buffer register is read out.







PWM0D7 (02CAh) : PWMA CH0 Duty Data Register of Module 7

PWM0D8 (02CBh) : PWMA CH0 Duty Data Register of Module 8

PWM0D9 (02CCh) : PWMA CH0 Duty Data Register of Module 9

PWM0D10 (02CDh) : PWMA CH0 Duty Data Register of Module 10

PWM0D11 (02CEh) : PWMA CH0 Duty Data Register of Module 11

PWM0D12 (02CFh) : PWMA CH0 Duty Data Register of Module 12

PWM0D13 (02D0h) : PWMA CH0 Duty Data Register of Module 13



[82]

SeJong200 Family

6.13. PWMA : Pulse Generation Example

Clock Count 000h

Clock Count 100h

Clock Count 200h

Clock Count 300h

Clock Count 400h

PWM Clock (FSYS/1)

PWM Out

PWM Out

PWM Out

PWM Out

1 Clock Cycle

Low

(50% Duty)

1 Clock Cycle

(PWMxDy = 00h)

(PWMxDy = 01h)

(PWMxDy = 80h)

(PWMxDy = FFh)

[83]


6.14. Self Touch Sensor : Registers (1 of 9)

Support capacitive sensing scheme Max. 26-channel Touch Sensor Max. 65,536 (16-bit) level sensitivity Extremely low power sensing solution

- - - - - - - - - - - - - - TSIF TS_RUN

R/W(0) R/W(0)

TSCON (0220h) : Touch Sensor Control Register

TS_RUN : [1] Run touch sensing. Set by S/W, cleared by H/W. TSIF : Touch sensing interrupt flag. [1] touch sensing interrupt occurred. Set by H/W, cleared by S/W

- - - - - - - - - - - - TSTYP TSPN - -

R/W(0) R/W(0)

TSCFG (0221h) : Touch Sensor Configuration Register

TSPN : [0] Discharging type [1] Charging type @ HRC mode [1] Full Discharge/Charge mode @ HSD mode [0] Normal Discharge/Charge mode @ HSD mode TSTYP : [1] HSD sensing type [0] HRC sensing type

TSENC15 TSENC14 TSENC13 TSENC12 TSENC11 TSENC10 TSENC9 TSENC8 TSENC7 TSENC6 TSENC5 TSENC4 TSENC3 TSENC2 TSENC1 TSENC0


TSENCNT (0226h) : Touch Sensing Enable Counter Register

TSENCNT : Touch sensing Enable Counter @ HSD mode



- - - - - - - - TSPD23 TSPD22 TSPD21 TSPD20 TSPD19 TSPD18 TSPD17 TSPD16


TSPDH (0222h) : Touch Sensing Pulse Duration High Register

TSPDH/L : Touch sensing Pulse Duration. Pulse duration : TSPD / FTS

TSPD15 TSPD14 TSPD13 TSPD12 TSPD11 TSPD10 TSPD9 TSPD8 TSPD7 TSPD6 TSPD5 TSPD4 TSPD3 TSPD2 TSPD1 TSPD0


TSPDL (0223h) : Touch Sensing Pulse Duration Low Register

- - - - - - - - TSPC23 TSPC22 TSPC21 TSPC20 TSPC19 TSPC18 TSPC17 TSPC16


TSPCH (0224h) : Touch Sensing Count Pre-Cut High Register

TSPCH/L : Touch sensing Pre-Cut Duration. Pre-Cut duration : TSPC / FTS

TSPC15 TSPC14 TSPC13 TSPC12 TSPC11 TSPC10 TSPC9 TSPC8 TSPC7 TSPC6 TSPC5 TSPC4 TSPC3 TSPC2 TSPC1 TSPC0


TSPCL (0225h) : Touch Sensing Count Pre-Cut Low Register



- - - - - - - - SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00


TS_SR (0227h) : Touch Sensor Sensing Resistor selection Register

TS_SR[7:0] Resistor Value

00000001 = 01H 0 (0.2Kohm)

00000110 = 06H 0.33 Kohm

00000010 = 02H 0.50 Kohm

00001100 = 0CH 0.66 Kohm

00010100 = 14H 0.80 Kohm

00000100 = 04H 1.00 Kohm

00011000 = 18H 1.33 Kohm

00101000 = 28H 1.60 Kohm

00001000 = 08H 2.00 Kohm

00110000 = 30H 2.60 Kohm

01010000 = 50H 3.20 Kohm

00010000 = 10H 4.00 Kohm

01100000 = 60H 5.30 Kohm

10100000 = A0H 6.40 Kohm

00100000 = 20H 8.00 Kohm

11000000 = C0H 10.60 Kohm

01000000 = 40H 16.00 Kohm

10000000 = 80H 32.00 Kohm



TSCNT31 TSCNT30 TSCNT29 TSCNT28 TSCNT27 TSCNT26 TSCNT25 TSCNT24 TSCNT23 TSCNT22 TSCNT21 TSCNT20 TSCNT19 TSCNT18 TSCNT17 TSCNT16


TSCNTH (0229h) : Touch Sensor Counter High Register

TSCNT15 TSCNT14 TSCNT13 TSCNT12 TSCNT11 TSCNT10 TSCNT9 TSCNT8 TSCNT7 TSCNT6 TSCNT5 TSCNT4 TSCNT3 TSCNT2 TSCNT1 TSCNT0


TSCNTL (022Ah) : Touch Sensor Counter Low Register

- - - - - - - - - - VIMASK1 VIMASK0 REF_EN FCAP_EN IBTRIM1 IBTRIM0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(1)

TSCOMPCFG (022Bh) : Touch Sensor Comparator Configuration Register

REF_EN : Comparator Reference enable FCAP_EN : Filter Cap. Enable IBTRIM[1:0] : Comparator Bias Current Trimming option VIMASK[1:0] : VIH/VIL Sensing Option Mask [00] : sensing option (VIH : one condition, VIL : one condition) [01] : sensing option (VIH : one condition, VIL : sweep condition) [10] : sensing option (VIH : sweep condition, VIL : one condition) [11] : sensing option (VIH : sweep condition, VIL : sweep condition) In this case, TSVIHOPT SFR must be the same as TSVILOPT SFR

IBTRIM[1:0] Bias current

00 13.3uA/13.0uA 01 26.3uA/26.01uA

10 38.7uA/39.1uA

11 50.0uA/52.1uA



- - - - - - - - - - - - CNTSFT3 CNTSFT2 CNTSFT1 CNTSFT0

R/W(0) R/W(0) R/W(0) R/W(0)

TSCNTSFT (0230h) : Touch Sensor Channel 1 Enable Register

CNTSFT[7:0] : touch sensing counter shift option when reading [0000] : TSCNTL[15:0] TSCNT[15:0] TSCNTH[15:0] TSCNT[31:16] … [1000] : TSCNTL[15:0] TSCNT[23:8] TSCNTH[7:0] TSCNT[31:24] TSCNTH[15:8] 0 … [1111] : TSCNTL[15:0] TSCNT[30:15] TSCNTH[0] TSCNT[31] TSCNTH[15:1] 0



- - - - - - - - - TSEN CHEN.5 CHEN.4 CHEN.3 CHEN.2 CHEN.1 CHEN.0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

TSCHEN (0228h) : Touch Sensor Channel Enable Register

TSEN : Touch Sensing Enable [0] : Touch Sensing Disable (Default) / [1] : Touch Sensing Enable CHSEL[5:0] : touch channel number . when user use touch , ADC or LCDC must not be used at the same port

[000000] : Reserved [000001] : Reserved [000010] : TS0.2 selection [000011] : TS0.3 selection [000010] : TS0.4 selection [000101] : TS0.5 selection [000110] : TS0.6 selection [000111] : TS0.7 selection [001000] : Reserved [001001] : Reserved [001010] : Reserved [001011] : Reserved [001100] : Reserved [001101] : Reserved [001110] : Reserved [001111] : Reserved

[010000] : TS1.0 selection [010001] : TS1.1 selection [010010] : TS1.2 selection [010011] : TS1.3 selection [010010] : TS1.4 selection [010101] : TS1.5 selection [010110] : TS1.6 selection [010111] : TS1.7 selection [011000] : TS1.8 selection [011001] : TS1.9 selection [011010] : Reserved [011011] : Reserved [011100] : Reserved [011101] : TS1.13 selection [011110] : TS1.14 selection [011111] : Reserved

[100000] : Reserved [100001] : Reserved [100010] : Reserved [100011] : TS2.3 selection [100010] : TS2.4 selection [100101] : Reserved [100110] : Reserved [100111] : Reserved [101000] : Reserved [101001] : TS1.9 selection [101010] : Reserved [101011] : Reserved [101100] : TS1.12 selection [101101] : Reserved [101110] : Reserved [101111] : Reserved

[110000] : Reserved [110001] : Reserved [110010] : Reserved [110011] : TS4.3 selection [110010] : TS4.4 selection [110101] : Reserved [110110] : Reserved [110111] : Reserved [111000] : Reserved [111001] : Reserved [111010] : Reserved [111011] : TS4.11 selection [111100] : TS4.12 selection [111101] : Reserved [111110] : Reserved [111111] : Reserved



Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TSCEN0.7 TSCEN0.6 TSCEN0.5 TSCEN0.4 TSCEN0.3 TSCEN0.2 Reserved Reserved


TSCAP0EN (022Ch) : Touch Sensor Test Capacitor Enable Register

Reserved TSCEN1.14

TSCEN1.13 Reserved Reserved Reserved TSCEN1.9 TSCEN1.8 TSCEN1.7 TSCEN1.6 TSCEN1.5 TSCEN1.4 TSCEN1.3 TSCEN1.2 TSCEN1.1 TSCEN1.0


TSCAP1EN (022Dh) : Touch Sensor Test Capacitor Enable Register

Reserved Reserved Reserved TSCEN2.12 Reserved Reserved TSCEN2.9 Reserved Reserved Reserved Reserved TSCEN2.4 TSCEN2.3 Reserved Reserved Reserved


TSCAP2EN (022Eh) : Touch Sensor Test Capacitor Enable Register

- - - TSCEN4.12

TSCEN4.11 Reserved Reserved Reserved Reserved Reserved Reserved TSCEN4.4 TSCEN4.3 Reserved Reserved Reserved

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

TSCAP4EN (022Fh) : Touch Sensor Test Capacitor Enable Register



- - - - - - - - DLY7EN DLY6EN DLY5EN DLY4EN DLY3EN DLY2EN DLY1EN DLY0EN

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

TSDLYOPT (0231h) : Touch Sensing Delay Option Mask Register

DLY7EN : Sensor Discharging/Charging Delay option 7 enable DLY6EN : Sensor Discharging/Charging Delay option 6 enable

… DLY1EN : Sensor Discharging/Charging Delay option 1 enable DLY0EN : Sensor Discharging/Charging Delay option 0 enable

- - - - - - - - VIH7EN VIH6EN VIH5EN VIH4EN VIH3EN VIH2EN VIH1EN VIH0EN

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

TSVIHOPT (0232h) : Touch Sensing Comparator VIH Option Mask Register, The register is dependent on VIMASK[1] flag of VICOMPCFG SFR.

VIH7EN : Sensor Comparator VIH option 7 enable VIH6EN : Sensor Comparator VIH option 6 enable

… VIH1EN : Sensor Comparator VIH option 1 enable VIH0EN : Sensor Comparator VIH option 0 enable

TSVIHOPT[7:0] VIH value 00000001 1.30V (0.936V) 00000010 1.40V (1.010V)

00000100 1.50V (1.080V) 00001000 1.60V (1.150V) 00010000 1.70V (1.220V) 00100000 1.80V (1.300V) 01000000 1.90V (1.370V) 10000000 2.00V (1.440V)

Ex) when VIH is sweep condition by VIMAK[1] and TSVIHOPT = 00000011, TS operation is enable VIH= 1.3V(0.936V) first And then enable VIH=1.4V(1.010V) option next

TSDLYOPT[7:0] delay value(ns) 00000001 5 00000010 20 00000100 35 00001000 50 00010000 65 00100000 80 01000000 95 10000000 110

Ex) if TSDLYOPT have multi-options at the same time as TSDLYOPT = 00000011, TS operation is enable delay value = 5 ns first And then enable delay value 20 ns option next



- - - - - - - - VIL7EN VIL6EN VIL5EN VIL4EN VIL3EN VIL2EN VIL1EN VIL0EN

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

TSVILOPT (0233h) : Touch Sensing Comparator VIL Option Mask Register, The register is dependent on VIMASK[0] flag of VICOMPCFG SFR.

VIL7EN : Sensor Comparator VIL option 7 enable VIL6EN : Sensor Comparator VIL option 6 enable

… VIL1EN : Sensor Comparator VIL option 1 enable VIL0EN : Sensor Comparator VIL option 0 enable

- - - - - - - - INTV7 INTV6 INTV5 INTV4 INTV3 INTV2 INTV1 INTV0

R(0) R(0) R(0) R(0) R(0) R(0) R(0) R(0)

TSSSINTV(0234h) : Touch Sensing Interval Register, It means the interval times between the end and the start of touch sensing in auto-running mode

INTV[7:0] : Touch Sensing interval (clock cycles)

TSVILOPT[7:0] VIL value 00000001 1.10V (0.792V) 00000010 1.00V (0.720V) 00000100 0.90V (0.648V) 00001000 0.80V (0.576V) 00010000 0.70V (0.504V) 00100000 0.60V (0.432V) 01000000 0.50V (0.360V) 10000000 0.40V (0.288V)

Ex) when VIL is sweep condition by VIMAK[0] and TSVILOPT = 00000011, TS operation is enable VIL= 1.10V(0.792V) first And then enable VIL= 0,40(0.288V) option next


6.15. ADC (Analog-to-Digital Converter) (1 of 6)

Differential Mode : Max. 21-channel , OPAMP + 12-bit ADC (SAR Type), LDO25 = 1.8 V only , input range 0~1.8 V

Single Ended Mode : Max. 14-channel , 12-bit ADC, LDO25 = 1.8 ~3.3 V, input range 0~ LDO25 V Max. 104ksps(samples per sec.) @ FADC = 24MHz & 3V. (Max. 52ksps @ FADC = 5MHz & 3V)

- - - - - - - - - - - - AD_EN AD_REQ AD_END ADIF

R/W(0) R/W(0) R/W(1) R/W(0)

ADCON (0386h) : ADC Control Register

AD_EN : ADC Ready Enable AD_REQ : ADC Start. Cleared by H/W when AD_END goes to 1 from 0. AD_END : Current ADC Status. 0 = ADC is running now. User must check the ADCF instead of AD_END. ADCF : ADC Interrupt Flag. Must be cleared by S/W.

- - - - - - - - - - - - ADCLK_EN ADCDIV2 ADCDIV1 ADCDIV0

R/W(0) R/W(0) R/W(0) R/W(0)

ADCFG (0387h) : ADC Configuration Register

ADCLK_EN : ADC Clock Enable ADCDIV[2:0] : ADC Clock Selection. [000] : FOSC / 256 [001] : FOSC / 128 [010] : FOSC / 64 [011] : FOSC / 32 [100] : FOSC / 16 [101] : FOSC / 8 [110] : FOSC / 4 [111] : FOSC / 2



- ADCSEL14 ADCSEL13 ADCSEL12 ADCSEL11 ADCSEL10 ADCSEL9 ADCSEL8 - ADCSEL6 ADCSEL5 ADCSEL4 ADCSEL3 ADCSEL2 ADCSEL1 ADCSEL0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ADCSEL (0388h) : Differential ADC Channel Selection Register, It must be used as pair of VP and VN, VP number is 1 less than VN number

ADCSEL[6:0] : ADC channel selection . when user use differential ADC, LCDC, Touch or single ADC must not be used at the same port ADCSEL[6:4] Port Number(0,1,2,,4) ADCSEL[3:0] OPAMP VP Channel Number [0000000] : ADC0.00 channel selection. [0000001] : Reserved [0000010] : Reserved [0000011] : Reserved [0000100] : Reserved [0000101] : Reserved [0000110] : Reserved [0000111] : Reserved [0001000] : ADC0.08 channel selection. [0001001] : Reserved [0001010] : ADC0.10 channel selection. [0001011] : Reserved [0001100] : ADC0.12 channel selection. [0001101] : Reserved [0001110] : ADC0.14channel selection. [0001111] : Reserved

[0010000] : Reserved [0010001] : Reserved [0010010] : Reserved [0010011] : Reserved [0010100] : Reserved [0010101] : Reserved [0010110] : Reserved [0010111] : Reserved [0011000] : Reserved [0011001] : Reserved [0011010] : ADC1.10 channel selection. [0011011] : Reserved [0011100] : ADC1.12 channel selection. [0011101] : Reserved [0011110] : ADC1.14channel selection. [0011111] : Reserved

ADCSEL[14:8] : ADC channel selection. when user use differential ADC, LCDC, Touch or single ADC must not be used at the same port ADCSEL[14:12] Port Number(0,1,2,,4) ADCSEL[11:8] OPAMP VN Channel Number [0000000] : Reserved [0000001] : ADC0.00 channel selection. [0000010] : Reserved [0000011] : Reserved [0000100] : Reserved [0000101] : Reserved [0000110] : Reserved [0000111] : Reserved [0001000] : Reserved [0001001] : ADC0.09 channel selection. [0001010] : Reserved [0001011] : ADC0.11 channel selection. [0001100] : Reserved [0001101] : ADC0.13 channel selection. [0001110] : Reserved [0001111] : ADC0.15 channel selection.

[0100000] : ADC2.00 channel selection. [0100001] : Reserved [0100010] : Reserved [0100011] : Reserved [0100100] : Reserved [0100101] : ADC2.05 channel selection. [0100110] : Reserved [0100111] : ADC2.07 channel selection. [0101000] : Reserved [0101001] : ADC2.09channel selection. [0101010] : Reserved [0101011] : ADC2.11 channel selection. [0101100] : Reserved [0101101] : ADC2.13channel selection. [0101110] : Reserved [0101111] : ADC2.15 channel selection.

[1000000] : Reserved [1000001] : ADC4.01 channel selection. [1000010] : Reserved [1000011] : ADC4.03 channel selection. [1000100] : Reserved [1000101] : ADC4.05 channel selection. [1000110] : Reserved [1000111] : ADC4.07 channel selection. [1001000] : Reserved [1001001] : ADC4.09channel selection. [1001010] : Reserved [1001011] : ADC4.11 channel selection. [1001100] : Reserved [1001101] : Reserved [1001110] : Reserved [1001111] : Reserved

[0010000] : Reserved [0010001] : Reserved [0010010] : Reserved [0010011] : Reserved [0010100] : Reserved [0010101] : Reserved [0010110] : Reserved [0010111] : Reserved [0011000] : Reserved [0011001] : Reserved [0011010] : Reserved [0011011] : ADC1.11channel selection. [0011100] : Reserved [0011101] : ADC1.13 channel selection. [0011110] : Reserved [0011111] : ADC1.15channel selection.

[0100000] : Reserved [0100001] : ADC2.01 channel selection. [0100010] : Reserved [0100011] : Reserved [0100100] : Reserved [0100101] : Reserved [0100110] : ADC2.06 channel selection. [0100111] : Reserved [0101000] : ADC2.08channel selection. [0101001] : Reserved [0101010] : ADC2.10 channel selection. [0101011] : Reserved [0101100] : ADC2.12 channel selection. [0101101] : Reserved [0101110] : ADC2.14channel selection. [0101111] : Reserved

[1000000] : ADC4.00 channel selection. [1000001] : Reserved [1000010] : ADC4.02 channel selection. [1000011] : Reserved [1000100] : ADC4.04 channel selection. [1000101] : Reserved [1000110] : ADC4.06 channel selection. [1000111] : Reserved [1001000] : ADC4.08 channel selection. [1001001] : Reserved [1001010] : ADC4.10 channel selection. [1001011] : Reserved [1001100] : ADC4.12 channel selection. [1001101] : Reserved [1001110] : Reserved [1001111] : Reserved



- - - - - - - - - ADCSEL6 ADCSEL5 ADCSEL4 ADCSEL3 ADCSEL2 ADCSEL1 ADCSEL0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ADCSEL2 (038Ah) : Single ended ADC Channel Selection Register

- - - - ADCR11 ADCR10 ADCR9 ADCR8 ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ADCR (0389h) : ADC Result Register

ADCR : ADC Result (12-bit Data)

ADCSEL[6:0] : ADC channel selection. when user use single ADC, LCDC, Touch or differential ADC must not be used at the same port ADCSEL[6:4] Port Number(0,1,2,,4) ADCSEL[3:0] OPAMP VP Channel Number [0000000] : Reserved [0000001] : Reserved [0000010] : Reserved [0000011] : Reserved [0000100] : Reserved [0000101] : Reserved [0000110] : Reserved [0000111] : Reserved [0001000] : Reserved [0001001] : Reserved [0001010] : ADC0.10 channel selection. [0001011] : ADC0.11 channel selection. [0001100] : ADC0.12 channel selection. [0001101] : ADC0.13 channel selection. [0001110] : Reserved [0001111] : Reserved

[0010000] : Reserved [0010001] : Reserved [0010010] : Reserved [0010011] : Reserved [0010100] : Reserved [0010101] : Reserved [0010110] : Reserved [0010111] : Reserved [0011000] : Reserved [0011001] : Reserved [0011010] : Reserved [0011011] : Reserved [0011100] : Reserved [0011101] : Reserved [0011110] : Reserved [0011111] : Reserved

[0100000] : Reserved [0100001] : Reserved [0100010] : ADC2.02 channel selection. [0100011] : ADC2.03 channel selection. [0100100] : Reserved [0100101] : Reserved [0100110] : Reserved [0100111] : Reserved [0101000] : Reserved [0101001] : Reserved [0101010] : ADC2.10channel selection. [0101011] : ADC2.11channel selection. [0101100] : Reserved [0101101] : Reserved [0101110] : Reserved [0101111] : Reserved

[1000000] : Reserved [1000001] : Reserved [1000010] : Reserved [1000011] : Reserved [1000100] : Reserved [1000101] : ADC4.05 channel selection. [1000110] : ADC4.06 channel selection. [1000111] : ADC4.07 channel selection. [1001000] : ADC4.08 channel selection. [1001001] : ADC4.09channel selection. [1001010] : ADC4.10 channel selection. [1001011] : Reserved [1001100] : Reserved [1001101] : Reserved [1001110] : Reserved [1001111] : Reserved



CEN0.15 CEN0.14 CEN0.13 CEN0.12 CEN0.11 CEN0.10 CEN0.9 CEN0.8 CEN0.7 CEN0.6 CEN0.5 CEN0.4 CEN0.3 CEN0.2 CEN0.1 CEN0.0


IOENB0 (0380h) : ADC Channel Enable Register (Port 0)

1 = ADC0 Channel ON / 0 = ADC0 Channel OFF (Default)







- CEN4.14 CEN4.13 CEN4.12 CEN4.11 CEN4.10 CEN4.9 CEN4.8 CEN4.7 CEN4.6 CEN4.5 CEN4.4 CEN4.3 CEN4.2 CEN4.1 CEN4.0





- - TRIM13 TRIM12 TRIM11 TRIM10 TRIM9 TRIM8 TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0


OPAMP_TRIM (038Bh) : OPAMP Trim Register

OPAMP Gain TRIM Value Register

OPAMP is designed for 1.8 V only, so user must trim LDO_25 to 1.8 V for differential ADC mode

0

5

10

15

20

25

30

1 3 5 7 9 11 13 15 17 19 21 23

Gain Trimming

Ideal Gain

Real Gain



OPAMP Gain TRIM Value Register

- - - - - - - - - - - - - - OPAMP_STAB

OPAMP_EN

R (0) R/W(0)

OPAMP_CON(038Ch) : OPAMP Control Register

- - - - - - STAB_CNT9

STAB_CNT8

STAB_CNT7

STAB_CNT6

STAB_CNT5

STAB_CNT4

STAB_CNT3

STAB_CNT2

STAB_CNT1

STAB_CNT0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1)

OPAMP_STAB_CNT (038Dh) : OPAMP Stable Setup Time Period Counter Register

OPAMP_EN : OPAMP Enable ( 0 : disable , 1 : enable) OPAMP_STAB : OPAMP Stable Indicator ( 0 : unstable, 1: stable)

SATB_CNT[9:0] : Stable time (> 20 us) after OPAMP enable


6.15. ADC (Block Diagram)

Analog MUX

ADC0.xx (P0.xx)

ADC1.xx (P1.xx)

ADC4.xx (P4.xx)

Successive Approximation

Register

FADC

AD_END

ADCIF

ADC Interrupt Flag

SAR[11:0]

ADCR

D/A Converter

Control Circuit

Clock Divide

Internal RING Clock FOSC

Analog Comparator

AVREF (= VDDIO)

VSS

ADCSEL2[6:0] AD_EN AD_REQ

ADCON.3 ADCON.2 ADCFG[2:0]

ADCON.1

ADCON.0

ADCDIV2

ADCDIV1

ADCDIV0

ADC4.xx (P4.xx)

ADCLK_EN

ADCFG.3

9 8 7 6 5 4 3 2 11 10 1 0

Analog MUX ADC1.xx

(P1.xx)

ADC0.xx (P0.xx)

OP AMP

VP

VN

ADCSEL[6:0]


Hold Time 11 10 9 8 7 4 3 2 1 0 Setup Time

6.15. ADC : Conversion Timing

AD_EN : ADC Block Enable Signal. Set or Cleared by S/W. AD_REQ : ADC Conversion Request Start Bit. Set by S/W and Cleared by H/W. This bit must be set at each sample conversion. AD_END : Set or Cleared by H/W. Clear when Conversion started. Set when Conversion ended. ADCIF : ADC Interrupt Flag. Set by H/W and Cleared by S/W. User should clear ADCIF bit in ADC interrupt routine. User must check the ADCIF flag instead of AD_END.

AD_EN

AD_REQ

ADCF

AD_END

Set by S/W

Cleared by H/W

16TADC (8TADC) x 12 bits = 96TADC 8TADC

120TADC

8TADC

Valid Bit

Set by H/W

Set by H/W

ADC Interrupt

Cleared by H/W Set by S/W

System Clock (FSYS)

Divide (ADCDIV[2:1]=111)

FADC TADC

(1/FADC) 1 Sample

Conversion Time

48MHz @ 3V FOSC/2 24MHz 41.66ns 5.0us

24MHz @ 3V FOSC/2 12MHz 83.33ns 10.0us

[An Example of ADC Conversion Table]

. . .


6.16. I2S: Feature

Inter-IC Sound Bus that is a serial link for transmitting stereo audio between devices in a system.

The I2S bus was invented by Philips Semiconductor, but is now widely used by several semiconductor manufacturers.

Format 1~16bit I2S format / MSB-justified format

Sampling Frequency 16/32/48fs

FIFO for transmit and receive 64 word entries for left and right channel

Master only Notice

All 64 word must be filled before transmission. If not, empty interrupt can be occurred.

left right

64

16bit


6.16. I2S: Clock & Timing

/2

CLKRATIO[1:0]]

/4

/8

/16

I2S_MCK Main Clock


6.16. I2S: Registers (1 of 4)

RXRATIO7

RXRATIO6

RXRATIO5

RXRATIO4

RXRATIO3

RXRATIO2

RXRATIO1

RXRATIO0 RXRES4 RXRES3 RXRES2 RXRES1 RXRES0 RXFORM

AT RXSWAP RXEN


RXCON0 (03A0h) : I2S RX Control Register 0

- - - - - - - - - - - - - Reserved CLK_RATIO1

CLK_RATIO0

R/W(0) R/W(0) R/W(0)

RXCON1 (03A1h) : I2S RX Control Register 1

- - - - - - - - - - - - RX_HF_INT

RX_F_INT

RX_HF_MASK

RX_F_MASK

R(0) R(0) R/W(0) R/W(0)

RXINT (03A2h) : I2S RX Interrupt Control Register

RX_HF_INT : RX Half Full Indicator ( set by logic , clear by S/W) RX_F_INT : RX Full Indicator (set by logic, clear by S/W) RX_HF_MASK : RX Half Full Interrupt enable (0 : Interrupt disable , 1 : Interrupt enable) RX_F_MASK : RX Full Interrupt enable ( 0 : Interrupt disable, 1 : Interrupt enable)

RXEN : Receiver Enable ( 0 : Disable , 1 : Enable) RXSWAP : Position of Left Channel ( 0 : Left channel is stored on even addresses, 1 : Left channel is stored on odd addresses) RXFORMAT : Data Format ( 0 : I2S format, 1 : MSB-justified format) RXRES[4:0] : TX Sample Data Resolution Number of bits (RES + 1) that are stored in each audio word in the sample buffer. If the received signal has fewer bits than set by RES, zero padding of LSB’s is used. If the received signal has more bits than set by RES, LSB’s are truncated. Valid range is 1 to 15. RXRATIO[7:0]: Clock Divider for the Receive Frequency , The ratio between bit clock and sampling frequency.

CLK_RATIO[1:0] : Clock Divider for Master Clock (00 :1/2 , 01 : 1/4 , 10 : 1/8 , 11 : 1/16)



RXDAT15 RXDAT14 RXDAT13 RXDAT12 RXDAT11 RXDAT10 RXDAT9 RXDAT8 RXDAT7 RXDAT6 RXDAT5 RXDAT4 RXDAT3 RXDAT2 RXDAT1 RXDAT0


RXDATA (03A3h) : I2S RX Data Register

RXDAT[15:0] : Receive Audio Data

- - - - - - - - - - RXADDR5

RXADDR4

RXADDR3

RXADDR2

RXADDR1

RXADDR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

RXADDR (03A4h) : I2S RX FIFO Address Register

RXADDR[5:0] : Receive FIFO Initial Address



TXRATIO7

TXRATIO6

TXRATIO5

TXRATIO4

TXRATIO3

TXRATIO2

TXRATIO1

TXRATIO0 TXRES4 TXRES3 TXRES2 TXRES1 TXRES0 TXFORM

AT TXSWAP TXEN


TXCON0 (03A8h) : I2S TX Control Register 0

TXEN : Tansmitter Enable ( 0 : Disable , 1 : Enable) TXSWAP : Position of Left Channel ( 0 : Left channel is stored on even addresses, 1 : Left channel is stored on odd addresses) TXFORMAT : Data Format ( 0 : I2S format, 1 : MSB-justified format) TXRES[4:0] : TX Sample Data Resolution Number of bits (RES + 1) that are stored in each audio word in the sample buffer. If the received signal has fewer bits than set by RES, zero padding of LSB’s is used. If the received signal has more bits than set by RES, LSB’s are truncated. Valid range is 1 to 15. TXRATIO[7:0]: Clock Divider for the Transmit Frequency , The ratio between bit clock and sampling frequency.

- - - - - - - - - - - - - Reserved CLK_RATIO1

CLK_RATIO0

R/W(0) R/W(0) R/W(0)

TXCON1 (03A9h) : I2S TX Control Register 1

CLK_RATIO[1:0] : Clock Divider for Master Clock (00 :1/2 , 01 : 1/4 , 10 : 1/8 , 11 : 1/16)

- - - - - - - - - - - - TX_HF_INT

TX_F_INT

TX_HF_MASK

TX_F_MASK

R/W(0) R/W(0) R/W(0) R/W(0)

TXINT (03AAh) : I2S TX Interrupt Control Register

TX_HF_INT : TX Half Full Indicator ( set by logic , clear by S/W) TX_F_INT : TX Full Indicator (set by logic, clear by S/W) TX_HF_MASK : TX Half Full Interrupt enable (0 : Interrupt disable , 1 : Interrupt enable) TX_F_MASK : TX Full Interrupt enable ( 0 : Interrupt disable, 1 : Interrupt enable)



TXDAT15 TXDAT14 TXDAT13 TXDAT12 TXDAT11 TXDAT10 TXDAT9 TXDAT8 TXDAT7 TXDAT6 TXDAT5 TXDAT4 TXDAT3 TXDAT2 TXDAT1 TXDAT0


TXDATA (03ABh) : I2S TX Data Register

TXDAT[15:0] : Transmit Audio Data

- - - - - - - - - - TXADDR5

TXADDR4

TXADDR3

TXADDR2

TXADDR1

TXADDR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

TXADDR (03ACh) : I2S TX FIFO Address Register

TXADDR[5:0] : Transmit FIFO Initial Address

IOEN1 IOEN0

R/W(0) R/W(0)

TXCON0 (03ADh) : I2S IO Enable Register

IOEN0 : 1st IO Path Enable (0 : Disable, 1 : Enable) IOEN1 : 2nd IO Path Enable (0 : Disable, 1 : Enable)


6.16. I2S: Setting Example

Fs Master clock Data width RES RATIO

32KHz

256Fs 8bit 7 15 (=256/8/2-1)

16bit 15 7 (=256/16/2-1)

384Fs 8bit 7 23 (=384/8/2-1)

16bit 15 11 (=384/16/2-1)

512Fs 8bit 7 31 (=512/8/2-1)

16bit 15 15 (=512/16/2-1)

44.1KHz

256Fs 8bit 7 15 (=256/8/2-1)

16bit 15 7 (=256/16/2-1)

384Fs 8bit 7 23 (=384/8/2-1)

16bit 15 11 (=384/16/2-1)

512Fs 8bit 7 31 (=512/8/2-1)

16bit 15 15 (=512/16/2-1)

48KHz

256Fs 8bit 7 15 (=256/8/2-1)

16bit 15 7 (=256/16/2-1)

384Fs 8bit 7 23 (=384/8/2-1)

16bit 15 11 (=384/16/2-1)

512Fs 8bit 7 31 (=512/8/2-1)

16bit 15 15 (=512/16/2-1)


6.17. LCDC: Data Frame

SEG

0

SEG

1

SEG

2

SEG

3

SEG

4

SEG

5

SEG

6

SEG

7

… SEG

26

SEG

27

SEG

28

SEG

29

SEG

30

SEG

31

SEG

32

SEG

33

SEG

34

COM0 b0 b4 b0 b4 b0 b4 b0 b4

…

b0 b4 b0 b4 b0 b4 b0 b4 b0 x

COM1 b1 b5 b1 b5 b1 b5 b1 b5 b1 b5 b1 b5 b1 b5 b1 b5 b1 x

COM2 b2 b6 b2 b6 b2 b6 b2 b6 b2 b6 b2 b6 b2 b6 b2 b6 b2 x

COM3 b3 b7 b3 b7 b3 b7 b3 b7 b3 b7 b3 b7 b3 b7 b3 b7 b3

ADDR 281H 282H … 287H 288H 289H

SEG 32 x 4 COM LCDC buffer Bias : static ~ 1/3 Duty : static ~ 1/4 LCD clock : 64 Hz ~ 4 KHz


6.17. LCDC: Timing at each mode

Static

1/2 duty , 1/2 bias

1/3 duty , 1/2 bias

1/3 duty , 1/3 bias

1/4 duty , 1/3 bias Duty is extended to 1/4 , wave form is same as 1/3 duty , 1/3 bias


6.17. LCDC: Registers (1 of 7)

- - - - - - - - DUTY1 DUTY0 BIAS1 BIAS0 CLKSEL3 CLKSEL2 CLKSEL1 CLKSEL0


LCDC_MODE (0280h) : LCDC MODE Control Register

CLKSEL[3:0] : LCD Clock Selection , Range 64 Hz ~ 4 KHz , selected clock = main clock / [2^(21-CLKSEL)] ( 0000 : clock off , 0001 : 1/[2^20], … 1111 : 1/[2^6] ) BIAS [1:0] : Bias Selection (00 : static, 01: 1/2 bias, 10 : 1/3 bias , 11 : Reserved) DUTY[1:0] : Duty Selection (00 : static, 01 : 1/2 duty, 10 : 1/3 duty, 11 : 1/4 duty

In case of Main clock 32 Mhz

static 1/2duty 1/3duty 1/4duty

static × × ×

1/2bias × ×

1/3bias × (×)

0000 LCDoff 0001 32Hz 0010 64Hz 0011 128Hz

0100 256Hz 0101 512Hz 0110 1KHz 0111 2KHz

1000 4KHz 1001 8KHz 1010 16KHz 1011 32KHz

1100 64KHz 1101 128KHz 1110 256KHz 1111 512KHz

Duty and Bias support



REG15 REG14 REG13 REG12 REG11 REG10 REG9 REG8 REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0


LCDC_SEG03_00 (0281h) : LCDC SE 3 to 0 Register

REG[3:0] : SEG0 , REG[7:4] : SEG1 , REG [11:8] : SEG2 , REG[15:12] : SEG4



LCDC_SEG07_04 (0282h) : LCDC SEG 7 to 3 Register














LCDC_SEG19_16 (0285h) : LCDC SEG 19 to 16 Reigster










- - - - REG17 REG17 REG17 REG17 REG16 REG16 REG16 REG16 REG16 REG16 REG16 REG16

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)






REG[3:0] : SEG32 , REG[7:4] : SEG33 , REG [11:8] : SEG34



- - - - - - - - 0 VLCD_GEN_EN

CONTRAST3

CONTRAST2

CONTRAST1

CONTRAST0

CONTRAST_EN

INT_VLCD_EN


LCDC_CON(028Ah) : LCDC Gen. Control Register

INT_VLCD_EN : Internal VLCD Enable (0 : Disable , 1 : Enable) CONTRAST_EN : Contrast Enable (0 : Disable , 1 : Enable) CONTRAST_ST[3:0]: Contrast Value VLCD_GEN_EN : VLCD Generator Enable (0 : Disable , 1 : Enable)

INT_VLCD_EN

VLCD_GEN_EN LVDD VLCD3 VLCD3 VLCD3 Remarks

IN IN IN/OUT OUT OUT OUT Items Result

0 X X Float Float Float External Input

1 0 VDD V3 V2 V1 External Input

1 1 VDD V3 V2 V1 Internal

1 0 VSS VSS VSS VSS Off

VLCD_GEN

HALF_BIAS_EN

LVDD

INT_VLCD_EN

CONTRAST_EN

CONTRAST[3:0] VLCD2

VLCD1

VLCD_GEN_EN

VLCD3

VLCD_GEN_EN_B

VLCD3

CONTRAST[3:0]

HALF_BIAS_EN

R

R

R

VLCD2

VLCD1

LVDD

INT_VLCD_EN

CONTRAST_EN

2R

CONTRAST_EN=1 ; V4V3

CONTRAST_EN=0 ; LVDDV3

V2

V4

V1

V3

HALF_BIAS_EN=1 ; V2=V1

VLCD_GEN_EN=0 ; LVDD Floating



Contrast_ST[3:0] VLCD3 전압

0000 2.564

0001 2.61

0010 2.656

0011 2.702

0100 2.748

0101 2.794

0110 2.84

0111 2.886

1000 2.932

1001 2.978

1010 3.024

1011 3.07

1100 3.116

1101 3.162

1110 3.208

1111 3.254



SEG_IO_EN15

SEG_IO_EN14

SEG_IO_EN13

SEG_IO_EN12

SEG_IO_EN11

SEG_IO_EN10

SEG_IO_EN9

SEG_IO_EN8

SEG_IO_EN7

SEG_IO_EN6

SEG_IO_EN5

SEG_IO_EN4

SEG_IO_EN3

SEG_IO_EN2

SEG_IO_EN1

SEG_IO_EN0


LCDC_SEG_IO_EN_L (028Ch) : LCDC SEG IO Enable Register

SEG_IO_EN[15:0] : SEG Output Enable (0: Disable , 1 : Enable) when user use LCDC , ADC or Touch must not be used at the same port

SEG_IO_EN0 : SEG0 (P2.15) SEG_IO_EN1 : SEG1 (P4.00) SEG_IO_EN2 : SEG2 (P4.01) SEG_IO_EN3 : SEG3 (P4.02) SEG_IO_EN4 : SEG4 (P0.07) SEG_IO_EN5 : SEG5 (P1.00) SEG_IO_EN6 : SEG6 (P1.01) SEG_IO_EN7 : SEG7 (P1.02)

SEG_IO_EN31

SEG_IO_EN30

SEG_IO_EN29

SEG_IO_EN28

SEG_IO_EN27

SEG_IO_EN26

SEG_IO_EN25

SEG_IO_EN24

SEG_IO_EN23

SEG_IO_EN22

SEG_IO_EN21

SEG_IO_EN20

SEG_IO_EN19

SEG_IO_EN18

SEG_IO_EN17

SEG_IO_EN16


LCDC_SEG_IO_EN_H (028Dh) : LCDC SEG IO Enable Register


SEG_IO_EN[31:16] : SEG Output Enable (0: Disable , 1 : Enable) when user use LCDC , ADC or Touch must not be used at the same port





- - - - - - - - - - - - COM_IO_EN3

COM_IO_EN2

COM_IO_EN1

COM_IO_EN0

R/W(0) R/W(0) R/W(0) R/W(0)

LCDC_COM_IO_EN (028Eh) : LCDC COM IO Enable Register

- - - - - - - - - - - - EXTVLCD_EN3

EXTVLCD_EN2

EXTVLCD_EN1

EXTVLCD_EN0

R/W(0) R/W(0) R/W(0) R/W(0)

LCDC_EXTVLCD_EN (028Fh) : LCDC EXTVLCD Enable Register

COM_IO_EN[3:0] : COM Output Enable (0: Disable , 1 : Enable)

COM_IO_EN0 : COM0 (P0.03) COM_IO_EN1 : COM1 (P0.04) , If duty is static, this is SEG34 COM_IO_EN2 : COM2 (P0.05) , If duty is static or 1/2, this is SEG33 COM_IO_EN3 : COM3 (P0.06) , If duty is static, 1/2 or 1/3, this is SEG32

EXTVLCD_EN[3:0] : External VLCD input IO Enable (0: Disable , 1 : Enable) This is used when LCDC_CON.INT_VLCD_EN = 0.

EXTVLCD_EN0 : VLCD1 (P1.15) EXTVLCD_EN1 : VLCD2 (P2.00) EXTVLCD_EN2 : VLCD3 (P2.01) EXTVLCD_EN3 : LVDD (P2.02)


6.18. RTC: Registers (1 of 8)

- - - - - - - - - - - - - - - RTC_EN

R/W(0)

RTC_EN(03C0h) : RTC Enable Control Register

RTC_EN : RTC Enable (0 : Disable, 1 : Enable)

- - - - - - - - - - - SQWE SQW_SEL3

SQW_SEL2

SQW_SEL1

SQW_SEL0


SQW (03C1h) : SQW Control Register

SQWE : Square Wave Output Enable (0 : Disable, 1 : Enable) SQW_SEL[3:0]: Square Wave Division Ratio



- - - - CAL_EN CAL_SIGN

CAL_VALUE_19

CAL_VALUE_18

CAL_VALUE_17

CAL_VALUE_16

CAL_VALUE_15

CAL_VALUE_14

CAL_VALUE_13

CAL_VALUE_12

CAL_VALUE_11

CAL_VALUE_10


CALIBRATION_H (3C2h) : Calibration Value Register

CAL_EN : Calibration Enable (0 : Disable, 1 : Enable) CAL_SIGN : Calibration Sign Value (0 : negative , 1 : positive) 0 : Lengthen Period, 1 : Shorten Period CAL_VALUE[19:10] : Calibration Value High

+1ppm : CAL_VLAUE = 1000000 +2ppm : CAL_VALUE = 1000000/2 +3ppm : CAL_VALUE = 1000000/3

- - - - - - CAL_VALUE_9

CAL_VALUE_8

CAL_VALUE_7

CAL_VALUE_6

CAL_VALUE_5

CAL_VALUE_4

CAL_VALUE_3

CAL_VALUE_2

CAL_VALUE_1

CAL_VALUE_0


CALIBRATION_L (3C3h) : Calibration Value Register

CAL_VALUE[9:0] : Calibration Value Low

- - - - - - - - - - - - - - CEN_EN CEN_VALUE

R/W(0) R/W(0)

WR_CENTURY (03C4Fh) : Century Write Register

CEN_EN : Century Enable (0 : Disable, 1: Enable) CEN_VALUE : Century Value



- - - - - - - - - W_YEAR6

W_YEAR5

W_YEAR4

W_YEAR3

W_YEAR2

W_YEAR1

W_YEAR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_YEAR(03C5h) : Year Write Register

W_YEAR[6:0] : Year Write Value, 0~ 99

- - - - - - - - - - - - W_MONTH3

W_MONTH2

W_MONTH1

W_MONTH0

R/W(0) R/W(0) R/W(0) R/W(0)

WR_MONTH (03C6h) : Month Write Register

W_MONTH[3:0] : Month Write Value , 1~12

- - - - - - - - - - - W_DATE4

W_DATE3

W_DATE2

W_DATE1

W_DATE0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_DATE (3C7h) : Date Write Register

W_DATE[4:0] : Date Write Value, 1~31

- - - - - - - - - - - W_HOUR4

W_HOUR3

W_HOUR2

W_HOUR1

W_HOUR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_HOUR (3C8h) : Calibration Value Register

W_HOUR[4:0] : Hour Write Value, 0~23

- - - - - - - - - - W_MINUTE5

W_MINUTE5

W_MINUTE5

W_MINUTE5

W_MINUTE5

W_MINUTE5

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_MINUTE (03C9Fh) : Minute Write Register

W_MINUTE[5:0] : Minute Write Value, 0~59



- - - - - - - - - - W_SECOND5

W_SECOND4

W_SECOND3

W_SECOND2

W_SECOND1

W_SECOND0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_SECOND(03CAh) : Second Write Register

W_SECOND[5:0] : Second Write Value, 0~59

- - - - - - - - - W_S_SECOND6

W_S_SECOND5

W_S_SECOND4

W_S_SECOND3

W_S_SECOND2

W_S_SECOND1

W_S_SECOND0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

WR_S_SECOND (03CBh) : Sub Second Write Register

W_S_SECOND[6:0] : Sub-Second Write Value , 0~127 , 7.8125 ms base

- - - - - - - - - - - - - - PERIODC_EN

ASYNC_EN

R/W(0) R/W(0)

LOG_MODE (3CCh) : LOG Mode Register

PERIOD_EN : Periodic Log Enable (0 : Disable, 1 : Enable) ASYNC_EN : Async /Sync Log Mode (0 : Async one-shot, 1 : Sync one-shot)

00 : no logging 01 : 7.8125 ms sync one-shot log going @ RTC_LOG_START = 1 1x: periodic sync logging by RTC_LOG_PERIOD_VAL

- - - - - - - - - - - - - - - LOG_START

R/W(0)

LOG_START (3CDh) : LOG Start Register

LOG_START : Logging Start (0 : Async one shot logging, 1 : 7.8125 ms sync one shot logging)

- - - - - - LOG_PERIOD9

LOG_PERIOD8

LOG_PERIOD7

LOG_PERIOD6

LOG_PERIOD5

LOG_PERIOD4

LOG_PERIOD3

LOG_PERIOD2

LOG_PERIOD1

LOG_PERIOD0


LOG_PERIOD (03CEh) : LOG Period Register

LOG_PERIOD[9:0] : 7.8125 ms base, max 8 second



- - - - - - - - - LOG_YEAR6

LOG_YEAR5

LOG_YEAR4

LOG_YEAR3

LOG_YEAR3

LOG_YEAR1

LOG_YEAR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_YEAR(03CFh) : Year LOG Register

LOG_YEAR[6:0] : Year Logging Value , 0~99

- - - - - - - - - - - - LOG_MONTH3

LOG_MONTH2

LOG_MONTH1

LOG_MONTH0

R/W(0) R/W(0) R/W(0) R/W(0)

LOG_MONTH (03D0h) : Month LOG Register

LOG_MONTH[3:0] : Month Logging Value, 1~12

- - - - - - - - - - - LOG_DATE4

LOG_DATE3

LOG_DATE2

LOG_DATE1

LOG_DATE0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_DATE (3D1h) : Date LOG Register

LOG_DATE[4:0] : Date Logging Value, 1~31

- - - - - - - - - - - LOG_HOUR4

LOG_HOUR3

LOG_HOUR2

LOG_HOUR1

LOG_HOUR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_HOUR (3D2h) : Hour LOG Register

LOG_HOUR[4:0] : Hour Logging Value, 0~23

- - - - - - - - - - LOG_MINUTE5

LOG_MINUTE4

LOG_MINUTE3

LOG_MINUTE2

LOG_MINUTE1

LOG_MINUTE0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_MINUTE (03D3Fh) : Minute LOG Register

LOG_MINUTE[5:0] : Minute Logging Value, 0~59



- - - - - - - - - - LOG_SECOND5

LOG_SECOND4

LOG_SECOND3

LOG_SECOND2

LOG_SECOND1

LOG_SECOND0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_SECOND(03D4h) : Second LOG Register

LOG_SECOND[5:0] : Second Logging Value, 0~59

- - - - - - - - - LOG_S_SECOND6

LOG_S_SECOND5

LOG_S_SECOND4

LOG_S_SECOND3

LOG_S_SECOND2

LOG_S_SECOND1

LOG_S_SECOND0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LOG_S_SECOND (03D5h) : Sub Second LOG Register

- - - - - - - - - - - - - - - ALARM_EN

R/W(0)

ALARM_EN (3D6h) : Alarm Enable Register

ALARM_EN : Alarm Enable (0 : Disable, 1 : Enable)

- - - - - - - - - - - ALARM_RPT4

ALARM_RPT3

ALARM_RPT2

ALARM_RPT1

ALARM_RPT0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_REPEAT (3D7h) : Alarm Repeat Register

ALARM_RPT[4:0] : Alarm Repeat Mode

LOG_S_SECOND[6:0] : Sub-Second Logging Value , 0~127 , 7.8125 ms base



- - - - - - - - - - - A_DATE4 A_DATE3 A_DATE2 A_DATE1 A_DATE0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_DATE(03D9h) : Alarm Date Register

A_DATE[4:0] : Alarm Date Value, 1~31

- - - - - - - - - - - A_HOUR4

A_HOUR3

A_HOUR2

A_HOUR1

A_HOUR0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_HOUR (03DAh) : Alarm Hour Register

A_HOUR[4:0] : Alarm Hour Value, 0~23

- - - - - - - - - - A_MINUTE5

A_MINUTE4

A_MINUTE3

A_MINUTE2

A_MINUTE1

A_MINUTE0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_MINUTE (3DBh) : Alarm Minute Register

A_MINUTE[5:0] : Alarm Minute Value, 0~59

- - - - - - - - - - A_SECOND5

A_SECOND4

A_SECOND3

A_SECOND2

A_SECOND1

A_SECOND0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_SECOND (3DCh) : Alarm Second Register

- - - - - - - - - - - - A_MONTH3

A_MONTH2

A_MONTH1

A_MONTH0

R/W(0) R/W(0) R/W(0) R/W(0)

ALARM_MONTH (03D8h) Alarm Month Register

A_MONTH[3:0] : Alarm month Value , 1~12

A_S_SECOND[6:0] : Alarm Sub-Second Value , 0~127 , 7.8125 ms base



- - - - - - - - - - - - Reserved LOG_CLEAR Reserved ALARM_C

LEAR

R/W(0) R/W(0) R/W(0) R/W(0)

INT_CLEAR(03DEh) : Interrupt Clear Register

LOG_CLEAR : Log Interrupt Clear (0 : abort, 1 : clear) ARARM_CLEAR : Alarm Interrupt Clear (0 : abort, 1 : clear)

- - - - - - - - - - LOG_PERIODIC

LOG_SYNC

LOG_ASYNC LOG_F Reserved ALARM_F

R(0) R(0) R(0) R(0) R(0) R(0)

INT STATUS (03DFh) : Interrupt Status Register

LOG_PERIODIC : Periodic mode LOG_SYNC : Sync one-shot mode LOG_ASYNC : Async one-shot mode LOG_F : Log Interrupt Flag ALARM_F : Alarm Interrupt Flag

- - - - - - - - - - - - Reserved LOG Reserved ALARM

R/W(0) R/W(0) R/W(0) R/W(0)

INT_MASK (03DDh) Interrupt Mask Register

LOG : Log Interrupt Mask (0 : Disable, 1: Enable) ALARM : Alarm Interrupt Mask (0 : Disable, 1: Enable)


6.19. UR: Feature

Carrier Generation The carrier frequency is calculated by the following equation. Length of Carrier Signal’s High Phase : tH = CGDH / FCGC Length of Carrier Signal’s Low Phase : tL = CGDL / FCGC Carrier Frequency : FCARR = 1/(tH + tL)

Envelope Generation : 8-bit Mode

Length of Envelope Signal’s High Phase : tEH = EGDH / FEGC Length of Envelope Signal’s Low Phase : tEL = EGDL / FEGC

Envelope Generation : 16-bit Mode Length of Envelope Signal’s High or Low Phase : tEH (tEL) = (EGDH * 256 + EGDL) / FEGC

ECGC

CAOF

tH tL

CGC 0 1 2 CGDH 1 2 …… CGDL …… 1

EEGC

EVOF

tEH tEL

EGC 0 1 2 EGDH 1 2 …… EGDL …… 1

Counter Module for Remote Control Application Generates REM output : modulated or not. Consists of two Counters

• CGC : Carrier Generation Counter (8-bit) • EGC : Envelope Generation Counter (16-bit)

EGC can be used as 8-bit or 16-bit counter Each Counter has two compare data registers. Each Counter can be used independently.


6.19. UR: Registers (1 of 2)

- - - - - - - - - - ECGI ECGC EGCM EEGI EEGC EVDE

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

CGCON (0401h) : Carrier Generator Control Register

- - - - - - - - - - CGIF CAOF - - EGIF EVOF

R(0) R(0) R(0) R(0)

CGSTS (0400h) : Carrier Generator Status Register

CGIF : CGC Interrupt Flag Set by H/W when CGC value matches with CGDL or CGDH. Cleared by H/W when ECGI is cleared by interrupt service routine. CAOF : Carrier Output Status Flag. If CAOF is 1, CGC runs to match CGDH, otherwise CGDL. This flag is toggled automatically and cleared if ECGC is cleared. EGIF : EGC Interrupt Flag Set by H/W when EGC value matches with EGDL or EGDH. Cleared by H/W when EEGI is cleared by interrupt service routine. EVOF : Envelope Output Status Flag. In 8-bit mode, if EVOF is 1, EGC runs to match EGDH, otherwise EGDL.

ECGI : Enable CGC Interrupt ECGC : Enable CGC. CGC is reset when disabled. EGCM : EGC operation Mode [0] = 8-bit counter, [1] = 16-bit counter. EEGI : Enable EGC Interrupt EEGC : Enable EGC. EGC is reset when disabled. EVDE : Envelope Data Enable [0] = S/W can update EVOF directly. REM waveform changes immediately. [1] = H/W automatically toggles EVOF. REM waveform is synchronized to CAOF.


6.19. UR: Registers (2 of 2)

- - - - - - - - CGDL.7 CGDL.6 CGDL.5 CGDL.4 CGDL.3 CGDL.2 CGDL.1 CGDL.0


CGDL (0403h) : CGC Low Data Register

- - - - - - - - REMOE INVREM ECS1 ECS0 EVOE CCS2 CCS1 CCS0


CGCFG (0402h) : Carrier Generator Configuration Register

REMOE : REM output enable to I/O PAD control INVREM : If set, invert REM output waveform. ECS[1:0] : Envelope Counter Clock Frequency (FEGC) Selection. [0,0] = FSYS (System Clock), [0,1] = Reserved, [1,0] = FCGC (CGC clock according to CCS), [1,1] = Carrier frequency EVOE : If set, REM outputs the envelope data without modulation by carrier. CCS[2:0] : Carrier Counter Clock Frequency (FCGC) Selection. FSYS: System clock frequency for peripheral. [0,0,0] = FSYS/1, [0,0,1] = FSYS/2, [0,1,0] = FSYS/3, [0,1,1] = FSYS/4, [1,0,0] = FSYS/6, [1,0,1] = FSYS/8, [1,1,0] = FSYS/12, [1,1,1] = FSYS/16

- - - - - - - - CGDH.7 CGDH.6 CGDH.5 CGDH.4 CGDH.3 CGDH.2 CGDH.1 CGDH.0


CGDH (0404h) : CGC High Data Register

- - - - - - - - EGDL.7 EGDL.6 EGDL.5 EGDL.4 EGDL.3 EGDL.2 EGDL.1 EGDL.0


EGDL (0405h) : EGC Low Data Register

- - - - - - - - EGDH.7 EGDH.6 EGDH.5 EGDH.4 EGDH.3 EGDH.2 EGDH.1 EGDH.0


EGDH (0406h) : EGC High Data Register


6.19. UR: Mode (1 of 3)

Carrier and Envelope Generation with 8-bit EGC Mode (EGCM = 0) If EVOE is 1, REM outputs only the envelope data.

CCS[2:0]

ECGC

CGC

=

FCGC

0 1

CGDL CGDH

ECGC

FCARR

FSYS / 1 FSYS / 2 FSYS / 3 FSYS / 4 FSYS / 6 FSYS / 8 FSYS / 12 FSYS / 16

CGIF

ECGI

ECS[1:0] EEGC =

FEGC

0 1

EGDL EGDH

EEGC FSYS FCGC FCARR

EGIF

EEGI

CAOF

EGC[7:0]

Interrupt

EVOE

INVREM REMOE

REM

EVDE EVOF


6.19. UR: Mode (2 of 3)

Carrier and Envelope Generation with 16-bit EGC Mode (EGCM = 1) During the interrupt routine, a new 16-bit compare value can be written to the compare register (EGDH & EGDL) Notice, however, that a write to EGDL clears the ECMP bit, which temporarily disables the comparator function while these registers

are being updated so an invalid match does not occur. A write to EGDH sets the ECMP bit and re-enables the comparator. For this reason, user software should write to EGDL first, then the EGDH.

CCS[2:0]

ECGC

CGC

=

FCGC

0 1

CGDL CGDH

ECGC

FCARR


CGIF

ECGI

ECS[1:0] EEGC =

FEGC

EGDH,EGDL

EEGC FSYS FCGC FCARR

EGIF

ECGI

CAOF

EGC[15:0]

Interrupt

EVOE

INVREM REMOE

REM

EVDE EVOF

ECMP

1

0

Write to EGDL

EEGC

Write to EGDH

ECMP


6.19. UR: Mode (3 of 3)

Two independent Timer or PWM generator Each counter can run independent to each other. But, they shares the same interrupt vector address. CGC can be used as 8-bit timer or PWM generator (EVOE = 0, EVDE = 0, EVOF = 1). EGC can be used as 8-bit or 16-bit timer or PWM generator (EVOE = 1, EVDE = 1)

CCS[2:0]

ECGC

CGC

=

FCGC

0 1

ECGC

FCARR


CGIF

ECGI

ECS[1:0] EEGC

FEGC

EGDH,EGDL

FSYS FCGC FCARR

EGIF

ECGI

CAOF

EGC[15:0]

Interrupt

ECMP

= 1

0

Write to EGDL

EEGC

Write to EGDH

ECMP

SeJong200 Family

6.20. Interrupt Controller (1 of 10)

Interrupt Sources I2C0, I2C1, SPI, Stop Timer, UART0, UART1, TCS, WDT, TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, ADC, I2S, UR 14 External

Interrupt Sources.

4-level Interrupt Priority

I2SIF ADCIF T4IF T3IF T2IF T1IF T0IF WDTIF TSIF UART1IF UART0IF STIF SPIIF I2C1IF I2C0IF -


IFR_PIF (0120h) : Internal Interrupt Flag Register

I2SIF : I2S interrupt flag ADCIF : ADC interrupt flag T4IF : Timer 4 interrupt flag T3IF : Timer 3 interrupt flag T2IF : Timer 2 interrupt flag T1IF : Timer 1 interrupt flag T0IF : Timer 0 interrupt flag WDTIF : WDT interrupt flag TSIF : Touch Sensor interrupt flag UART1IF : UART 1 interrupt flag UART0IF : UART 0 interrupt flag STIF : Stop Timer or RTC interrupt flag SPIF : SPI interrupt flag I2C1IF : I2C 1 interrupt flag I2C0IF : I2C 0 interrupt flag

- - - - - - - - - - - - - - - URIF

R/W(0)

IFR_PIF2 (0148h) : Internal Interrupt Flag Register

URIF : UR interrupt flag

[131]

SeJong200 Family


EXT15IF EXT14IF EXT13IF EXT12IF EXT11IF EXT10IF EXT9IF EXT8IF - - EXT5IF EXT4IF EXT3IF EXT2IF EXT1IF EXT0IF


IFR_EXT (0121h) : External Interrupt Flag Register

EXT5IF : External 5 (P3.5) interrupt flag EXT4IF : External 4 (P3.4) interrupt flag EXT3IF : External 3 (P3.3) interrupt flag EXT2IF : External 2 (P3.2) interrupt flag EXT1IF : External 1 (P3.1) interrupt flag EXT0IF : External 0 (P3.0) interrupt flag

EXT15IF : External 15 (P2.15) interrupt flag EXT14IF : External 14 (P2.14) interrupt flag EXT13IF : External 13 (P2.13) interrupt flag EXT12IF : External 12 (P2.8) interrupt flag EXT11IF : External 11 (P2.7) interrupt flag EXT10IF : External 10 (P2.6) interrupt flag

EXT9IF : External 9 (P2.5) interrupt flag EXT8IF : External 8 (P2.4) interrupt flag

[132]



- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG1(0123h) : Internal Interrupt Configuration 1 (I2C0) Register

INT_EN : Interrupt Enable PRI[1:0] : Interrupt Priority [00] : Highest priority [01] : 2nd priority [10] : 3rd priority [11] : lowest priority

- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG2(0124h) : Internal Interrupt Configuration 2 (I2C1) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG3(0125h) : Internal Interrupt Configuration 3 (SPI) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG4(0126h) : Internal Interrupt Configuration 4 (Stop Timer) Register




- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG5(0127h) : Internal Interrupt Configuration 5 (UART0) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG6(0128h) : Internal Interrupt Configuration 6 (UART1) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG7(0129h) : Internal Interrupt Configuration 7 (TS) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG8(012Ah) : Internal Interrupt Configuration 8 (WDT) Register




- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG9(012Bh) : Internal Interrupt Configuration 9 (Timer0) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG10(012Ch) : Internal Interrupt Configuration 10 (Timer1) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG11(012Dh) : Internal Interrupt Configuration 11 (Timer2) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG12(012Eh) : Internal Interrupt Configuration 12 (Timer3) Register




- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG13 (012Fh) : Internal Interrupt Configuration 13 (Timer4) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG14(0130h) : Internal Interrupt Configuration 14 (ADC) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG16(0149h) : Internal Interrupt Configuration 16 (UR) Register


- - - - - - - - - - - - PRI1 PRI0 - INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

INTCFG15(0131h) : Internal Interrupt Configuration 15 (I2S) Register




- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

EXTCFG0(0132h) : External Interrupt Configuration 0 Register

INT_EN : Interrupt Enable POL : Interrupt Polarity Selection ([0] : posedge detection, [1] : negedge detection) PRI[1:0] : Interrupt Priority [00] : Highest priority [01] : 2nd priority [10] : 3rd priority [11] : lowest priority

- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)





- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)





- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)

EXTCFG10(0142h) : External Interrupt Configuration 10Register


- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)





- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)



- - - - - - - - - - - - PRI1 PRI0 POL INT_EN

R/W(0) R/W(0) R/W(0) R/W(0)




6.20. Interrupt Functional Description

High Priority High Priority High Priority

Low Priority

11 10 01 00

Lowest

Highest

Interrupt Level

I2C0 I2C0IF 11 10 01 00 I2C1 I2C1IF 11 10 01 00 SPI SPIIF 11 10 01 00 Stop Timer STIF 11 10 01 00 UART0 UART0IF 11 10 01 00 UART1 UART1IF 11 10 01 00 TCS TCSIF 11 10 01 00 WDT WDTIF 11 10 01 00 TIMER0 T0IF 11 10 01 00 TIMER1 T1IF 11 10 01 00 TIMER2 T2IF 11 10 01 00

ADC ADCIF

11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00

Interrupt Enable Bits High

Priority

Low Priority

CFG1 PRI1 PRI0 INT_EN
















Interrupt Vector

Low Priority

High Priority

Interrupt Sources (F/W P

olling)

TIMER3 T3IF

TIMER4 T4IF

I2S I2SIF

UR URIF


6.20. Interrupt Functional Description

High Priority High Priority High Priority

Low Priority

11 10 01 00

Lowest

Highest

Interrupt Level

11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00

11 10 01 00 11 10 01 00 11 10 01 00

INT10

11 10 01 00

INT11 EXT11IF

11 10 01 00

INT12

11 10 01 00

INT13 EXT13IF

11 10 01 00

INT14

INT15 EXT15IF

11 10 01 00

Interrupt Enable Bits High

Priority

Low Priority

EXTCFG0 PRI1 PRI0 INT_EN














Interrupt Vector

Low Priority

High Priority

Interrupt Sources (F/W P

olling) 1

0

POL 1 0

POL

1 0

POL

1 0

POL

1 0

POL

1 0

POL

EXT10IF

EXT12IF

EXT14IF

INT0

INT1 EXT1IF

INT2

INT3 EXT3IF

INT4

INT5 EXT5IF

1 0

POL 1 0

POL

1 0

POL

1 0

POL

1 0

POL

1 0

POL

EXT0IF

EXT2IF

EXT4IF

INT8

INT9 EXT9IF

1 0

POL

1 0

POL EXT8IF


6.20. Interrupt Controller

Operation Sequence Upon reception of peripheral or external interrupt with pre-programmed polarity, INTC (Interrupt Controller) immediately triggers DSP Core’s interrupt line. Note that the type of all peripheral interfaces is “level-triggered, high-level”, while the type of external

interrupts is “edge-triggered” with the polarity programmed by the configuration register. In the DSP core, the interrupt masking register should be setup correctly at initially core-booting sequence. After INTC triggers the DSP core’s interrupt line, the DSP core goes into the interrupt service routine (ISR). In the DSP core’s ISR, the INTC’s another interrupt triggering with higher priority preempts the current ISR

(interrupt preemption). At the end of DSP core’s ISR, the programmer should turn off the interrupt flag in register of the interrupt

source, i.e., the peripheral interface. For the external interrupts, the DSP core should turn off the corresponding bit(s) of IFR_EXT register. Note that the chip does not ensure the disabling of external interrupts which is up to the designer controlling

the external environments.


6.21. System Power Scheme

LDO_18 S_LDO LDO_25

VD33A VDDINTA VD33 VDD

VS33

VSSA

Logic part

VSS

VD33

12bit ADC

OPAMP (1.8 V only)

When differential ADC , Set VDDINTA = 1.8 V (Trim LCO_25) When single ADC, Set OPAMP off

Touch Engine

Digital plane (IO + Logic)

Analog plane (ADC + Touch)

IO


6.21. System Trimming Options (1 of 6)

LDO Trimming Options

- - - - - - - - - - - TRIM3 TRIM2 TRIM1 TRIM0

R/W(0) R/W(1) R/W(1) R/W(0)

TRIM_LDO_18 (013Ch) : LDO18 (For Logic) Trimming Option Register

TRIM_LDO_18[10:0] VDD

0000 1.495V

0001 1.546V

0010 1.597V

0011 1.648V

0100 1.698V

0101 1.749V

0110 1.800V

0111 1.851V

1000 1.902V

1001 1.953V

1010 2.003V

1011 2.053V

TRIM[3:0] : LDO_18 LDO output trimming value , the enable of LDO_18 is set by CEB pin not register




- - - - - - - - - - - TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

R/W(1) R/W(0) R/W(0) R/W(0) R/W(1)

TRIM_LDO_25 (013Dh) : LDO25 (For OPAMP, ADC and Touch) Trimming Option Register

TRIM_LDO_25[4:0] VDDINTA(V)

00000 1.479

00001 1.540

00010 1.600

00011 1.661

00100 1.721

00101 1.782

00110 1.842

00111 1.903

01000 1.963

01001 2.024

01010 2.085

01011 2.145

01100 2.206

01101 2.266

01110 2.327

01111 2.388

TRIM_LDO_25[4:0] VDDINTA(V)

10000 2.448

10001 2.509

10010 2.569

10011 2.630

10100 2.690

10101 2.751

10110 2.812

10111 2.872

11000 2.933

11001 2.993

11010 3.054

11011 3.114

11100 3.175

11101 3.235

11110 3.296

11111 3.356

TRIM[4:0] : LDO_25 LDO output trimming value , the enable of LDO_25 is set by the LDO_25_EN in LDO_LVR_SET Register




- - - - - - - TRIM_I TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0


TRIM_S_LDO (013Eh) : LDO100 (For logic at sleep mode) Trimming Option Register

TRIM_S_LDO[7:0] VDD I(XI2.IN) I(AVDD)

1111 1110 1.4996V 248nA 0.558uA

1111 1101 1.5996V 248nA 0.558uA

1111 1011 1.6996V 248nA 0.558uA

1111 0111 1.7996V 248nA 0.558uA

1110 1111 1.8996V 248nA 0.558uA

1101 1111 1.9996V 248nA 0.559uA

1011 1111 2.0994V 248nA 0.573uA

0111 1111 2.196V 248nA 0.705uA

TRIM[7:0] : S_LDO output trimming value , the enable of S_LDO is set by the S_LDO_EN in LDO_LVR_SET Register TRIM_I : S_LDO current reduce option (0 : disable , 1 : enable)



LDO_LVR_FLASH Control & Trimming Options

- - - - - - - - - - - TRIM4 TRIM3 TRIM2 TRIM1 TRIM0

R/W(0) R/W(0) R/W(1) R/W(1) R/W(0)

TRIM_LVR (013Bh) : LDO100 (For chip) Trimming Option Register

TRIM[4:0] LVR_16

00000 X (1.30V)

00001 X(1.35V)

00010 1.365V

00011 1.435V

00100 1.491V

00101 1.544V

00110 1.595V

00111 1.646V

01000 1.697V

01001 1.748V

01010 1.799V

01011 1.850V

01100 1.901V

01101 1.952V

01110 2.003V

01111 2.054V

TRIM[4:0] LVR_16

10000 2.105V

10001 2.156V

10010 2.207V

10011 2.258V

10100 2.309V

10101 2.360V

10110 2.411V

10111 2.462V

11000 2.514V

11001 2.565V

11010 2.616V

11011 2.667V

11100 2.718V

11101 2.769V

11110 2.820V

11111 2.869V



LDO_LVR_FLASH Control & Trimming Options

- - - - - - - - - - - - - S_LDO_EN

LDO_25_EN LVR_ON

R/W(0) R/W(0) R/W(1)

LDO_ LVR_SET (013Ah) : LVR Control Register

- - - - - - - - - - - - - - - PWR_SW_EN_B

R/W(0)

PWR_SW_EN_B(013Fh) : Flash power switch enable

Flash power switch enable/disable control (0 : flash power enable , 1: flash power disable)

LVR_ON : LVR on/off control (0 : LVR off , 1: LVR on) LDO_25_EN : LDO_25 enable for OPAMP, ADC and Touch (0 : disable , 1: enable) S_LDO_EN : S_LDO enable for sleep mode (0 : disable , 1: enable)

POR (LVR)

A X 1

B X 1

LVR_ON

POR/LVR Reset

POR LVR

1.8

VD

DIN

T [V

]

1.6

0

A B

POR Pulse

TIME 1.6V 1.6V

LVR Pulse TRIM_LVR[4:0]



LDO On Counter

- - - - - INCNT10 INCNT9 INCNT8 INCNT7 INCNT6 INCNT5 INCNT4 INCNT3 INCNT2 INCNT1 INCNT0

R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0)

LDO_ON_CNT (0103h) : LDO Stabilization Timer Count when wake-up from stop mode (recommended timer value : 20us)

PD_ON

[ Condition ] 1) ISCLK_SW = 0 (clock : Internal ring clock) 2) TSCLK_OFF = 1 (touch clock off) 3) ADCLK_EN = 0 (ADC clock off) 4) LVR_ON = 0 (LVR off)

LDO_ON_TIMER

LDO_ON_TIMER Overflow

System Clock


6.22. Reset Circuit : 3 Reset Sources

LVD(POR) Reset Power-on Reset when power is turned on. Power-fail Reset when the supply voltage is below the threshold voltage (VRST).

External Reset Pin Reset Pin must be held “LOW” for at least 24 clock cycles.

WDT Reset : Enable or Disable by S/W

Initialize

WDT 32 bits Counter

VDD

WDT RESET Generation

EnWDT

External RESETB Generation

(Min. 24 Clocks Period)

LVD RESET Generation LVD

RESETB

Clock

POR

Internal RESET


6.23. IAP ( In Application Programming)

Code memory(64kB) can be programmed during the operation of DSP.

Program time : approximately 30 us / Page Erase time : approximately 30 ms

Program unit : 1 Byte / Erase unit : 1k Bytes

IAP Registers

FAEN0.15 FAEN0.14 FAEN0.13 FAEN0.12 FAEN0.11 FAEN0.10 FAEN0.9 FAEN0.8 FAEN0.7 FAEN0.6 FAEN0.5 FAEN0.4 FAEN0.3 FAEN0.2 FAEN0.1 FAEN0.0


FAEN0 (060Eh) : Flash Access Enable Register 0

Flash Access Enable pattern 0 : 0xD119



FAEN1 (0060Fh) : Flash Access Enable Register 1

Flash Access Enable pattern 1 : 0xC976



FAEN2 (00610h) : Flash Access Enable Register 2

Flash Access Enable pattern 2 : 0xEC81



FAEN3 (00611h) : Flash Access Enable Register 3

Flash Access Enable pattern 3 : 0xC11E



- - - - - - - - - - - - RDT.3 RDT.2 RDT.1 RDT.0

R/W(0) R/W(1) R/W(0) R/W(0)

IAP_READ_T (0605h) : IAP Read Timing

IAP Read Timing : clock cycles (2 @ 48MHz)

- - - - - - NVSHT.9 NVSHT.8 NVSHT.7 NVSHT.6 NVSHT.5 NVSHT.4 NVSHT.3 NVSHT.2 NVSHT.1 NVSHT.0


IAP_NVSH_T (0606h) : IAP NVSTR Setup / Hold Timing

IAP NVSTR Setup / Hold Timing : clock cycles (275 @ 48MHz)

NVH1T.15 NVH1T.14 NVH1T.13 NVH1T.12 NVH1T.11 NVH1T.10 NVH1T.9 NVH1T.8 NVH1T.7 NVH1T.6 NVH1T.5 NVH1T.4 NVH1T.3 NVH1T.2 NVH1T.1 NVH1T.0


IAP_NVSH1_T (060Dh) : IAP NVSTR1 Hold Timing

IAP NVSTR1 Hold Timing : clock cycles (5500 @ 48MHz)

- - - - - PGST.10 PGST.9 PGST.8 PGST.7 PGST.6 PGST.5 PGST.4 PGST.3 PGST.2 PGST.1 PGST.0

R/W(1) R/W(0) R/W(0) R/W(0) R/W(1) R/W(0) R/W(0) R/W(1) R/W(1) R/W(0) R/W(0)

IAP_PGS_T (0607h) : IAP PGM Setup Timing

IAP PGM Setup Timing : clock cycles (550 @ 48MHz)

- - - - - - - - - - - - - - PGHT.1 PGHT.0

R/W(1) R/W(1)

IAP_PGH_T (0609h) : IAP PGM Hold Timing

IAP PGM Hold Timing : clock cycles (2 @ 48MHz)



- - - - PGMT.11 PGMT.10 PGMT.9 PGMT.8 PGMT.7 PGMT.6 PGMT.5 PGMT.4 PGMT.3 PGMT.2 PGMT.1 PGMT.0


IAP_PRM_T (0608h) : IAP PGM Timing

IAP PGM Timing : clock cycles (1050 @ 48MHz)

- - - - - - - - - ERST.22 ERST.21 ERST.20 ERST.19 ERST.18 ERST.17 ERST.16

R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(1)

IAP_ERSH_T (060Bh) : IAP ERS High Timing

IAP ERS High Timing : clock cycles (16 @ 48MHz)

ERST.15 ERST.14 ERST.13 ERST.12 ERST.11 ERST.10 ERST.9 ERST.8 ERST.7 ERST.6 ERST.5 ERST.4 ERST.3 ERST.2 ERST.1 ERST.0


IAP_ERSL_T (060Ch) : IAP ERS Low Timing

IAP ERS Low Timing : clock cycles (51424 @ 48MHz)

- - - - - - - RCVT.8 RCVT.7 RCVT.6 RCVT.5 RCVT.4 RCVT.3 RCVT.2 RCVT.1 RCVT.0


IAP_RCV_T (060Ah) : IAP Recovery Timing

IAP Recovery Timing : clock cycles (55 @ 48MHz)

- - - - - - - - - - - IFREN

R/W(0)

ISP_MODE (0601h) : ISP Mode Register

IFREN : Information Block Enable Status flag (set/cleared in only ISP mode)



IAPA.15 IAPA.14 IAPA.13 IAPA.12 IAPA.11 IAPA.10 IAPA.9 IAPA.8 IAPA.7 IAPA.6 IAPA.5 IAPA.4 IAPA.3 IAPA.2 IAPA.1 IAPA.0


IAP_ADDR (0603h) : IAP Address Register

IAP Address

IAPD.15 IAPD.14 IAPD.13 IAPD.12 IAPD.11 IAPD.10 IAPD.9 IAPD.8 IAPD.7 IAPD.6 IAPD.5 IAPD.4 IAPD.3 IAPD.2 IAPD.1 IAPD.0


IAP_DATA (0604h) : IAP Data Register

IAP Read/Write Data

- - - - - - - - - - - ERC IFREN_ST PGM PERS RD

R(0) R(0) R(0) R(0) R(0)

IAP_STATUS (0602h) : IAP Status Register

ERC : Status flag of Erase Reference Cell operation IFREN_ST : Information Block Enable Status flag PGM : Status flag of Program operation PERS : Status flag of Page Erase operation RD : Status flag of Read operation

- - - - - - - - - - - IAPC.1 IAPC.0

R/W(0) R/W(0)

IAP_CMD (0600h) : ISP Command Register

IAP Command [00] : Read command [01] : Page Erase command [10] : Reserved [11] : Program command


7. Absolute Maximum Ratings

Items Conditions Ranges

Voltage on any pin relative to Ground - -0.5V to (VDDIO+0.5V)

Voltage in VDDIO relative to Ground - -0.5V to 3.6V

Output Voltage - -0.5V to (VDDIO+0.5V)

Output Current High One I/O pin active -25mA

All I/O pin active -100mA

Output Current Low One I/O pin active +30mA

All I/O pin active +150mA

Storage Temperature - -65 oC to +150 oC

Soldering Temperature - 260 oC for 10 seconds


8. DC Characteristics

* TA = -40 oC to +85 oC, VDDIO = +2.2V to +3.6V unless otherwise specified.

Parameter Symbol Pin Conditions Value

Unit Min. Typ. Max.

Input Low Voltage VIL P0, P1, P2, P3 VDDIO = +2.2V to +3.6V -0.5 - 0.2VDDIO-0.1 V

Input high Voltage VIH P0, P1, P2, P3 VDDIO = +2.2V to +3.6V 0.2VDDIO+1.0 - VDDIO+0.5 V

Output Low Voltage VOL

P0, P1, P2, P3 VDDIO = +3.0V to +3.6V (IOL = 8.12mA) VDDIO = +2.7V to +3.0V (IOL = 6.76mA) VDDIO = +2.2V to +2.7V (IOL = 4.54mA)

- - 0.3VDDIO V

P0, P1, P2, P3 (High Drive) VDDIO = +3.0V to +3.6V (IOL = 32.49mA) VDDIO = +2.7V to +3.0V (IOL = 27.07mA) VDDIO = +2.2V to +2.7V (IOL = 18.18mA)

- - 0.3VDDIO V

Output High Voltage

VOH P0, P1, P2, P3 VDDIO = +3.0V to +3.6V (IOH = -7.57mA) VDDIO = +2.7V to +3.0V (IOH = -6.17mA) VDDIO = +2.2V to +2.7V (IOH = -4.42mA)

0.7VDDIO - - V

VOHP P0, P1, P2, P3 (Pull-up Resistor Only)

VDDIO = +3.0V to +3.6V (IOHP = -30.30uA) VDDIO = +2.7V to +3.0V (IOHP = -24.71uA) VDDIO = +2.2V to +2.7V (IOHP = -16.13uA)

0.7VDDIO - - V

Logical 1 to 0 Transition Current

ITL P0, P1, P2, P3 VDDIO = +3.0V ± 10%

(VIN = +2.0V) - - -650 µA

Input Leakage Current

IIL P0, P1, P2, P3 VIN = VIH or VIL - - ±1 µA

Pin Capacitance CIO All VDDIO = +3.0V - 10 - pF


9. AC Characteristics

Parameter Symbol Pin Conditions Value

Unit Min. Typ. Max.

RESETB Input Width tRST RESETB VDDIO = 3V ± 10% 24 - - FSYS

External Interrupt Input Width

tINT External Interrupt VDDIO = 3V ± 10% 4 - - FSYS

* TA = -40 oC to +125 oC, VDDIO = +1.8 to +3.6V unless otherwise specified.

External Interrupt Pin

RESETB 0.2VDD 0.2VDD

tRST

0.8VDD 0.8VDD

0.2VDD 0.2VDD

tINT

tINT


10. Package Dimensions : 48-MLF

TOP VIEW

D

E

BOTTOM VIEW

D2

E2

1 2

48

b

e

k

Exposed PAD

L

36

24

12

Pin #1 ID

Seating Plane

A

A1 A3

SIDE VIEW

DETAIL A

DETAIL A

0.20 REF. Terminal Thickness

0.00 ~ 0.05

3

24

48

Symbol Dimensions [mm]

Min. Nom. Max. A 0.70 0.75 0.80

A1 0.00 0.02 0.05

A3 0.20 REF

D 6.00 BSC

E 6.00 BSC

D2 4.20 4.30 4.40

E2 4.20 4.30 4.40

b 0.15 0.20 0.25

e 0.40 BSC

L 0.35 0.40 0.45

k 0.20 - -

[48-MLF]

Notes: 1. All Dimension are in mm. Angles in Degrees. 2. Dimension b applies to Plated Terminal & is measured. 3. BSC : Basic Dimension. Theoretically exact value shown without tolerances. REF : Reference Dimension, Usually without tolerance, for information purpose only.

1 2

12

3

36

SeJong200 Family

DETAIL A


0.00 ~ 0.05

[160]


D

E

34

68

17

51 2

Pin #1 ID

TOP VIEW BOTTOM VIEW

1

3

E2

Exposed PAD

1

17

2 3

68

P

k

L

51

D2

34

b

e

Seating Plane

A

A1 A3

SIDE VIEW

DETAIL A


Min. Nom. Max. A 0.80 0.85 0.90

A1 0.00 0.01 0.05

A3 0.20 REF

D 8.00 BSC

E 8.00 BSC

D2 4.70 4.80. 4.90

E2 4.70 4.80. 4.90

b 0.15 0.20 0.25

e 0.40 BSC

L 0.30 0.40 0.50

k 0.20 - - P 0.24 0.42 0.60

[68-MLF]




DETAIL A


0.00 ~ 0.05

D

E

44

88

22

66 2

Pin #1 ID

TOP VIEW BOTTOM VIEW

1

3

E2

Exposed PAD

1

22

2 3

88

P

k

L

66

D2

44

b

e

Seating Plane

A

A1 A3

SIDE VIEW

DETAIL A


Min. Nom. Max. A 0.80 0.85 0.90

A1 0.00 0.01 0.05

A3 0.20 REF

D 10.00 BSC

E 10.00 BSC

D2 4.20 4.30. 4.40

E2 4.20 4.30. 4.40

b 0.15 0.20 0.25

e 0.40 BSC

L 0.30 0.40 0.50

k 0.20 - - P 0.24 0.42 0.60

[88-MLF]



11. Supporting tools

In-Circuit Debugger (GENSYS & GenICE)

World Wide Programmable in Anywhere (Hi-Lo Systems, ADVANTECH, TOPMAX, CORERIVER)

Support Parallel / Serial Programming

ROM Writer

Easy-to-Use GUI (GENTOS)

Assembler & Linker for Windows Optimized Cross-C Compiler

On-board Application (with Touch & MCU Demo) Various Sample Test Program

Application System


Appendix A : Update History

V1.0 First Release.

V1.1 ADC resolution : 12-bit 24-bit

V1.2 Page 9, 16 : Pin name P1.14(ADC1.14(VP8) -> Removed ) P2.09(ADC2.09(VP12) -> Removed ) P2.12(ADC2.12(VN13,S8) -> S8 ) P4.03(I2C1_SCLK_A) ->

I2C1_SCL_A) V1.3

Page 140 : Add Flash Power Switch Enable Reg(0x013F)

V1.4 RTC address change (0x03A- ~ 0x03B-)

(0x03C- ~ 0x03D-)

V1.5 Added the touch sensors

V1.6 touch sensors register update

V1.6.1 88 pin map update

V1.7 Ext counter port description update for Timer2,4 the power condition for differential ADC mode setting port exclusively among LCDC, ADC and Touch update system trimming option part

V1.8 ADC S8 position update

V1.9 Updated UART description Added STOP timer

Documents

MiDAS Family SeJong Family - CORERIVER · PDF fileSeJong Family CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, ... SeJong200