Microprocessor 8085 A

7/27/2019 Microprocessor 8085 A

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8085 Microprocessor Architecture

The Intel 8085A microprocessor(P)


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Intel 8085 CPU

Introduced on March

1976 8-bit microprocessor

3 MHz 6500 Transistors

64K Byte addressablememory


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The 8085A The 8085A is an 8-bit general purpose microprocessor

that can address 64K Bytes of memory.

It has 40 pins and uses +5V for power. It can run at amaximum frequency of 3 MHz.

The pins on the chip can be grouped into 6 groups:

Address BusData Bus

Control and Status Signals

Power supply and frequency

Externally Initiated Signals

Serial I/O portsv


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8085A Pin Diagram

Address ( Low order)and data Bus

Address Bus

( High order)

Clock

8085 A

8085 A Pin Diagram


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8085A Pin Diagram


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Interrupts &Externally Initiated

Signals

40

Vcc

3RESET

OUT

A15 26

A8 21

AD7 19

AD0 12

30 ALE

29 S0

33 S1

34 IO/M

32 RD

31 WR

11 INTA

38 HLDA

Control and

Status Signals

Serial I/O Ports

High Order Address Bus

Multiplexed Address/ Data Bus

SID 5

SOD 4

TRAP 6

RST 7.5 7

RST 6.5 8

INTR 10

RST 5.5 9

READY 35

HOLD 39

RESETIN 36

37CLK

OUT

1

X1

2

X2

GRD

20

8085A : Groups


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The 8085 Bus Structure

The 8-bit 8085 CPU (or Micro Processing Unit) communicates with

the other units using a 16-bit address bus, an 8-bit data bus and

a control bus


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The Address and Data Bus: Interconnections between units

The address bus consists of 16 address lines of which

1. 8 signal linesA8 A15 are unidirectional.

2. The other 8 address bits are multiplexed (timeshared) with the 8 data bits.

So, the bitsAD0 AD7 are bi-directional and serve as

A0 A7 and D0 D7 at the same time.

During the execution of the instruction, these lines carrythe address bits during the early part, then during thelate parts of the execution, they carry the 8 data bits.

Bus:A shared group of wires used for communicating signals among devices

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The Address and Data Bus: Interconnections between units

Important Facts

In order to separate the address from the data, a latch

can be used to save the value before the function of the

bits changes.

16 address lines are capable of addressing a

total of 216 = 65,536 (64k) memory locations.

Address locations: 0000 (Hex) FFFF (Hex)

Data range: 00 (Hex) FF (Hex)



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The Control and Status SignalsThere are 4 main control and status signals.

These are: ALE: Address Latch Enable. This signal is a pulse that become

1 when the AD0 AD7 lines have an address on them. It

becomes 0 after that. This signal can be used to enable a latch

to save the address bits from the AD lines.

RD: Read. Active low.

WR: Write. Active low.

IO/M: This signal specifies whether the operation is a memory

operation (IO/M=0) or an I/O operation (IO/M=1).

S1 and S0 : Status signals to specify the kind of operation

being performed .


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There are 4 main control and status signals.

These are: ALE: Address Latch Enable. This signal is a pulse that become

1 when the AD0 AD7 lines have an address on them. It

becomes 0 after that. This signal can be used to enable a latch

to save the address bits from the AD lines.

RD: Read. Active low.

WR: Write. Active low.

IO/M: This signal specifies whether the operation is a memory

operation (IO/M=0) or an I/O operation (IO/M=1).

S1 and S0 : Status signals to specify the kind of operation

being performed .


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Frequency Control Signals

There are 3 important pins in the frequency control group.

X0 and X1 are the inputs from the crystal or clock generating

circuit.

The frequency is internally divided by 2.

So, to run the microprocessor at 3 MHz, a clock running

at 6 MHz should be connected to the X0 and X1 pins.

CLK (OUT): An output clock pin to drive the clock of the rest of

the system.

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Demultiplexing AD7-AD0

it is obvious that theAD7 AD0 lines are serving a dual

purpose and that they need to be demultiplexed to be used

in both situations.

The high order bits of the address remain on the bus for

~three clock periods. However, the low order bits remain

foronly one clock period and they would be lost if they are

not saved externally.

To make sure an external latch to save the value of AD7AD0 when it is carrying the address bits is used. TheALE

signal enables this latch.

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Demultiplexing AD7-AD0

Given that ALE operates as a pulse during first clock pulse T1, theaddress is latched. Then when ALE goes low, the address issaved and the AD7 AD0 lines can be used for their purpose asthe bi-directional data lines.

A15-A8

LatchAD7-AD0

D7

- D0

A7

- A0

8085

ALE

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Memory

Memory: Where instructions (programs) and data are stored

Organized in arrays of locations (addresses),

Each Memory Location stores one byte (8 bits)

There is a a lot of interaction between the microprocessor and the memory

for

exchange of information during program execution

. control signals and their timing

Memory has its requirements and the microprocessor has its requirements as well.

.

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The interfacing operation is simply the matching of these requirements


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Memory structure & its requirements

The process of interfacing the above two chips is the same.

The ROM does not have a WR signal

Address

Lines

Data Lines

CS

RDOutput Buffer

RAMWRInput Buffer

Data Lines

Address

Lines

Date

Lines

CS

RDOutput Buffer

ROM

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Interfacing Memory

Accessing memory can be summarized into the

following three steps: Select the chip.

Identify the memory register.

Enable the appropriate buffer.

Translating this to microprocessor domain: The microprocessor places a 16-bit address on the address bus.

Part of the address bus will select the chip and the otherpart will

go through the address decoder to select the register. The signals IO/M and RD combined indicate that a memory read

operation is in progress. The MEMR signal can be used to enable

the RD line on the memory chip.

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I/O

I/O devices: Enable system to interact

with the world Device interface hardware connects actual

device to bus

The CPU views the I/O device registers justlike memory that can be accessed over thebus. However, I/O registers are connected to

external wires, device control logic, etc. Reads may not return last value written

Writes may have side effects

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Address decoding

The result of address decoding is the identification of a

register for a given address. A large part of the address bus is usually connected

directly to the address inputs of the memory chip.

This portion is decoded internally within the chip.

What concerns us is the other part that must bedecoded externally to select the chip.

This can be done either using logic gates or a

decoder.

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The Overall Picture

Putting all of the concepts together, we get:

A15-A8

LatchAD7-AD0

D7

- D0

A7

- A0

8085

ALE

IO/MRDWR

1K Byte

Memory

Chip

WRRD

CS

A9

- A0

A15

- A10

Chip Selection

Circuit

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D Q

G

OC

A7AD7

ALEEnable

74LS373

D7

ALE is High the latch is transparent

Output changes according to input dataOutput follows the input as long as G is

high

ALE Low Output of latch represents

low order address bus

The output does not change and

retains the D input level which is the

low order address

8 such latches de-multiplex the AD bus

The Latch in Detail


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The 8085: Pin outs and details

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ADDRESS LINES A8 - A15:

These tri-state lines are outbound only.

They provide the upper 8 bits of the 16-bit-wide address which identifies one

unique 8-bit byte within the Ps address space.Sixteen address lines provide an address space of 65,536 locations.

ADDRESS-DATA LINES AD0 - AD7:

These tri-state lines may by either inbound or outbound.They provide a multiplexing between the lower 8 bits of the 16-bit-wide address

early in a machine cycle and 8 data bits later in the cycle.

When containing addresses, these lines are outbound only; when containing

data, they may be either inbound or outbound, depending upon the nature of the

machine cycle.

They also will contain the 8 bits of an I/O device address during an I/O operation.


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ADDRESS LATCH ENABLE (ALE):

This signal appears outbound early in a machine cycle to advise theexternal circuitry that the AD0 - AD7 lines contain the lower 8 bits of a

memory address.

It should be used to clock a catch-and-hold circuit such as a 74LS245 or

74LS373, so that the full address will be available to the system for the rest

of the machine cycle.

The falling edge of ALE is the point at which the signals on the AD lines, as

well as the S0, S1, and IO/M lines will be stable and may be taken by the

external circuitry.

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STATUS LINES S0, S1, & IO/M:

These three status lines serve to indicate the general status of the processor

with respect to what function the P will perform during the machine cycle.The S0 and S1 lines are made available for circuits which need advanced

warning of the ensuing operation, such as very slow RAM or otherspecialized devices.

The IO/M line approximates in one line what the S0 and S1 lines do in two. It

indicates whether the operation will be directed toward memory (line is low),or toward I/O (line is high).

READ & WRITE (RD & /WR):

These lines indicate which direction the MP expects to pass data between itselfand the external data bus.

Read indicates that the P is expecting data to be fed to it;Write indicates that the P is going to send data away from itself.These lines also serve to time the event, as well as identify its direction.

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The 8085: Pin outs and details READY:

This is an input line which may be used as a signal from external RAM thata wait state is needed, since the RAM is not able to provide the data or

accept it in the time allowed by the P .

The negation of Ready, by being pulled low, will cause the 8085 to enterwait states.

See the timing diagrams for critical timing.

HOLD & HOLD ACKNOWLEDGE (HOLD & HLDA):

These lines provide the 8085 with a DMA capability by allowing anotherprocessor on the same system buses to request control of the buses.

Upon receipt of HOLD, the P will tristate its address, data, and certaincontrol lines, then generate HLDA.

This signals the other processor that it may proceed.

The P will remain off the buses until HOLD is negated.

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INTERRUPT & INTERRUPT ACKNOWLEDGE (INTR & INTA):

These lines provide a vectored interrupt capability to the 8085.

Upon receipt of INTR, the P will complete the instruction in process, thengenerate INTA as it enters the next machine cycle.

The interrupting device will jam a Restart (RST) instruction onto the data bus,which the P uses to locate an interrupt vector in low RAM.

RST 5.5, 6.5, 7.5:These three lines are additional interrupt lines which generate an automaticRestart,.

These lines have priority over the INTR line, and each other.

They also have certain electrical characteristics for assertion, and may be

masked off or on by software.

TRAP: This is an unmaskable interrupt with a fixed vector in RAM.

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RESET IN & RESET OUT:

These lines provide for both P and system reset. The RESET IN line is generated asynchronously by some sort of external

circuit, such as an RC network or Reset switch. Upon receipt of this signal, the P will internally synchronize the Reset with

the clock of the processor, then generate RESET OUT for other devices in

the system.

X1 & X2:

These two pins provide connection for an external frequency determining

circuit to feed the 8085s clock.

This is normally a crystal, although other resonant circuits may be used.

The internal oscillator of the 85 will divide the frequency by two for the

system clock.

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CLOCK (CLK):

This line provides a system clock signal to external circuits which need to be in

synchronization with the P .SERIAL INPUT DATA & SERIAL OUTPUT DATA (SID & SOD):

These two lines provide for a single serial input or output line to/from the 8085.

These lines are brought into the device as D7, and may be tested or set by theRead Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions.

These two instructions also have control over the mask which controls the RST5.5, 6.5, and 7.5, and TRAP, interrupts.

The SID and SOD lines are simple single bit I/O lines; any timing required to

provide external communication via them must be provided by the software.

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Vcc & Vss: These are the power connections for +5 volts and ground


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The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is capable ofperforming the following operations:

Store 8-bit data (Registers, Accumulator)

Perform arithmetic and logic operations (ALU)

Test for conditions (IF / THEN)

Sequence the execution of instructions

Store temporary data in RAM during execution

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8085 Functional Block Diagram

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Simplified block diagram

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The ALU In addition to the arithmetic & logic circuits, the

ALU includes the accumulator, which is part ofevery arithmetic & logic operation.

Also, the ALU includes a temporary registerused for holding data temporarily during the

execution of the operation. This temporary

register is not accessible by the programmer.

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The 8085: Registers

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Registers

Six general purpose 8-bit registers: B, C, D, E, H, L

They can also be combined as register pairs to perform 16-bitoperations: BC, DE, HL

The H&L register pair may be used to store indirect addresses

Registers are programmable (data load, move, etc).

Accumulator

Single 8-bit register that is part of the ALU !

Used for arithmetic / logic operations the resultis always stored in the accumulator.

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Flag Bits

Indicate the result of condition tests.

Carry, Zero, Sign, Parity, etc. Conditional operations (IF / THEN) are executed based on the

condition of these flag bits.

Program Counter (PC)

Contains the memory address (16 bits) of the instruction that will be

executed in the next step.

Stack Pointer (SP)

Contains the address information(16 bit) of the location of the stack.

This register is always incremented/decremented by 2.

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The Flags Register

There is also the flags register(5 bits) whose bits areaffected by the arithmetic & logic operations.

S-sign flag The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logicoperation.

Z-zero flag Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected

by operations on the accumulator as well as other registers. (DCR B).

AC-Auxiliary Carry This flag is set when a carry is generated from bit D3 and passed to D4 . This flag

is used only internally for BCD operations. (Section 10.5 describes BCD additionincluding the DAA instruction).

P-Parity flag After an ALU operation if the result has an even # of 1s the p-flag is set.

Otherwise it is cleared. So, the flag can be used to indicate even parity.

CY-carry flag After an ALU operation if the operation results in a carry the carry flag is set.

Otherwise it is cleared. So, the flag can be used to indicate borrow for subtraction.

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The Flag register

CYZS AC P

D7 D6 D5 D4 D3 D2 D1 D0

X X X


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8085:SYSTEM TIMING

The time required by the 8085 to fetch andexecute one machine language instruction isdefined as an Instruction Cycle.

The instructions may be of different complexities,with the result that the more complicatedinstructions take longer to execute.

The 8085s method of instruction execution inside

the P is more organized, however, and so thetime required to execute any instruction is morepredictable and more regular.

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Cycles and States

T- State: One subdivision of an operation. A T-state lasts

for one clock period.

An instructions execution length is usually measured in anumber of T-states. (clock cycles).

Machine Cycle: The time required to complete one

operation of accessing memory, I/O, or acknowledging anexternal request.

This cycle may consist of 3 to 6 T-states.

Instruction Cycle: The time required to complete the

execution of an instruction.

In the 8085, an instruction cycle may consist of 1 to 6

machine cycles.

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More on the 8085 machine cycles

The 8085 executes several types of instructions

with each requiring a different number ofoperations of different types. However, the

operations can be grouped into a small set.

The three main types are: Memory Read and Write.

I/O Read and Write.

Request Acknowledge.

These can be further divided into various

operations (machine cycles).

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8085:THE PROCESS0R CYCLE

Each instruction is divided into one to five Machine Cycles.

Each machine cycle is essentially the result of the need, by theinstruction being executed, to access the RAM.

The shortest instruction would require just one machine cycle, in whichthe instruction itself is obtained from RAM.

The longest, of five machine cycles, would consist of five RAMaccesses, the first to obtain the instruction byte itself, and theremaining four to be divided into fetching and saving other bytes.

For example, cycles numbers 2 & 3 may be needed to fetch twomore bytes of an address, while numbers 4 & 5 may be needed tosave a 2-byte address somewhere else in RAM.

The type of machine cycle being executed is specified by the statuslines IO/M, S0, and S1, and the control lines RD, WR, and INTA.

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These six lines can define seven different machine cycle types


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Machine Cycles :Types

1. OP CODE FETCH

2. MEMORY READ

3. MEMORY WRITE

4. I/O READ5. I/O WRITE

6. INTERRUPT ACKNOWLEDGE

7. BUS IDLE

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Control and Status signals


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ALE, RD, WR, IO/M, S0 and S1

Control and Status signals

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XXZReset

XXZHold

RD, WR = Zand INTA = 1

00ZHalt

INTA = 0111Interrupt

Acknowledge

WR = 0101IO WriteRD = 0011IO Read

WR = 0100Memory Write

RD = 0010Memory Read

RD = 0110Op-code Fetch

S0S1IO/M

Control

Signals

StatusMachine cycle


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Generating Control Signals

The 8085 generates a single RD signal. However, the signal needs tobe used with both memory and I/O. So, it must be combined withthe IO/M signal to generate different control signals for the memory

and I/O. Keeping in mind the operation of the IO/M signal we can use

the following circuitry to generate the right set of signals:

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Example: Instruction Fetch Operation

All instructions (program steps) are stored in memory.

To run a program, the individual instructions must be read from

the memory in sequence, and executed.

Program counter puts the 16-bit memory address of the

instruction on the address bus

Control unit sends the Memory Read Enable signal toaccess the memory

The 8-bit instruction stored in memory is placed on the databus and transferred to the instruction decoder

Instruction is decoded and executed

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Example: Instruction Fetch Operation

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Op-code Fetch Machine Cycle

The first step of executing any instruction is theOp-code/Instruction fetch cycle.

In this cycle, the microprocessor brings in theinstructions Op-code from memory.

To differentiate this machine cycle from the very similarmemory read cycle, the control & status signals are set as

follows: IO/M=0, S0 and S1 are both 1.

This machine cycle has four T-states. The 8085 uses the first 3 T-states to fetch the op-code.

T4 is used to decode and execute it. It is also possible for an instruction to have 6 T-states

in an op-code fetch machine cycle.

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Op-code Fetch: Timing Diagram

Timing transfer of byteFrom memory to P

T1 T2 T3

CLK

A15 A8

AD7 AD0 05H

20H

4FH

ALE

IO/M

RD

Memory

content

Low order

address

Higher order

address

M


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Memory Read Machine Cycle

The memory read machine cycle is exactly

the same as the opcode fetch except: It only has 3 T-states

The S0 signal is set to 0 instead

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The Memory Read Machine Cycle

To understand the memory read machine cycle, letsstudy the execution of the following instruction:

MVI A, 32

In memory, this instruction looks like: The first byte 3EH represents the opcode for loading a byte

into the accumulator (MVI A), the second byte is the data tobe loaded.

The 8085 needs to read these two bytes frommemory before it can execute the instruction.

Therefore, it will need at least two machine cycles. The first machine cycle is the opcode fetch discussed earlier.

The second machine cycle is the Memory Read Cycle.

Figure 3.10 page 83.

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Example: Memory Read Operation

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2000H

2001H

3E

32

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8085 Functional Block Diagram

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8085:Instruction Set

8085 instruction set consists of the following instructions:

Data movement instructions. Arithmetic - add, subtract, increment and decrement.

Logic - AND, OR, XOR and rotate.

Control transfer - conditional, unconditional, call subroutine,return from subroutine and restarts.

Input/Output instructions.

Other Machine Instructions - setting/clearing flag bits,enabling/disabling interrupts, stack operations, etc.

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Addressing modes


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Addressing modes

Direct addressing:Simple instructions,

address of the memory location iscontained in the instruction

itselfInstructions are 3 byte in length

Register Direct addressing:

Address is that of data in registeror register pair not memorylocation

Instructions are executed faster,they need not be fetched frommemory

Single byte instructions

Register indirect addressing

Instruction specifies register paircontaining address, where thedata is stored

Instructions are 3 byte in length

Immediate Addressing

contains the data (8 or 16-bitdata) itself

2 or 3 byte instructions

Stack Addressing

Contents of stack pointer is dataitself

DATA TRANSFER GROUP


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DATA TRANSFER GROUP

This group of instructions provides the 8085 with the ability to

move data around inside the RAM, between the RAM and the registersof the P , and between registers within the P .

They are important because a good deal of moving must be done inprogramming

MOV GROUP:

Three instructions (MOV r1,r2, MOV r,M, and MOV M,r) are the generalmeans of moving data between memory and registers

They are one byte instructions

Copies data from the source register r2 to the destination register r1 Illustrate the use of the Register Indirect mode of addressing

The letter "M", specifies MEMORY contents with H&L as the registerto contain the address. No other register pair can be used as such.

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MOV Instruction: Data Transfer Group


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p

MOV r1,r2

Cycle 1

T state 4

Address register

Flags None

MOV M,r , MOV r,M

Cycle 2

T state 7

Address register indirect

Flags None

7F7E7D7C7B7A7978A

77757473727170M

6F6E6D6C6B6A6968L

6766656463626160H

5F5E5D5C5B5A5958E

5756555453525150D

4F4E4D4C4B4A4948C

4746454443424140B

AMLHEDCB

Destination

Location

Source LocationHex. Code


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MOVE IMMEDIATE : Data Transfer Group

MVI GROUP:

These two instructions (MVI r,data, and MVI M,data)provide a means of loading a byte immediately into a

register or a memory address. Note that the Register Indirect mode again is evident.

The immediate data is stored as a byte directly belowthe instruction byte.

MVI r,d8 Move immediate 8 bit data, MVI M, d8

Cycle 2, 3

T state 7, 10

Address immediateFlags None

3E362E261E160E06

AMLHEDCB

LOAD ACUMULATOR DATA TRANSFER GROUP


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LOAD ACUMULATOR:DATA TRANSFER GROUP

STA addr16

Cycle 4

Tstate 13

Address direct

Flags None

Hex Code 32

LDA addr16

Cycle 4

T state 13

Address direct

Flags None

Hex code 3A

LDA & STA:

The Load Accumulator Direct (LDA) and the Store Accumulator Direct(STA) instructions provide a means of moving a byte between theaccumulator and a RAM address.

This may also be done with the MOV OP code, but only indirectly, that is,with the help of the H&L registers.

The address of the byte to be loaded or stored follows the instruction, againwith the inverse addressing

This is a 3 byte instruction

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LOAD Resister Pair: Data Transfer Group

LXI rp, addr 16

Cycle 3

T state 10

Address immediate

Flags None

LXI INSTRUCTION: Load register pair immediate

This single instruction (LXI rp,data 16/addr 16) provides ameans of loading any register pair with a two-byte value.

The second byte of the instruction is loaded into the leftmost,or low-order, register of the pair,

while the third byte is loaded into the rightmost, or high order,register of the pair

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31211101

SPHDB

DATA TRANSFER GROUP


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DATA TRANSFER GROUP

LHLD & SHLD:The Load H&L Direct (LHLD) and Store H&L Direct (SHLD) instructions

provide a means of moving two bytes between the HL register pair

and a Memory address pointed out by 16 bit address.Since the H&L register pair is heavily used in the Register Indirect

mode, these instructions provide a quick means of loading the two

bytes of an address into the pair in only one instruction.

The two bytes following the instruction contain an address in memory

location again low-order in byte 2, and high-order in byte 3.

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LHLD addr16

Cycle 5T state 16

Address direct

Flags None

Hex code 2A

SHLD addr16

Cycle 5T state 16

Address direct

Flags None

Hex code 22

DATA TRANSFER GROUP


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DATA TRANSFER GROUP

LDAX & STAX: The Load Accumulator Indirect (LDAX) and Store Accumulator Indirect

(STAX) instructions provide a means of moving data between theaccumulator and a memory location indirectly, with the memoryaddress contained in either the BC or DE register pair.

This is not the same as the MOV, which uses only the HL register pair.

This instruction permits the accumulator to access groups of databytes, as may be necessary with long precision arithmetic.

Obviously, the BC or DE pair must be previously loaded with theaddress desired.

They are 1 byte instructions

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LDAX

Cycle 2

T state 7Address indirect

Flags None

Hex code LDAX B 0A

LDAX D 1A

STAX

Cycle 2

T state 7Address indirect

Flags None

Hex code STAX B 02

STAX D 12

DATA TRANSFER GROUP


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DATA TRANSFER GROUP

XCHG INSTRUCTION: The Exchange (XCHG) instruction permits the HL register pairs

contents to be exchanged with the DE register pairs contents.

Exchange H and L with D and E

This allows an address to be built in the DE pair, then, when ready, tobe transferred at once to the HL pair.

This would be advantageous in complex data handling

Moves the contents of four registers at a time

One byte instruction

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XCHG

Cycle 1

T state 4

Address register

Flags None

Hex code EB


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ARITHMETIC GROUP

This group provides the 8085 with mathematical ability

to manipulate 8-bit data to manipulate larger data (by judicious use of the codes)

The Accumulator can perform additions, subtractions, and compares.

The other register contents can only increment or decrement by 1.

All the condition flags are affected (Unless otherwise indicated)

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ARITHMETIC GROUP


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ADD INSTRUCTIONS:

The Add Register (ADD r) and Add Memory (ADD M) instructions add the

byte specified, either in a register or in the address contained by the

H&L registers, into the accumulator.

They assume that the accumulator already has in it the other value to

participate in the add.

The sum will remain in the accumulator.

If the answer resulted in a ninth bit, it is stored in the Carry flag

It is a one byte instruction

Mallika Verma

ADD r, ADD M

Cycle 1, 2T state 4, 7

Address register

Flags All modified to reflect the result of

addition

8786858483828180

AMLHEDCB

ARITHMETIC GROUP


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66

ARITHMETIC GROUP

ADD WITH CARRY (ADC):

The Add Register with Carry (ADC r) and Add Memory with Carry

(ADC M) instructions will add the specified byte, either in a register

or in the address contained by the H&L registers, AND the value ofthe Carry bit, into the accumulator.

By including the carry bit in the operation, mathematical operations

on values longer than 8 bits are possible.

the first value must already be loaded in the A register prior to

execution of these instructions.

The sum remains in the accumulator.

If the answer resulted in a ninth bit, it is stored in the Carry flag. It is a one byte instruction

Mallika Verma


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67

ARITHMETIC GROUP

ADC r, ADC M

Cycle 1, 2

T state 4, 7 Address register

Flags All modified to reflectthe result of addition

Mallika Verma

8F8E8D8C8B8A8988

AMLHEDCB

ARITHMETIC GROUP


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68

ARITHMETIC GROUP

ADD IMMEDIATES:

The Add Immediate (ADI) and Add Immediate with Carry (ACI)

instructions provide a means of adding a fixed value into the

accumulator.

These instructions assume that an initial value has already been

loaded into the accumulator.

The immediate data is provided by the second byte of the instruction.

The ACI instruction adds the immediate value and the value of the

Carry flag, while the ADI does not take the Carry flag into account.

The sum remains in the accumulator.

If the answer resulted in a ninth bit, it is stored in the Carry flag.

Mallika Verma

ADI d 8

Cycle 2T state 7

Address immediate

Flags All modified to reflect

the result of addition

ACI d8

Cycle 2T state 7

Address immediate

Flags All modified to reflect the

result of addition

ARITHMETIC GROUP


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69

ARITHMETIC GROUP

SUBTRACT INSTRUCTIONS:SUB r and SUB M subtract the specified byte, in a register

or in the address contained by the H&L registers, from

the contents of the accumulator.The accumulator must have the first value already loaded ,

prior to the execution of the instructions.

The subtract is accomplished by the complement-and-addtechnique, in which the twos complement of thespecified value is computed first, and then added to thecontents of the A register.

The Carry flag will be set to a 1 if a borrow was requiredduring the subtraction.

Mallika Verma


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ARITHMETIC GROUP

SUB r, SUB M

Cycle 1, 2

T state 4, 7 Address register

Flags All modified to reflectthe result of Subtraction

Mallika Verma

9796959493929190

AMLHEDCB

ARITHMETIC GROUP


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71

SUBTRACT WITH BORROW:

The Subtract Register with Borrow (SBB r) and the SubtractMemory with Borrow (SBB M) instructions will subtract thespecified byte, either in a register or in the address contained inthe H&L registers, and the value of the Carry flag, from thecontents of the A register.

The first value must be loaded into the A register prior to theexecution of the instructions.

The subtract is accomplished by the complement-and-addtechnique.

The Carry flag will be set to a 1 if a borrow was required duringthe subtraction.

Mallika Verma

SBB r, SBB M

Cycle 1, 2

T state 4, 7

Address register

Flags All modified to reflect theresult of Subtraction

9F9E9D9C9B9A9998

AMLHEDCB


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72

ARITHMETIC GROUP

SUBTRACT IMMEDIATES:

The Subtract Immediate (SUI d8) and Subtract Immediate with Borrow

(SBI d8) instructions provide a means of subtracting a fixed valuefrom the contents of the accumulator.

The immediate value is provided by the second byte of the instruction.

The first value must be loaded into the accumulator prior to the

execution of the instructions.The subtract is accomplished by the complement-and-add technique.

The SBI instruction will subtract both the immediate value and thecontents of the Carry flag from the A register, while the SUI does nottake the Carry flag into account.

The Carry flag will be set at the end of the instruction if , a borrow wasrequired during execution.

Mallika Verma


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ARITHMETIC GROUP

SUI d 8

Cycle 2 T state 7

Address immediate

Flags All modified to reflect theresult of subtraction

Hex Code D6

Mallika Verma

SBI d 8

Cycle 2T state 7

Address immediate

Flags All modified to reflect the

result of subtractionHex Code DE

SUBTRACT IMMEDIATES


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74

ARITHMETIC GROUP

INCREMENT INSTRUCTIONS:

The Increment Register (INR r) and Increment Memory (INR M)

instructions provide a quick means of adding one to the contents of aregister or memory location.

These instructions allow the programmer to create counting routines

and reiterations.

Note that the Carry flag is not affected by these instructions.

Mallika Verma

INR r, INR M

Cycle 1, 3

T state 4, 10

Address register

Flags All modified except Cy to reflect

the result of operation

3C342C241C140C04

AMLHEDCB


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75

ARITHMETIC GROUP

DECREMENT INSTRUCTIONS:

The Decrement Register (DCR r) and Decrement Memory (DCR M)instructions provide a quick means of subtracting one from the

contents of a register or a memory location. These instructions allow the programmer to create counting routines

and reiterations.

Note that the Carry flag is not affected by these instructions.


Mallika Verma

DCR r, DCR M

Cycle 1, 3

T state 4, 10Address register

Flags All modified except Cy to reflect

the result of operation

3D352D251D150D05

AMLHEDCB

ARITHMETIC GROUP


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76

REGISTER PAIR INSTRUCTIONS:

The Increment Register Pair (INX rp) and Decrement Register Pair (DCXrp) instructions provide a means of adding to, or subtracting from, a16-bit value contained in a register pair.

In the INX instruction, this means that the carry from the sum of the loworder byte of the pair and the one will be added into the upper byteautomatically.

In the DCX instruction, this means that a borrow from the high-orderbyte, if required, will be allowed into the low-order byte, if thesubtraction of one from the low-order byte demands it.

Note that none of the flags are affected.It is also used for incrementing/ decrementing memory location

Mallika Verma

INX rp, DCX rp

Cycle 1T state 6

Address register

Flags none3B2B1B0B33231303

SPHDBSPHDB

DCXINX


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77

ARITHMETIC GROUP

D0UBLE ADD:

The Add Register Pair to H&L (DAD rp) instruction adds a 16 bit value already

existing in the BC or DE register pair into the 16-bit value contained in the H&L

registers. The sum remains in the H&L registers.

The Carry flag will be set if a carry occurred out of the high order byte;

A carry from low- to high-order bytes within the add is taken into account

automatically.

This instruction is one byte

Only instruction where the accumulator is not involved in addition

Mallika Verma

DAD rpCycle 3

T state 10

Address register

Flags only CY flag affected,

no other flag

39291909

SPHDB

ARITHMETIC GROUP


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78

ARITHMETIC GROUP

DECIMAL ADJUST:

The Decimal Adjust Accumulator (DAA) instruction converts the 8-bit valuein the A register, which normally is assumed to be two 4bit hexadecimalvalues, into two 4-bit BCD values.

This allows the programmer to accept input data as BCD, process it in theaccumulator using essentially hexadecimal arithmetic, and then convert theresult back into BCD.

This may be done by virtue of the fact that the ten numbers of BCD (0 to 9)are coded in binary exactly as are the first ten of the sixteen numbers of

binary coded hexadecimal. i.e., adding 3810 and 3816 are exactly thesame.

The conversion be may accomplished by the use of the Auxiliary Carry flag.If the contents of the low-order four bits of the A register is >9, or if the ACflag is set, a value of 6 is added to these bits. Then the high-order four bitsof the A register are examined; again, if they contain a value >9, or if theCarry flag is on, a 6 is added to them.

The Carry flag, of course, indicates that the hexadecimal value of the bytebefore the instruction, when translated to BCD, is too large to fit in one byte.


Mallika Verma


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LOGICAL GROUP


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80

LOGICAL GROUP

This group of instructions provides the decision-making ability of the 8085, and includes some

logically oriented utility instructions as well.

By using these instructions, the condition flags

may be set so that they can be tested by Jump-on-condition instructions.

Unless otherwise noted, all the condition flags areaffected.

Mallika Verma

LOGICAL GROUP


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81

AND INSTRUCTIONS:

ANA r and ANA M instructions perform a logical And functionbetween the specified byte, either in a register or in the addresscontained in the H&L registers, and the contents of the accumulator.

The accumulator must first be loaded with an initial value.

The And function occurs on a bit-by-bit basis. The low order bit of

the specified byte is Anded with the low order bit of the A register; ifboth the bit from the outside byte AND the bit from the A register area 1, the bit in the A register is left as a 1. If either the bit position ofthe outside byte or the bit position in the A register, or both,contained 0s, that bit position in the A register is reset to 0. Identical

actions occur on the other seven bit positions at the same time. The result, left in the accumulator, is a bit pattern which indicates,

with 1s left on, in which positions of the bytes both the A registerand the outside byte contained 1s.

This is valuable for testing the conditions of specific bits within abyte, and reacting accordingly.

All condition flags are involved, but the Carry flag is always clearedby an And.


Mallika Verma


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82

LOGICAL GROUP

ANA r, ANA M

Cycle 1, M


Flags S, Z , P are modified to

reflect the result of operation.

Cy is reset and AC is setHex Code

Mallika Verma

A7A6A5A4A3A2A1A0

AMLHEDCB

LOGICAL GROUP


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83

AND IMMEDIATE:The ANI d8 instruction allows the programmer to match the byte in the

accumulator with a fixed mask byte, contained in the second byte of

the instruction.

The A register must first be loaded with the byte to be tested.The Anding function occurs exactly as Explained for the ANA

instruction.

All condition flags are involved, but the Carry flag is cleared.

Mallika Verma

ANI, d8

Cycle 2

T state 7

Address register

Flags S, Z , P are modified to reflect the

result of operation. Cy is reset and AC is set

Hex Code E6

LOGICAL GROUP


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84

OR INSTRUCTIONS:

The ORA r and ORA M instructions perform inclusive Ors between the specifiedbyte, either in a register or in the address contained in the H&L registers, and thecontents of the accumulator.

The A register must be loaded with the first , value prior to the execution of theseinstructions.

The Or function occurs on a bit-by-bit basis. The low order bit of the outside byte isOred with the low order bit of the A register; if either the bit from the outside byteOR the bit from the A register is a 1, or both, that bit position is set to a 1 in the Aregister. If neither bit position from the outside bit or the A register is a 1, a 0 is

loaded into that bit position of the A register.

Identical operations occur on the other seven bit positions of the bytes.

The result, left in the accumulator, is a bit pattern in which a 1 exists in any bit

position in which either of the bytes also had a bit set.

All condition flags are affected, but the Carry and Auxiliary Carry flags are alwayscleared.

Mallika Verma

LOGICAL GROUP


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85

LOGICAL GROUP

ORA r, ORA M

Cycle 1, 2


Flags S, Z , P are modified toreflect the result of operation.

Cy and AC are resetHex Code

Mallika Verma

B7B6B5B4B3B2B1B0

AMLHEDCB

LOGICAL GROUP


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86

LOGICAL GROUP

OR IMMEDIATE:

The ORI d8 instruction allows the programmer to OR the contents of

the accumulator with data contained in the second byte of the

instruction. The first byte must be loaded into the A register prior to execution of

the instruction. All condition flags are affected, but the Carry and Auxiliary Carry

flags are always cleared.

Mallika Verma

ORI, d8

Cycle 2

T state 7

Address registerFlags S, Z , P are modified to reflect the

result of operation. Cy and AC are reset

Hex Code F6

LOGICAL GROUP


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87

LOGICAL GROUP

EXCLUSIVE OR INSTRUCTIONS:

XRA r and XRA M instructions perform exclusive Or functionsbetween a specified byte, either in a register or in a byte containedin the address in the H&L register, and the contents of theaccumulator.

The A register must be loaded with the first byte prior to theexecution of the instruction.

The Exclusive Or occurs on a bit-by-bit basis. Identical operations occur on the other bit positions of the bytes at

the same time. T

he results are left in the accumulator, which contains a bit pattern

with 1s set where there was a 1 in either the A register or theoutside byte, and 0s set where there was either 0s in both bytes or1s in both bytes, in the same bit position.

All condition flags are affected, but the Carry and Auxiliary Carryflags are always cleared.

Mallika Verma

LOGICAL GROUP


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88

LOGICAL GROUP

XRA r, XRA M

Cycle 1, 2


Flags S, Z , P are modified toreflect the result of operation.

Cy and AC are resetHex Code

Mallika Verma

AFAEADACABAAA9A8

AMLHEDCB

LOGICAL GROUP


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89

EXCLUSIVE OR IMMEDIATE:

The XRI d8 instruction allows the programmer to perform an Exclusive Or

between a mask byte stored as the second byte of the instruction and the

contents of the accumulator.

The first byte must be loaded into the A register prior to the execution of the

instruction.

The Exclusive Or function occurs on a bit-by-bit basis exactly as outlined

above.

All the condition flags are affected, but the Carry and Auxiliary Carry flags

are cleared.

Mallika Verma

XRI, d8

Cycle 2

T state 7Address register

Flags S, Z , P are modified to reflect the

result of operation. Cy and AC are reset

Hex Code EE

COMPARE INSTRUCTIONS


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90

COMPARE INSTRUCTIONS

COMPARE INSTRUCTIONS:

The CMP r and CMP M instructions compare the contents of thespecified byte, either in a register or in the address contained in the

H&L registers, to the contents of the accumulator. This is accomplished by subtracting the byte in the register/ memory

from the contents of the accumulator.

The contents of the accumulator remain unchanged, and the actualanswer of subtraction is lost.

The condition flags are all affected, and are set to indicate theconditions of the lost answer.

If A < reg/mem Cy flag is set

If A = reg/mem Zero flag is set

If A > reg/mem CY and Zero flags are reset

Compare Instructions


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91

p

CMP r, CMP M

Cycle 1, 2

T state 4, 7

Address register

Flags S, AC , P are also modifiedin addition to CY and Zero

Hex Code

BFBEBDBCBBBAB9B8

AMLHEDCB

COMPARE INSTRUCTIONS:


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COMPARE IMMEDIATE:

The CPI d8 instruction compares the contents of the accumulator to a

fixed value provided by the second byte of the instruction.

The first value must be loaded into the A register prior to the execution

of the instruction.The function occurs by a subtraction with lost answer, as described

above.

The contents of the A register are left unchanged.

CPI, d8

Cycle 2

T state 7Address register

Flags S, Z , P are modified in

addition to CY and Z

Hex Code FE

ROTATE INSTRUCTIONS:


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ROTATE INSTRUCTIONS:

The Rotate Left (RLC) and Rotate Right (RRC)instructions rotate the accumulators contents one bitposition left or right, respectively.

In the RLC, all the bits move one position to the left; thehigh order bit which is shifted out of the A register ismoved around to the low order bit position. It is alsomoved to the Carry flag.

In the RRC, all the bits move one position to the right;the bit shifted out of the low order position of the Aregister is moved around to the high order position. It isalso moved to the Carry flag.

Thus, the Carry flag in either case indicates whether a bitwas shifted out of the accumulator.

Only the Carry flag is affected by these instructions.

ROTATE INSTRUCTIONS


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94

ROTATE THROUGH CARRYS:

The RAL and the RAR instructions rotate the accumulatorscontents one bit position left or right, respectively.

Unlike the rotates above, however, these instructions use

the Carry flag as a ninth bit in the circle.In the RAL, the bits in the A register are shifted left one

position; the high order bit moved to the Carry flag; theCarry flag contents is moved to the low order position of

the A register.In the RAR, the bits in the A register are shifted right one

position; the low order bit is moved to the Carry flag; theCarry flag is moved to the high order position of the A

register.Only the Carry flag is affected.

ROTATE INSTRUCTIONS


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95

ROTATE INSTRUCTIONS

RLC, RRC, RAL, RAR

Cycle 1

T state 4

Flags CY

1F170F07

RRCRALRRCRLC

HEX Codes

ROTATE INSTRUCTIONS


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96

ROTATE INSTRUCTIONS

RAL instruction

D0D7

CY

RAR Instruction

D0D7

CY

D0D7

CY

RLC Instruction

CY

D0D7

RRC Instruction

TEST INSTRUCTIONS


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COMPLEMENT ACCUMULATOR:

The Complement Accumulator (CMA) instruction provides a 1scomplement of the 8 bits in the A register

No condition flags are affected.

CARRY INSTRUCTIONS:

The Complement Carry (CMC) and Set Carry (STC) instructionsallow direct control of the Carry flag by the programmer.

The CMC will change the flag from 1 to 0, or 0 to 1, depending uponits initial condition.

The STC forces the flag to a 1, regardless of its previous state.

No other flags are affected.

170F07

STCCMCCMA

Branch Instructions


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Branch Instructions

This group of instructions permits the programmer toalter the flow of program execution from a normalstraight line.

There are two major types of these instructions in the8085.

The first type is the Jump, in which the flow is alteredwith no intention of returning to the place where theJump occurred.

The second type is the Call, which provides linking, viathe system stack, to save the address of the nextinstruction following the Call, proceed to a subordinateroutine, and return to the saved address when thatroutine is completed.

Mallika Verma

Branch Instructions


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99

Branch Instructions

Jumps and Calls may be conditional or unconditional

An unconditional Jump or Call causes the function to beexecuted absolutely.

The conditional Jump or Call causes the function to beexecuted if the conditions specified are met. In the firstbyte of these instructions, three bits labeled XXX willcontain a code which specifies the conditions to betested. These may be specified by the programmer inassembly language by putting together a mnemoniccomposed of a J, for Jump, or a C, for Call, followed by

one or two more characters which specify the conditionsto be tested. The breakdown follows:

Jump Instructions


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Jump Instructions

JUMP INSTRUCTIONS:

The Jump (JMP addr16) and Jump Conditional (JXXaddr16) instructions allow program flow to be altered by

loading the contents of the two bytes following theinstruction to be loaded into the Program Counter. Thenext instruction to be fetched, therefore, will the first of

the new routine. The JMP instruction is unconditional; the Jump occurs

absolutely.

The JXX instruction will alter program flow if theconditions specified by the XX" bits are true; otherwise,program flow remains in a straight line.

No condition codes are affected.

JUMP INSTRUCTIONS


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101

FA a16

F2 a16

EA a16

E2 a16

DAa16

D2 a16

CA a16

C2 a16

Opcode

S = 1JM, a168

S = 0JP, a167

P = 1JPE, a166

P = 0JPO, a165

CY =1JC, a164

CY = 0JNC, a163

Z = 1JZ, a162

Z = 0JNZ, a161

FlagConditionS.No.Unconditional JumpJMP addr 16

Cycle 3

T state 10

Address ImmediateFlags none

Hex Code C3

Conditions attached with Jump

Conditional Jump

JXX addr 16

Cycle 3

T state 10

Address ImmediateFlags none

Subroutine Instructions


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102

CALL INSTRUCTIONS:

The CALL addr16 and the conditional CXX addr16 instructions allow a subroutine tobe invoked, with the address of the next sequential instruction saved for later ref.

TWO STEPS1.The Call will move the high byte of the PC into the address pointed to by theStack Pointer minus 1, and the low byte of the PC into the address below that.

The SP is then decremented by two, to update it to the new stack position.

2.The two bytes following the Call instruction will then be moved to the PC, with thesecond byte of the instruction containing the low order byte of the address, and thethird byte of the instruction containing the high order byte of the address.

Thus, the address of the instruction following the Call is saved on thesystem stack, and the address of the first instruction of thesubroutine is fetched next. The Call Conditional executes exactly thesame way, providing that the conditions specified by the XX bits aretrue.

None of the flags are affected.

CALL INSTRUCTIONS


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103

FC a16

F4 a16

EC a16

E4 a16

DCa16

D4 a16

CC a16

C4 a16

Opcode

S = 1CM, a168

S = 0CP, a167

P = 1CPE, a166

P = 0CPO, a165

CY =1CC, a164

CY = 0CNC, a163

Z = 1CZ, a162

Z = 0CNZ, a161

FlagConditionS.No.

Unconditional Call

CALL addr 16Cycle 5

T state 18

Address Imm/reg

indirectFlags none

Hex Code CD

Conditions attached with Call

Conditional CallCXX addr 16

Cycle 5

T state 18

Address Imm/reg

indirect

Flags none

RETURN INSTRUCTIONS


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104

RETURN INSTRUCTIONS:

The RET and Return Conditional (RXX) instructions provide a means,at the end of a subroutine, of resuming program execution at theinstruction following the Call instruction which invoked the

subroutine.These instructions are placed at the end of the subroutine, not in the

body of the main program.

When encountered, the Return will move the byte pointed to by theStack Pointer into the lower byte of the PC, the next byte higher inRAM to the higher byte of PC, and add 2 to the contents of SP.

Thus, the address of the instruction following the Call, previously savedon the stack, is now in PC, and will be fetched next.

The Return Conditional executes exactly the same way, providing that

the conditions specified by the XX bits are true.

The stack pointer is updated accordingly.

None of the flags are affected.

Return Instructions


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105

F8 a16

F0 a16

E8 a16

E0 a16

D8a16

D0 a16

C8 a16

C0 a16

Opcode

S = 1RM, a168

S = 0RP, a167

P = 1RPE, a166

P = 0RPO, a165

CY =1RC, a164

CY = 0RNC, a163

Z = 1RZ, a162

Z = 0RNZ, a161

FlagConditionS.No.

Unconditional RET

RETCycle 3

T state 10

Address reg indirect

Flags none1 Byte

Hex Code C9

Conditions attached with Return

Conditional ReturnRXX

Cycle 3

T state 12

Address reg indirectFlags none

1 Byte

JUMP INDIRECT INSTRUCTIONS


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106

JUMP INDIRECT INSTRUCTIONS

The Jump H&L Indirect instruction

PCHL moves the contents of the H&L registers into the Program Counter

The contents of H&L must be previously built, and may be assembled byother parts of the program to the advantage of the programmer.

The original contents of the PC are destroyed, so this is a one-way jump.

PCHL

Cycle 1

T state 6

Address register

Flags none

1 Byte

Hex Code E9

RESTART INSTRUCTIONS


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The RST n instruction Are special unconditional call instructions

One byte instructions

Are software interrupts provides part of the vectored interrupt system by which

any one of eight different levels of interrupt may stop

the execution of the program currently in progress by saving the address of the next instruction onto the stack,and then jump to any one of eight different locations in lowcore, depending upon the contents of the bits marked n inthe instruction.

as many as eight different external events i.e. I/O devices,etc., may ask for service;

Software Interrupts


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108

Software Interrupts

RST n

Cycle 3

T state 12


Flags none

One byte

1 Byte

FFRST 78

F7RST 67

EFRST 56

E7RST 45

DFRST 34

D7RST 23

CFRST 12

C7RST 01

OpcodeInstructionS.No.

The default interrupt for the P in the Lab is RST 5 (EF)

MACHINE CONTROL GROUP


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109

This group is a collection of miscellaneous instructionswhich control bodily functions of the P, or provideutilities.

PUSH AND POP:

Push Register Pair (PUSH rp) and Pop Register Pair (POP rp)

allow programmers to manipulate the system stack. The Push will place the contents of the BC, DE, or HL registerpairs onto the stack, and update the SP accordingly.

The Pop instruction will return the last two items on the stack

to the specified register pair, and update the SP. The condition flags are not affected;

The SP register pair may not be specified.

STACK Instructions


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110

E5D5C5

PUSH HPUSH DPUSH B

PUSH rpSP-1 rhSP -2 rlSP SP-2Cycle 3T state 12


Flags none

One byte

LXI SP a16 is always

before PUSH

Data transfer instruction

POP rprl SPrh SP +1SP SP+2Cycle 3

T state 10


Flags none

One byte


E1D1C1

POP HPOP DPOP B

Processor Word Instructions


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111

PSW INSTRUCTIONS:

PUSH PSW and the POP PSW instructions will allow the programmer to save thecontents of the A register and of the condition flags on the stack, or to retrievethem from the stack.

The Processor Status Word (PSW) of the 8085 is defined as a "Flag Byte" whichcontains the condition flag bits in a specific sequence:

S Z X AC X P X CY

The contents of the A register is also saved as part of the PSW.

When the PUSH PSW is encountered, the contents of the A register is pushed

onto the stack first, followed by the Flag byte.The SP is then updated.

When the POP is executed, the Flag byte is retrieved first, and the bits areloaded into their proper flip-flops.

The A register is then loaded with the next byte retrieved.

This allows programmers to save conditions at the beginning ofsubroutines so that the execution of the instructions within theroutines will not alter the conditions under which the original

program was operating.

PUSH and POP PSW


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112

PUSH and POP PSW

PUSH PSWSP-1 ASP -2 Flag ContentSP SP-2Cycle 3

T state 12


Flags noneOne byte

LXI SP a16 is always

before PUSH

Data transfer instructionOpcode F5

POP PSWFlag content SPA SP +1SP SP+2Cycle 3

T state 10

Address reg indirectFlags Z, S, P, CY, AC

One byte


Opcode E1

Stack Exchange Instructions


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113

EXCHANGE STACK TOP with H&L (XTHL) instruction

causes the contents of the H&L registers to be exchanged with thetwo bytes which are currently on the top of the system stack.

These will be the last two bytes pushed.

It is a two-way instruction; the stack receives the original contents ofH&L, while H&L receives the two bytes from the stack.

The contents of SP remain unchanged.

No flags are affected.

XTHLL SPH SP +1Cycles 5

T state 16

Address reg indirectFlags none

Opcode E3



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114


MOVE H&L TO SP: SPHL instruction

Will directly move the contents of the H&L registers into theStack Pointer

the original contents of SP are destroyed.

This may be used to permit multiple stacks to exist at one time in

the system.

No flags are affected. SPHLSPHLCycle 1

T state 6

Address register

Flags none

One byte

Opcode E1

I/O INSTRUCTIONS


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The IN port and OUT port instructions allow the P tocommunicate with the outside world.

In both cases, the address byte of the device to be used

is contained in the byte following the instruction. This byte is presented at once to both the upper and

lower bytes of the A0-A15 address lines.

In the case of IN, the byte accepted on the D0-D7 datalines by the P is placed in the A register. For the OUT, the byte to be sent on the data lines is

placed in the A register prior to execution of the

instruction. No flags are affected.

These are two byte instructions

I/O INSTRUCTIONS


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116

IN Port (8bit

address)

Cycle 3

T state 10

Address Direct

Flags none

Two byte

Op code DB port

OUT Port (8 bit

address0

Cycle 3

T state 10

Address Direct

Flags none

Two byte

Op code D3 Port

INTERRUPT CONTROL INSTRUCTIONS


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117

Enable Interrupts (EI) and Disable Interrupts(DI) instructions allow the P to permit or denyinterrupts under program control

For the EI, the interrupts will be enabled following thecompletion of the next instruction following the EI.

This allows at least one more instruction, perhaps a RET

or JMP, to be executed before the P allows itself to againbe interrupted.

For the DI, the interrupts are disabled immediately.

No flags are affected.

Enable or Disable all interrupts except TRAP

INTERRUPT CONTROL INSTRUCTIONS


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118

HALT and NO-OP: The Halt (HLT) and No-Operation(NOP) instructions serve general utility purposes

The Halt will stop the processor from further execution; itcan be restarted again only by an interrupt.

A reset signal applied to the P will abort the Halt.The P may enter a Hold state, as the result of another

device wanting the bus, from a Halt, but will return to the

Halt state when the Hold is canceled.

The NOP is simply a one-byte long place holder, which ispassed through automatically without any data motion or

action of any kind.It is used primarily as a programmers aid in saving space

within language programs for later use.

Halt and NOP


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119

EI and DI

Cycle 1

T state 4

Flags none

One byteOp code FB, F3

HLT

Cycle 1

T state 5

Flags none

One byteOp code 76

NOP

Cycle 1

T state 4

Flags none

One byteOp code 00

Machine Control Group

RIM and SIM Instructions


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120

The Read Interrupt Mask (RIM) and Set

Interrupt Mask (SIM) instructions are used to

service both the extended interrupt system of

the 85 and the Serial Input Data (SID) and

Serial Output Data (SOD) pins on the device.

While these items are both serviced by the same instructions, theyare not electrically or logically related, and should not be confused

RIM Instructions


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121

READ INTERRUPT MASK (RIM)

This instruction permits the system to examine the interrupt maskby loading into the A register a byte which defines the condition ofthe mask bits

For the mask able interrupts, the condition of the interrupts pendingfor the mask able interrupts, the condition of the Interrupt Enableflag, and the condition of the Serial Input Data (SID) pin on the P

The format of the Accumulator is

M5.5M6.5M7.5IEI5.5I6.5I7.5SID

D0D1D2D3D4D5D6D7

The Interrupt Mask is a group of bits which can be accessed by RIM, SIMinstructions via the accumulator.

Read Interrupt Mask


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122

From the D0 end of the byte, the purpose of these bits areas follows:

INTERRUPT MASK BITS D0, D1, D2: These bits indicate whetherthe interrupts for 5.5, 6.5, and 7.5 are masked on or off. The bits areset to a 1 for disabled, and 0 for enabled. It is a valuable tool, sinceone program section may not necessarily know what a secondsection is doing or expecting.

INTERRUPT ENABLE BIT D3: This bit corresponds to theInterrupts Enabled. It is set or reset by the Enable Interrupts orDisable Interrupts OP codes

M5.5M6.5M7.5IEI5.5I6.5I7.5SID

D0D1D2D3D4D5D6D7

Read Interrupt Mask


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123

INTERRUPTS PENDING BITS D4, D5, D6: These bits indicate

what interrupts have occurred since the last time that specific

interrupt was serviced. If interrupts 5.5 or 6.5 are masked off by bitsD0 or D1, bits D4 and D5 will not be set. Bit D6, which corresponds

to the 7.5 interrupt, will be set on to indicate that an interrupt was

requested, even if it was masked off.

SERIAL INPUT DATA BIT D7: This bit provides the condition of theSID pin. It will be 1 if the pin is high, and 0 if it is low. The software

examining this bit must have total ability to deal with whatever it

finds there.

M5.5M6.5M7.5IEI5.5I6.5I7.5SID

D0D1D2D3D4D5D6D7

Read Interrupt Mask


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124

When the RIM instruction is executed, the status of all the lines

indicated are sampled, and the resulting bit pattern is placed in the A

register. The instruction simply provides these conditions for display; it

has no affect on the bits themselves. The bits in the A register may

then be examined directly by logical instructions, or moved to a register

or memory location for safekeeping.

RIM

Cycle 1

T state 4

Flags none

One byte

Op code 20H

SIM Instructions


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125

SET INTERRUPT MASK (SIM)

This instruction is the reverse of the RIM

While the RIM simply reads the status of various lines, the SIMsets various bits to form masks or generate output data via theSOD line.

The conditions that the programmer wishes to set up must be setinto the A register exactly as desired first, then the SIM Instructionis executed.

The SIM will take the bit pattern it finds in the A registerand loadsit into the masks in the following format:

M5.5M6.5M7.5MSE7.5XSOESOD

D0D1D2D3D4D5D6D7


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Set Interrupt Mask


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127

MASK SET ENABLE BIT D3: This bit permits bits D0, D1, and D2 tobe changed. If a SIM is executed with this bit low, the condition of the

mask bits will not change. If a SIM is executed with this bit set high,

the mask bits will take on the same arrangement as those given in the

lower bits of the A register. This permits accessing of the mask byte todeal with the interrupts without affecting SOD.


D0D1D2D3D4D5D6D7

Set Interrupt Mask


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128

RST 7.5 RESET BIT D4: This bit permits the SIM instruction to

reset the interrupt pending flag indicated by bit D6 in the RIM

instruction byte. Since the 7.5 interrupt is handled somewhat more

importantly than the 5.5 and 6.5, it can indicate that it is pending via

the RIM instruction even though it is masked off. This bit allows that

pending request to be reset individually under program control.

UNDEFINED BIT D5: This bit is unused.


D0D1D2D3D4D5D6D7

Set Interrupt Mask


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129

SOD ENABLE BIT D6: This bit works in conjunction with bit D7. If itis set to 1 when the SIM is executed, the condition of bit D7, high orlow, is electrically loaded into the SOD latch, and in turn appears on

the SOD pin of the 85. If bit D6 is low, the SIMs execution has noaffect on the bit D7. This, like bit D3, allows executing SIMs toservice either interrupts or the serial I/O without affecting the other.

SERIAL OUTPUT DATA BIT D7: This bit contains the voltage level(+5 volts = 1, 0 volts = 0) which should appear at the SOD pin of the

85. If the SIM instruction is executed and bit D6 is set to 1(enabled), the level contained by D7 is forwarded to the SOD latch,which will in turn cause it to appear on the SOD pin. If bit D6 is low,the SIM instruction will have no affect on bit D7.


D0D1D2D3D4D5D6D7

Set Interrupt Mask


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130

The RESET IN line affects the flags of the interrupt masks.First, the RST 7.5 latch which catches the rising edge of the 7.5 flip-flop and

holds it till RIM instruction is reset.

Next, all three mask bits are set to a 1, which will disable all interrupts.

Lastly, the SOD latch is reset to a 0.These will effectively allow the new instructions following the Reset to take full

control of the P , without interrupts causing immediate problems.

SIM

Cycle 1

T state 4

Flags noneOne byte

Op code 30

ADDITIONAL INFORMATIONRESET SYSTEM

The 8085 generates its own Reset function upon receipt of an


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131

The 8085 generates its own Reset function upon receipt of an

asynchronous /RESET IN signal from an external source. This signal is probably generated from two sources, a Reset switch of

some kind accessible to the operator, and a Power-on Reset circuitwhich causes a reset when power is applied to system.

Receipt of /RESET IN is latched by an internal flip-flop at the risingedge of the next clock pulse (low asserted). At the beginning of thestate following the latch of /RESET IN, RESET OUT is generated to theoutside world, and the P enters T-reset cycles.

When the /RESET IN line goes high, the P will place the contents ofthe PC onto the address bus, and enter T1 of the M1 cycle for the nextinstruction. The PC was reset to all zeroes during the Reset cycle;therefore, the address appearing on the A0-A15 lines will be 0000H.

The Reset cycle does not affect the contents of any register except PC,or the arrangement of the condition flags.

The Intel documentation indicates that the occurrence of Reset isessentially asynchronous with respect to the execution of the programin process.

The results of a Reset are undetermined, and not guaranteed.

Reset Cycle


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132

The Reset cycle will reset, or turn off, the following items: Program Counter

Instruction Register

Interrupt Enable FF RST 7.5 FF

Trap FF

SOD FFThe following items are turned on, or set, by the Reset

cycle:

RST 5.5 Mask

RST 6.5 Mask

RST 7.5 Mask

INTERRUPT FACILITIES


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133

The functional items required are an InterruptRequest (INTR) pin, an Interrupt Acknowledge

(INTA) pin, an Interrupt Enable (INTE) pin, eight

interrupt vectors, and the Restart instruction

SUPPORT DEVICES FOR THE 8085

8155 : This device provides several items of general use for a small


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g85-based control environment. includes 256 bytes of RAM, two 8-bitwide parallel ports, one 6-bit wide parallel port and an interval timer.The timer is programmable, and the ports may be used for input,output, or both. The device accepts standard 8085 electricalinterface lines and operates on a single 5 volt supply.

8255:8755 EPROM WITH I/O: This device provides 2Ks worth of 8-bit bytes

of UV-erasable EPROM, and two 8-bit-wide bi-directional parallelI/O ports. It uses the 8085 electrical interface, and a 5 volt supply.

8259 Programmable interrupt controller: It handles 8 vectored interrupts

by itself, and is cascadable to a total of 64 interrupts by addingadditional 8259s to each of the first ones input lines. It requiresinitialization bytes to be sent to it before it can perform, and thesebytes can tailor its operation to a variety of conditions. It requires asingle 5 volt supply

In addition to these devices above, many Intel and non-Intel RAMs and ROMs

have been developed to provide data storage to meet every conceivable need

Documents

Microprocessor 8085 A