MicroMegas Trigger Processor Interface and Trigger Algorithms · David López Mateos, Harvard University, for the NSW trigger electronics group, nSW Design Review, February 13th,

David López Mateos, Harvard University, for the NSW trigger electronics group, nSW Design Review, February 13th, 2015

MicroMegas Trigger Processor Interface and Trigger Algorithms

‣ Interface to the detector

‣ Trigger algorithms

‣ Performance

‣ Trigger processor testing and integration

‣ Conclusions

nSW Design Review, February 2015 D. Lopez Mateos

Trigger Processor Interfaces

2

Level-1 Accepted events

algo params

TTC

BC clock

to Sector Logic

(2 streams of candidates)

6.4Gb/s each

ROD

Configurationprocessor

Monitor

processor

DCS

Sector

Logic

32 fibers(4 fibers per layer

8 layers)MM: 4.8G

sTGC: 5.28G

data tagged by BCID at source

FELIX

exceptionsstatisticssampled events

TTC

FPGA

configLL_TrigProcContext_V01

Busy

ATCA

carrier

Trigger

Processor

FPGA

on ATCA

mezzanine

card

Ethernet

ATCA

shelf mgr

IPMI

Ethernettemps

voltages

duplex fiberto FELIX

Note:

7 copies of each

stream are produced

NSW Trigger Processor context

E-links


Interfaces to the Detector

3


algo params

TTC

BC clock

to Sector Logic


6.4Gb/s each

ROD


Monitor

processor

DCS

Sector

Logic


8 layers)MM: 4.8G

sTGC: 5.28G


FELIX


TTC

FPGA


Busy

ATCA

carrier

Trigger

Processor

FPGA

on ATCA

mezzanine

card

Ethernet

ATCA

shelf mgr

IPMI

Ethernettemps

voltages


Note:

7 copies of each

stream are produced


E-links ‣ 64 strips per VMM

‣ Up to 1 trigger hit per VMM (earliest arrival hit)

‣ 32 VMMs per ADDC

‣ Up to 8 hits per ADDC per BC (1/4 of the sector)

‣ 32 fibers and ADDCs per sector

‣ 1 trigger processor per sector


Data Format

4

‣ Data transmitted from the ADDC to the trigger processor using the GBT architecture and protocol in a low-latency widebus mode (4.8 Gb/s, no forward error correction)

‣ Data packet of 112 bits provided every bunch crossing, will contain up to 8 hits per ADDC (32 VMMs), no encoding

‣ Two options considered:– VMM IDs for each trigger provided– Hit map provided (VMM ID encoding performed in the trigger processor

FPGA)

‣ The two options need to be implemented to understand performance


Data Format

5

‣ BCID: bunch crossing

‣ ART_DATA: strip number within one VMM that was hit

‣ ARTDATA_PARITY: parity of each ART_DATA 6-bit address (for error checking)

‣ HIT_CNT: Number of hits

‣ VMMID: Unique number for VMM that was hit for this ADDC

‣ HIT_LIST: single-bit list of hits (1 bit per VMM)

‣ ERR_FLAGS: Additional room for error reporting (e.g. more than 8 hits)


Fit-Based Trigger Algorithm

6

track

to IP

slope road

𝜽 (or 𝜽global)

𝛥𝜽

1. Translation of hardware addresses to global slopes, fixed to the IP

2. Determination of the presence of a multi-plane coincidence

3. Parallel calculation of average global slopes with horizontal and stereo strips, and local fit to 𝜽 with horizontal strips

4. Use of global and local slope from horizontal strips to calculate 𝛥𝜽, and global slopes from horizontal and stereo strips to calculate position (𝜽 and 𝝓)

➡ Used in most results discussed in what follows



7

‣ Incoming hits are converted to slope values using a look-up table, stored in a “finder” circular buffer

‣ Each slope road buffer is checked for coincidence every bunch crossing

‣ Upon coincidence, information is sent to the “fitters”

track

to IP

slope road


𝛥𝜽



8

‣ Fitters calculate in parallel:– Average global slope (𝜽 position at entrance of spectrometer, 𝜽 w.r.t IP)

– Average local slope (𝜽 direction at entrance of spectrometer)

– Stereo slopes (for 𝝓 calculation)‣ Filter stereo planes if there are inconsistencies

track

to IP

slope road


𝛥𝜽



9

‣ Use 𝜽 with respect to the IP and 𝜽 at the entrance of the spectrometer to

calculate 𝛥𝜽

‣ Use horizontal and stereo positions to calculate cartesian position, which gets turned into 𝜽, 𝝓 using a look up table

track

to IP

slope road


𝛥𝜽

Trigger Processor

Fitter

Calc ROICalc Mu Global(u plane slopes)

ADDC Packet DecodeCalc strip Number

Calc strip Slope(one per fiber)

FinderCollect hits in slope road

(One per “region”)

ADDC ART DataTrack Data

Track StrobeHit Data

Hit Data includes:Slope,Strip#,BXID

For each hitHit DataAHit DataB

Calc Mx Global(x plane slopes)

Mx Global

Mu Global

Track DataTrack Strobe


Calc Mv Global(v plane slopes)

Mv GlobalTrack DataTrack Strobe

Calc Mx Local

Mx LocallTrack DataTrack Strobe

Calc Delta Theta

ROI

Track DataMx GlobalMx Local

Mx GlobalMu GlobalMv Global

DTheta

Track data includes: Hit Data for each member

of a “found” track

3 Ticks 3 Ticks

2 Ticks

2 Ticks

3 Ticks

5 Ticks

4 Ticks5 Ticks

3 Ticks

Critical path total 18 clock ticks

Track data from many ‘Finders’ are multiplexed into

one ‘Fitter’



10

track

to IP

slope road


𝛥𝜽

‣ 18 clock ticks, or about 56 ns‣ 70% of resources used in a Xilinx V7

485 chip‣ Desirable upgrade to pin-compatible

Xilinx V7 690 for additional resources


Look-up Table Algorithm

11

1. Define 6 pairings of layers, use incoming hits to determine through a LUT slope of each pair

2. Slopes compared to each other and track candidate selected if enough pairs are consistent

3. Slopes averaged to obtain 𝜽 direction

of the track and similarly to obtain 𝜽 position

4. 𝝓 position calculated similarly to the previous algorithm

➡ Steps 1-3 timed to 59 ns using an FPGA implementation

1" 5" 2" 6" 3" 7" 4" 8"

Layer"Pair"Track"Candidate"

X"plane"U"plane"V"plane"

1" 6" 2" 5"

X0" X1" X2" X3"U" V"1 5 2 6 3 7 4 8 1 6 2 5

6.7$cm$

9.9$cm$

15.3$cm$

1$ 2$ 3$ 4$ 5$ 6$ 7$ 8$MM$$Layers$

Mul7plet$ Mul7plet$

18.5$cm$

DPAIR=$12.6$cm$

BC1A%

BC0A%

Layer%A%BC%hits%Shi1%

Register%

BC2@40%MHz%

BC1B%

BC0B%

Layer%B%BC%hits%Shi1%

Register%

BC2@40%MHz%

BC1A:BC1B%BC1A:BC0B%BC0A:BC1B%BC0A:BC0B%

READ%@320%MHz%

SLOPE%#0%

SLOPE%SELECT%

Hit%A%

Hit%B%

SLOPE%#63%

Hit%A%

Hit%B%

64%Slope%

CalculaHon%&%

Pre:selecHon%%

MAX%8%Hits/BC%

MATCH/SLOPE%STORAGE%

Shi1%Registers%Layer%A/Layer%B%RAW%DATA%

x%Number%of%Layer%Pairs%(6)% Slope%Select%Logic%

ROI%&%Track%Angle%%

Selected track(s)

4x31%Match%slope%bit%

BC1A:BC1B%BC1A:BC0B%BC0A:BC1B%BC0A:BC0B%

4x64%slopes%

Mi:%Match%slope%value%i%

M1% M31%

Slope%#0%

Slope%#255%

M1:M31% M1:M31%6%Layer%Pairs%

M1:M31% M1:M31%

4%BCA:BCB%combinaHons%

Mor%

OR% OR%

AND% Mor%

Selected%Slopes%

Data%ID%

Data%pointers%

Data%access%

3%Hcks% A%5%(Storage)%+%4%(Accumulate)%Hcks%

B%

1%Hcks%+1%per%track%

4%Hcks%

2%Hcks%

19%Hcks@320%MHz%A% B%

59,4%ns%From%% A%to% B%

Designed%(VHDL)%&%Simulated%XST%Synthesis%&%P&R%Virtex:7%xc7v485t%:2%speed%grade%

Slice%Registers%%%%%9%%Slice%LUTs%%%%%%%%%%%%14%%%%%%%%logic%%%%%%%%%%%%%%%%10%%%%%%%%shi1%Register%1%%%%%%%%route:thrus%%%%3%%Occupied%Slices%%%18%%%%%%%%%%%%%%%For%3%BCs%27%%%

Tunable%Logic%+/:%2%slope%bins%

x4%PR%

Match%Reset%

A

B

A B A B



12

truCT

2X,1UV 2X,2UV 3X,2UV 3X,3UV 4X,4UV

pass

/nfitn

0.97

0.98

0.99

1

1.01ηE=200 GeV, 2X,1UV, all

CT


pass

/nfitn

0.92

0.94

0.96

0.98

1ηE=200 GeV, 2X,1UV, all

CT


ent

/nfitn

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1 ηE=200 GeV, all


Ideal Efficiencies : Fit-based

13

‣ What fraction of events with some truth-level hits are fit with different coincidences?➡ Purely algorithmic‣ For all particles hitting the NSW, what fraction is fit with at least N number of hits?➡ Includes detector effects‣ For all particles creating at least 6 hits, what fraction are reconstructed with at least

N number of hits?➡Includes detector effects but only for “good” tracks, similar in LUT algorithm

‣ Simulations suggest 2X,2UV mode is background-resilient, but more realistic simulation required to establish operation mode

4(X,X)&+&(&1(U,U)&A

ND&1(V,V)&)&

3(X,X)&+&(&1(U,U)&A

ND&1(V,V)&)&

2(X,X)&+&(&1(U,U)&A

ND&1(V,V)&)&

4(X,X)&+&(&1(U,U)&O

R&1(V,V)&)&

3(X,X)&+&(&1(U,U)&O

R&1(V,V)&)&

1(X,X)&+&(&1(U,U)&O

R&1(V,V)&)&

2(X,X)&+&(&1(U,U)&O

R&1(V,V)&)&


Ideal Efficiencies: Look-up Table

14

‣ Inefficiencies at regions between modules caused by different look up tables used for different sector modules (need to devise way of recovering them)

‣ No dependence of efficiency on pT (but some loss from secondary showers expected at very high pT, from studies with fitter algorithm and E=1 TeV)

‣ Higher efficiency obtained for loser coincidence requirements


𝛥𝜽 Distributions

15

[rad]fitθ∆-15 -10 -5 0 5 10 15

-310×

track

s

0

2

4

6

8

10

12

14

16

18 rms=0.00432201E=50 GeV, 4X4UV

[rad]fitθ∆-15 -10 -5 0 5 10 15

-310×tra

cks

0

100

200

300

400

500

600

rms=0.00312018E=200 GeV, 4X4UV

[rad]fitθ∆-15 -10 -5 0 5 10 15

-310×

track

s

0

10

20

30

40

50

60

70

80rms=0.00318164

E=1000 GeV, 4X4UV

pT(𝜼=1.3)=25 GeV

pT(𝜼=2.7)=7 GeVpT(𝜼=1.3)=100 GeV

pT(𝜼=2.7)=27 GeV

pT(𝜼=1.3)=500 GeV

pT(𝜼=2.7)=135 GeV

‣ These include effects on the track upstream of the nSW

‣ Helpful to understand range of values necessary

‣ ±15 mrad seems enough to cover vast majority of events

‣ More systematic study (vs pT and 𝜼) necessary

[rad]truθ∆-fitθ∆-20 -15 -10 -5 0 5 10 15 20

-310×

norm

. are

a

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

mean=4.35e-05rms=0.00272fit mean=8.85e-06fit rms=0.00157

E=200 GeV, 4X4UV

ηall

[rad]truθ-fitθ-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

-310×

norm

. are

a

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16mean=8.68e-05rms=0.000329fit mean=9.15e-05fit rms=0.000272

E=200 GeV, 4X4UV

ηall

[rad]truφ-

fitφ

-40 -30 -20 -10 0 10 20 30 40-310×

norm

. are

a

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18 mean=0.000715rms=0.00402fit mean=0.000382fit rms=0.00232

E=200 GeV, 4X4UV

ηall


Ideal Resolution

16

‣ Resolution in 𝝓 of about 2.3 mrad, degraded significantly (to 5 mrad) when adding incoherent background

‣ 𝜽 position resolution is very high, 0.3 mrad, not affected significantly when adding incoherent background

‣ 𝛥𝜽 resolution of about 1.6 mrad, degrades to 1.7 mrad in the presence of incoherent background, confirmed with the Look-up Table algorithm


Handling Misalignments

17

‣ Five types of misalignments studied with the fit-based algorithm

‣ a, b, d and e can be corrected with extra storage of constants in step 1 (no extra CPU)

‣ c requires some additional study of necessary resources (not done yet)

‣ Missing one rotation in these studies, to be studied in the near future


Technically Handling Misalignments

18

‣ Shifts along radial direction can be corrected in original translation of addresses to slope values


Technically Handling Misalignments

19

‣ z-shifts need also updates in constants necessary for local slope

‣ Tilts can be fixed in the same way (16 constants per layer)


Effects of Misalignments

20

‣ Effects of misalignments studied corresponding to up to 5 mm mistakes in relative placement of detector planes

‣ Impact on efficiency is negligible (but biases in 𝜽, 𝝓 can impact matching to Big Wheel)

‣ Impact on theta and phi position resolution is small for all misalignments (never bigger than 4%)

‣ For 𝛥𝜽, degradation can be large, up to 80% for the rotation for which no correction has been studied yet (making 𝛥𝜽 of about 3 mrad)

[mrad]backφ ∆

0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5

no m

isal

σ/truθ

∆-fitθ

∆σ

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9E=200 GeV, 4X4UV

ηall


Current Test Set-up

21

‣ Work on MM trigger processor firmware using evaluation board with Xilinx Virtex 7 485T and ADDC emulator

‣ Using same ART data as used for simulations, and an implementation of the GBT deserialization in the FPGA

‣ Currently working on the integration of the BNL ADDC with an ART pattern generator

ART Pattern Generator(VC707 Development Board)

Trigger Processor(VC707 Development Board)

ADDC ART Data(GBT Fiber)

Ethernet

BNL ADDCVMM ART Data(LVDS Mini SAS)

ART Pattern Generator(VC707 Development Board)

Trigger Processor(VC707 Development Board)

ADDC ART Data(GBT Fiber)

Ethernet

BNL ADDCVMM ART Data(LVDS Mini SAS)


Current Test Set-up

22

‣ Mezzanine card developed to connect FMC output connectors from development board to MiniSAS in ADDC card

ART pattern generator

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Future Test Set-ups

23

‣ Cosmic ray set up at Harvard:– Provides muons of above 0.8 GeV with 1.5 ns time resolution– Not subject to test-beam schedules and allows for quick development iterations– Can integrate trigger testing boards easily since development happens on site

‣ MSW:– Test the full chain with prototype electronics at 40 MHz and low background levels– ART data recorded, can be later fed to pattern generator

‣ Vertical slice and test beams atCERN (see Joao’s talk)


Conclusions

24

‣ Good progress on definition of algorithms, and testing with evaluation boards

‣ Efficiency is very high and position resolution also

‣ 𝛥𝜽 resolution is closer to 2 mrad than 1 mrad (just from geometry considerations)

‣ Misalignments have a large impact on 𝛥𝜽 resolution, corrections for most types do not impact latency

‣ For certain rotations, corrections and impact on resources need to be studied

‣ Background effects are not too significant, but more realistic background simulation is highly desirable

‣ FPGA implementation is evolving with the algorithm development, but a large focus of the current effort is on integration and testing

‣ More sophisticated testing is planned as a natural evolution of current testing efforts

BACK-UP SLIDES


Trigger Processor and ADDC

26


Timing of Algorithm

27

Trigger Processor

Fitter

Calc ROICalc Mu Global(u plane slopes)

ADDC Packet DecodeCalc strip Number

Calc strip Slope(one per fiber)

FinderCollect hits in slope road

(One per “region”)

ADDC ART DataTrack Data

Track StrobeHit Data

Hit Data includes:Slope,Strip#,BXID

For each hitHit DataAHit DataB

Calc Mx Global(x plane slopes)

Mx Global

Mu Global



Calc Mv Global(v plane slopes)

Mv GlobalTrack DataTrack Strobe

Calc Mx Local

Mx LocallTrack DataTrack Strobe

Calc Delta Theta

ROI

Track DataMx GlobalMx Local

Mx GlobalMu GlobalMv Global

DTheta

Track data includes: Hit Data for each member

of a “found” track

3 Ticks 3 Ticks

2 Ticks

2 Ticks

3 Ticks

5 Ticks

4 Ticks5 Ticks

3 Ticks

Critical path total 18 clock ticks

Track data from many ‘Finders’ are multiplexed into

one ‘Fitter’

A : Incoming hits are converted to slope values

J : Calculate delta theta

K : Calculate cartesian

slopes

I: Filter background from stereo hits

E : Calculate local slope

F : Calculate global X slope

C : Check buffer for coincidence

B : Store hits in a buffer where address = (slope, plane, BC)cycles every BC, 2 BC deep

G : Calculate global U slope

H : Calculate global V slope

X strips X slopes U and V slopesV slopesU slopes

global U slope global V slope stereo validation

stereo global slopesglobal X slope

K : Lookup ,

(m_x,m_y)

D: Read Track from buffer and send components

Dtheta cut?

delta theta

local X slope

M: Abandon Fit

hit = (strip number, plane, slope)

slope road index to read

Incoming hit signals

L : Trigger Signal Output

local slope <0

delta theta too large

could cut if low

(not implemented)

block_detailed_v02


Misalignment Studies

28


Block Diagram

29


Slope Roads

30


Local Slope Calculation

31

θ

“Local” implies that the fit is not influenced by the IP

Note: Given 4 X-planes, there are 11 hit combinations, assuming N>1

Pre-calculated and stored in a reference table


𝛥𝜽 Calculation

32

θ θ0

We can now cut on delta_theta to filter out background tracks that are not originating from the vicinity of the IP

The error introduced by the approximation is <4%


Cartesian Slope Calculation

33

average

Note: Table (or mesh grid of cartesian slopes superimposed on detector) will be tuned to specified ROI resolution required

Reference table

ROI

A=csc(1.5°)B=cot(1.5°)



34

PR##1#

PR##2#

PR##3#

PR##0#

Z#

8#layers#11°#

30°#

1# 5#

Layer#Pair#

1#strip#

#Z#angle#aperture#(α<#θ)#

#

D0#

D2#D1#

DPAIR#

θ#

α#

D2=DPAIR(tanα#–#tanθ)##

1 5

MM""Layers"

Interac-on"Point"

z"

PR"#1"

Projec-ve"PR"#1"

PR"#1"

PR"#2"

PR"#3"

PR"#0"

)θ

)θ

SLOPE&SELECT&

#strip&Layer&&5&

1& 5&

Layer&Pair&

1&strip&

D2&

DPAIR&

#strip&Layer&&1&

Aperture&&&Offset&(common&to&a&Panel&Region)&

LUT&MATCH&SLOPE&

MATCH&

Hit&Offset&

1 5


Look-up Table Algorithm Performance

35

rms=1.7 mrad


Monitoring and Offline Information

36


algo params

TTC

BC clock

to Sector Logic


6.4Gb/s each

ROD


Monitor

processor

DCS

Sector

Logic


8 layers)MM: 4.8G

sTGC: 5.28G


FELIX


TTC

FPGA


Busy

ATCA

carrier

Trigger

Processor

FPGA

on ATCA

mezzanine

card

Ethernet

ATCA

shelf mgr

IPMI

Ethernettemps

voltages


Note:

7 copies of each

stream are produced


E-links

‣ ART data and processor results also sent to ROD upon L1 acceptance, buffer to keep this necessary for the L1 latency

‣ Additional ancillary functions implemented for monitoring purposes (see Lorne’s talk)


Configuration

37


algo params

TTC

BC clock

to Sector Logic


6.4Gb/s each

ROD


Monitor

processor

DCS

Sector

Logic


8 layers)MM: 4.8G

sTGC: 5.28G


FELIX


TTC

FPGA


Busy

ATCA

carrier

Trigger

Processor

FPGA

on ATCA

mezzanine

card

Ethernet

ATCA

shelf mgr

IPMI

Ethernettemps

voltages


Note:

7 copies of each

stream are produced


E-links

‣ Several configuration parameters for trigger processor and algorithm

‣ Configured through Ethernet or an e-link from FELIX

‣ More information in Lorne’s talk


Background Simulation

38

‣ Important work on background simulation ongoing (see D. Denys et al. talk)

‣ For performance studies, using non-coherent background extrapolated from Phase-1 LOI

‣ Other limitations exist in the simulation (e.g. implementation of neutron response in current and upgrade detectors)

5000

10000

15000

Hit

Rat

e [H

z/cm

2 ]

100 150 200 250 300 r[cm]

[*] ATL-U

PGR

AD

E-INT-2014-001

https://indico.cern.ch/event/343852/contribution/11/material/0/0.pdf

https://cds.cern.ch/record/1753329


MM Trigger Algorithms

39

‣ Finders are dynamically allocated and pre-select track candidates

‣ Global slope calculated from average θ of horizontal strips, local slope from a fit

‣ Δθ comes from fitter, ROI from LUT using stereo strip global slopes

[*] Harvard, ATL-UPGRADE-INT-2014-001

[*] Saclay, see S. Hassani's talk for details

‣ Calculate all pair-wise slope combinations using LUT

‣ Compare these and their compatibility with IP to select track candidates

‣ Use output to calculate ROI and Δθ

https://cds.cern.ch/record/1753329

https://indico.cern.ch/event/329834/session/1/contribution/2/material/slides/0.pdf


MM Trigger Processor Emulation

40

MM Trigger processor

GBT

des

eria

lizer

Athena singlemuon events

‣ Work on MM trigger processor firmware using Xilinx Virtex 7 evaluation board

‣ Athena events used in performance studies also used to test firmware

‣ Latency studies described in detail in Joao’s talk

‣ Impact of misalignments on the latency need to be evaluated and will cause algorithmic modifications


MM Trigger Processor Emulation

41

ART Pattern Generator MM Trigger processor

GBT

GBT

des

eria

lizer

Athena singlemuon events

‣ Working on local integration at Harvard using an ART pattern generator (see T. Lazovich talk)

‣ Ready for testing as soon as ADDC is available‣ Will, in parallel, use an evaluation board to save test beam trigger data with ADDC

https://indico.cern.ch/event/344459/contribution/6/material/slides/0.pdf

Documents

MicroMegas Trigger Processor Interface and Trigger Algorithms · David López Mateos, Harvard University, for the NSW trigger electronics group, nSW Design Review, February 13th,