Microelectronics Circuits for Neuronal Sensing and Stimulation

Stimulation
Dissertação para obtenção do Grau de Mestre em
Engenharia Eletrotécnica e de Computadores
Júri
Presidente: Prof. Doutor Marcelino Bicho dos Santos Orientador: Prof. Doutor Moisés Simões Piedade Co-Orientador: Prof. Doutor Jorge Ribeiro Fernandes Vogais: Prof. Doutor João Goes Eng. Tiago Miguel Lopes da Costa
Maio de 2012
ii
i
Acknowledgments
I would like to thank Prof. Moisés Piedade, for the opportunity of using this theme in my theses,
and for his guidance.
I would also like to acknowledge Eng. Tiago Costa that supervised the progress of the entire
work, often providing very useful and practical knowledge.
Prof. Jorge Fernandes and Prof. Marcelino Santos must also be mention because, they not only
introduced me to Microelectronics in their courses at IST, but also, during the course of this
thesis, provided solutions to many problems that I had to face.
I want to acknowledge my colleagues from IST with whom I shared many pleasant times and
studying hours. With a special mention to my colleague Carlos Paiva, who was present during
the final stage of this thesis and provided significant support and a pleasant working
environment.
I must also thank my parents Francisco and Cristina, for their unconditional support, and for
giving me the opportunity to have this kind of academic education.
Finally, I thank Liliana Coroas, who had to abdicate of my presence many times, endured the
situation, and still accepted to be my fiancée. Without her, these years would all have been less
interesting, and a lot more difficult.
ii
iii
Abstract
In this thesis, a Microelectronic Circuit for Neural Stimulation is presented. This circuit is to
be used in a Visual Neuroprosthesis and connected to an array of electrodes that will stimulate
the visual cortex. Since some parts of the circuit are going to be replicated, the area of such
parts is a major concern.
The circuit consists of two main blocks. The first is a multibias digital to analog converter
(DAC) which in turn can be divided in a multibias generator, and the DAC itself that converts the
five given bits into a value of the analog current scale. The second is a Biphasic current Output
Amplifier that will create a biphasic current impulse to stimulate the cortex cells.
In the first block, only the DAC is to be replicated, not the biasing circuit. There resides the
main advantage of using the multibias DAC topology in this project. To decrease the DAC area
the bit weights are generated by biasing voltages generated in a single biasing circuit, allowing
each DAC to have unitary sized transistors. This makes a great difference when the block that
was reduced and simplified is replicated many times (up to 1024 or more), whereas the biasing
circuit is shared by all.
In the second block, where the biphasic impulse is created, there is a four times output
gain that allows the circuit behind to be roughly four times smaller and the reference current to
be four times smaller thus lowering the total power consumption and area.
The circuit is implemented in AMS 0.35 µm technology, and the section that will be
replicated has an area of 29 x 83.2 µm 2 .
Keywords: multibias DAC, Neural Stimulation, Visual Neuroprosthesis, Biphasic stimulation.
iv
v
Resumo
Nesta Tese é apresentado um circuito realizado em microeletrónica que tem como objetivo
a estimulação neuronal. Este circuito vai ser usado numa Prótese Visual e ficará ligado a uma
matriz de implantes que irão estimular o córtex visual.
O Circuito é composto por dois blocos principais. O primeiro é um conversor analógico
digital (DAC) no qual se utiliza uma topologia multibias. Este bloco pode ser dividido em duas
partes fundamentais, o gerador das tensões de polarização (bias voltages), e o próprio DAC
que converte os cinco bits que lhe são fornecidos, num dos valores da escala de correntes (0-
100 µA). O segundo bloco é amplificador de saída que produzirá um impulso de corrente
bifásico, que por sua vez irá estimular as células do córtex.
No primeiro bloco, apenas o DAC vai ser replicado. Nesse facto reside a principal vantagem
de se utilizar uma topologia multibias. Para diminuir a área do DAC o peso dos bits é gerado
através de várias tensões de polarização que são geradas no circuito de polarização. Isso
permite que cada DAC tenha transístores de tamanho unitário. Esta vantagem faz uma grande
diferença quando o DAC de tamanho reduzido é replicado muitas vezes (1024 ou mais),
enquanto o circuito de polarização é partilhado por todos.
O segundo bloco, onde é gerado o impulso bifásico, tem um ganho de quatro vezes, o que
permite que os circuitos que são colocados antes sejam aproximadamente quatro vezes mais
pequenos, e diminui também quatro vezes as correntes de referência. Isso permite uma
diminuição da área e do consumo de energia.
O circuito foi implementado na tecnologia AMS 0.35 µm e a secção que vai ser replicada
tem uma área de 29 x 83.2 µm 2 .
Palavras-chave: Estimulação Neural, impulso bifásico, multibias, Prótese Visual.
vi
vii
Contents
1.3 Thesis objective ............................................................................................................5
1.4 Thesis Outline ...............................................................................................................7
2 DAC Design ........................................................................................................................10
2.1.1 Common binary weighted DAC vs. multibias DAC .............................................11
2.1.2 Multibias DAC advantages..................................................................................13
5.2.4 Full circuit photograph ........................................................................................60
5.4 Conclusions ................................................................................................................65
Appendix ....................................................................................................................................80
F. Charge and Discharge steps of DAC 16 .........................................................................85
G. Photograph of the fabricated chip ...................................................................................86
ix
List of Figures Figure 1.1: On the left: Microelectrodes Matrix; On the right: Single electrode in the neural
tissue. ...........................................................................................................................................4
Figure 1.3: Diagram of one electrode stimulator. ..........................................................................7
Figure 1.4: Diagram of the circuit, including the 4-bit decoder......................................................7
Figure 2.1: Five-bit current-mode DAC with binary weighted current sources. ...........................10
Figure 2.2: Vbias, Vnbias and Vncasc generator. ......................................................................12
Figure 2.3: Vpcasc Generator. ...................................................................................................12
Figure 2.4: Multi-bias DAC with equally sized transistors. ..........................................................12
Figure 2.5: Simplified schematic of the multibias DAC topology.................................................13
Figure 2.6: Dimensions of a MOS transistor (analog integrated design fig 1.10 page 21) [12]. ..15
Figure 2.7: Use of a reference to generate various currents( [13] page 136 figure 5.3). ............15
Figure 2.8: Basic current mirror ( [13] page 137 figure 5.5) ........................................................15
Figure 2.9: Cascode current source ( [13] page 140 figure 5.9). ................................................17
Figure 2.10: Cascode current mirror ( [13] page 140 figure 5.9).................................................17
Figure 2.11: Cascode current source with minimum headroom voltage (left), headroom
consumed by a precise cascode current mirror (right) [13]. .......................................................18
Figure 2.12: Modification of a Cascode Mirror for low-voltage operation suggested in [13]. ......19
Figure 2.13: Circuit proposed in Design of Analog CMOS Integrated Circuits [13].....................20
Figure 2.14: Circuit proposed in Analog integrated circuits design [12]. .....................................20
Figure 2.15: Circuit studied in lecture notes of the SIA course [19]. ...........................................20
Figure 3.1: Simplified schematic of one electrode stimulator. ....................................................23
Figure 3.2: Bias circuit for multi-bias DAC. .................................................................................24
Figure 3.3: Parallel transistors emulating a bigger device W=7.6, L=4 .......................................25
Figure 3.4: Single transistors W = 7.6, L = 4. .............................................................................25
Figure 3.5: Reference circuit for the bias circuit. ........................................................................26
Figure 3.6: Cadence schematic of the multibias DAC ................................................................30
Figure 3.7: Biphasic current pulse. .............................................................................................31
Figure 3.8: Biphasic current output amplifier ..............................................................................33
Figure 3.11: Output resistance parametric simulation with maximum positive output current.
Current in blue, voltage in pink. ..................................................................................................36
Figure 3.12: Output resistance parametric simulation with minimum positive output current.
Figure 3.13: Output resistance parametric simulation with maximum negative output current.
Figure 3.14: Output resistance parametric simulation with minimum negative output current.
Figure 4.1: Lateral diffusion under SiO_2 mask. ........................................................................40
Figure 4.2: Overetching of a polysilicon gate..............................................................................40
Figure 4.3: Simple Common Centroid layout. .............................................................................41
Figure 4.4: Common centroid with shared source ......................................................................42
Figure 4.5: A common-centroid layout for a differential source-coupled pair [12]. ......................42
Figure 4.6: Common centroid with a single transistor at the center. ...........................................44
Figure 4.7: Layout of the reference circuit for the multibias DAC ...............................................44
Figure 4.8: DAC's Layout ...........................................................................................................46
Figure 4.9: Output amplifier Layout ............................................................................................47
Figure 4.10: Final Layout with sixteen DACs and a four-bit decoder. .........................................48
Figure 4.11: Zoom in on the reference circuit and four DACs and drivers. .................................48
Figure 5.1: Biphasic current pulse with maximum amplitude (97µA). .........................................50
Figure 5.2: Breadboard test bench of the fabricated circuit ........................................................53
Figure 5.3: DAC 1 maximum current biphasic pulse ..................................................................57
Figure 5.4: DAC 16 maximum current biphasic pulse ................................................................57
Figure 5.5: DAC 16 minimum current biphasic pulse. ................................................................57
Figure 5.6: DAC 16 charge and discharge pulse at 50 kHz ........................................................58
Figure 5.7: INL for the Charge ramp from 0 to 100 µA ...............................................................58
Figure 5.8 INL for the Discharge ramp from 0 to 100 µA ............................................................58
Figure 5.9 DNL for the Charge ramp from 0 to 100 µA...............................................................59
Figure 5.10 DNL for the Discharge ramp from 0 to 100 µA ........................................................59
Figure 5.12: Photograph of the fabricated circuit. .......................................................................60
Figure 5.13: Fully cascode, 8-bit Multibias bias generator[3]......................................................61
Figure 5.14: Wide-swing cascode multibias generator[3]. ..........................................................61
Figure 5.15: Fully cascode 5-bit Multibias bias. ..........................................................................62
Figure 5.16: Matching technique for Biphasic Stimulation Pulse [14]. ........................................63
Figure 5.17: Method for matching anodic an cathodic current suggested in [16]........................64
Figure 6.1: Folded Cascode topology proposed in the SIA course.............................................68
Figure 6.2: Schematic of the Amplifier that was tested in Cadence............................................70
Figure 6.3: Plot of the output voltage of the amplifier in an AC simulation, with a magnitude of 1
V in the input, and for frequencies from 0 to 1GHz. In blue one can see the gain, in red the
phase. ........................................................................................................................................72
Figure 6.4: DC gain depending on the common mode voltage. .................................................73
Figure 6.5: Relation between the output noise and the frequency of the input signal.................74
Table 3.1: Value of each of the five bits .....................................................................................22
Table 3.2 : Dimensions of the biasing circuit for the multibias DAC. .........................................25
Table 3.3: Dimensions and Currents of the reference circuit's NMOS .......................................27
Table 3.4: Dimensions and Currents of the reference circuit's PMOS ........................................28
Table 3.5: Sizes of the output amplifier devices. ........................................................................34
Table 3.6: Ouput stage transistors behavior. ..............................................................................35
Table 5.1: Dimensions of the circuits layout ...............................................................................51
Table 5.2: Circuit's Worst Case Performance in Monte Carlo Simulations. ................................52
Table 5.3: Experimental results of the 16-DAC prototype ..........................................................53
Table 5.4: Maximum values for INL and DNL of DAC 16 ...........................................................59
Table 5.5: Branches current probability. .....................................................................................62
Table 6.1: Specifications for the Operational Amplifier. .............................................................69
Table 6.2: Amplifier transistors dimensions. ...............................................................................70
Table 6.3: Theoretical and Simulated DC operating point. .........................................................71
Table 6.4: Amplifier’s Objectives vs. Accomplishments ..............................................................75
xiii
n-channel MOSFET
p-channel MOSFET
Overdrive Voltage
1 Introduction
The project described in this report is related to the attempt of creating an Intracortical Neuronal
Stimulator. Although it is not integrated in any larger research project, most of the specifications
that guided the course of this work were based on conclusions from projects ICONS and
CORTIVIS [1].
This chapter begins by stating the relevance of the scientific area in question and presenting
some related works already done. Then, the main goals and challenges of this work are
described.
1.1 Motivation
In the last years, there has been a serious effort to develop integrated circuits for stimulation
that can be implemented in the human body. Microelectronics plays an important role in
development of such circuits and so it has been widely used. Many of these applications are in
the area of muscular stimulation (e.g. for heart diseases, or paralysis problems on the limbs) [2],
and in the area of organ’s cortex, or nerve stimulation (for instance for people who are blind,
partially blind or with hearing disease) [3], [4].
In all previous cases, the information needs to be coded in a way similar to how it was done
before the disease.
In order for prolonged use of the implanted stimulator to be possible, there is a need for an
external power source. If the power is transferred wirelessly [1], then, future procedures to
change the batteries, and a wired connection into the interior of the body are avoided, this will
not only decrease the risk of infections and health complications but it will also increase the
subject’s quality of life.
The circuit must be tuneable, in order for it to be used in different subjects with different
physiological characteristics. This will also increase the period in which the prosthesis is usable,
even when some properties of the stimulated organ change due to aging, the aggravation of the
disease or simply due to cell adaptations.
For both of the previous statements to be possible, wireless power and data transmission are
mandatory and a digital to analog converter is necessary.
The knowledge of the human visual system is not yet complete. However, in the last fifty years
this matter has been the object of a lot of research, in fact the understanding of the mammalian
visual system and its components, allowed researchers to find a relation between electrical
stimulation of any part of the visual pathway and the visual sensation. Experiences have shown
that electrical stimulation of individual parts of the visual system, like the retina, the optic nerve,
or even directly in the cerebral cortex, will induce the perception of points of light spatially
located, which are called phosphenes. Based on this ground, several projects, like CORTIVIS
and ICONS at INESC-ID, and research projects in other laboratories, have tried to develop
Chapter 1 Introduction
3
precise models of the human visual system so that useful visual prostheses can be developed
to partially restore the sight of blind individuals. One of the conclusions of these studies is that
the impedance of the electrode/cell interface is not fixed, thus each electrode, which will
stimulate a certain area of the cortex, should have a particular current pulse that is related to the
particular impedance of such area. The use of a digital to analog converter together with driving
circuit will allow the use of individual amplitudes and shapes for each of the stimulating
electrodes. The decision on what amplitude and shape to use is made and controlled by the
digital component of the prosthesis.
1.2 History and State of the Art
Although, useful results of research in visual prostheses are still on its early years, scientists
have been working hard to understand the nervous system and develop treatments for its
diseases for a long time. Experiences relating currents stimulation of muscles date back to 1759
[5] when Benjamin Franklin experimented the use of “electricity” as a way to overcome
paralysis, however, investigation at a cellular level was only possible in the last century.
Nowadays, the nervous system is more thoroughly understood, thus the ability to really treat a
variety of diseases is ready to make a leap resulting from the cooperation between biology and
microelectronics. Let us now briefly recall the progress that has been made in the last 60 years
or so.
In the 1950’s meaningful studies were carried out regarding the central nervous system at
cellular level, using microelectrodes and electronics to record and process the signals acquired
[6]. First, knowledge about single neurons was acquired, followed by a better understanding of
the nervous system, this knowledge was more detailed in sensory areas. These studies
however, revealed that, to make real progress on understanding the signal processing that
occurred in the neural networks, large arrays of electrodes would be needed. Some
experiments were made by gluing together individual electrodes, this was done aiming at the
objective of recording simultaneously from many different points. Although this experiments had
some significant results they were very limited in terms of geometry and reproducibility, and
caused considerable tissue damage at the time of insertion.
In 1965 for the first time lithographic techniques and silicon etching technology, which were
being developed for beam-lead integrated circuits, where suggested as suitable for producing
electrode arrays that would be able to record in several different places at the same time,
bearing no more damage than a single metal microelectrode. This theory was demonstrated by
Professor J. B. Angel in [7]. The problem was that, at that point the technologies and processes
available for silicon etching where rudimental, and the precision that was possible did not allow
high yield or reproducibility. Only over the next two decades the needed technology was
developed. In addition, the progress made in the past decade resulted in probes that are now
able to change the direction in which the neuroscience research will be following.
4
Parallel to the research in the area of microelectrodes and lithography, in the 1960’s, started the
development of implantable prostheses for the deaf and blind using arrays of metal electrodes
implanted in the cochlea, auditory nerve, inferior colliculus, and visual cortex [8]. Of course the
placement of the microelectrodes was very difficult, and since de dimensions of the electronics
were not yet appropriate for internal prostheses, they were all external, however, valuable
knowledge and insight was obtain referring to stimulus parameters and physiological response.
In spite of that, it was impossible to develop a system that could be said to realistically assess
the performance of a real working prosthesis. Today neural prostheses have shown to be able
to produce real results. As of December 2010, approximately 219,000 people worldwide have
received cochlear implants; in the U.S., roughly 42,600 adults and 28,400 children are
recipients [9].
In the field of eye diseases, microelectronic prostheses that interact with the remaining healthy
retina have been developed. These prostheses can restore some vision for individuals that
suffer from diseases at ocular level, like retinis pigmentosa. These prostheses use sub-retinal
devices that can replace photoreceptors, or even more complex epi-retinal (on top of the retina)
devices that will capture and process images that are transmitted to ganglion cells through a
matrix of electrodes (Figure 1.1). However, these devices, since they are in the front end of the
visual pathway, require that the rest of the visual system is functional, i.e. the optic nerves and
even the neurons that receive the information from the eye must be healthy. When that is not
the case, these prostheses are not useful. The stimulation needs to be performed directly to the
visual cortex, to neurons in periphery locations where the vision would be processed if the
visual system were healthy. In studies done by Brindley [10], and Dobelle and Mladejovsky [11]
(1982 and 1974 respectively) simultaneous stimulation of multiple electrodes allowed blind
volunteers to recognize simple patterns. However, this research also revealed an issue that
Figure 1.1: On the left: Microelectrodes Matrix; On the right: Single electrode in the neural tissue.
5
requires a paradigm shift in terms of electrode stimulation. In order for the stimulation to
produce phosphenes, currents need to be as high as 1 mA. These levels of current will cause
serious problems like epileptic seizures. In order for that not to happen one has to use deep
intra-cortical neuron-stimulation. This will excite the neurons at a depth between 1mm and
2mm, which will correspond to cortical layer 4, where signals from the lateral geniculate
nucleous arrive (Figure 1.1). The lateral geniculate nucleous is a redistribution center that
receives information related to the sense of vision, namely from the retinal ganglion cells
mention before. If one stimulates the neurons that deeply, it will allow a considerable decrease
in the magnitude of the current necessary to produce phosphenes, and will reduce the risk of
side effects for the subjects.
This was the evolution of the neural prostheses in general, and some considerations on what is
nowadays considered the best approaches in the field of visual prostheses.
1.3 Thesis objective
The objective of this thesis is to design a Neuronal Stimulator of reduced dimensions for a
visual prosthesis. The structure for the Visual Neuroprosthesis was already proposed and
defined in [1] (Figure 1.2). Several different blocks compose these prostheses. The Artificial
retina, the RF TX and the Power & Data RX blocks, are being developed in other theses. This
thesis is focused on the DAC and Driver (Electrode Stimulator).
Figure 1.2: Diagram of the Intra-cortical Neural Stimulator.
The DAC will have a 5-bit resolution and a maximum current of 25 µA. The Driver will use the
current from the DAC and generate a biphasic pulse with, 100 µA of maximum positive current
(gain of 4), and -100 µA of maximum negative current (gain of 4). The minimum current
6
amplitudes will be around 3.125 µA and -3.125 µA. The biphasic pulse is necessary because
when in a biological environment it is required to keep charge balance. The Driver will have two
control bits. The control bits will determine the duration of both the positive and negative pulse.
To sum up, the DAC will be responsible for the amplitude of the stimulus. The Driver will be
responsible for the duration and shape of the stimulus.
The electrical stimulation of the neurons should produce phosphenes. Phosphenes are only
perceived if the stimulation surpasses a certain charge threshold. This depends on the
electrode/brain cells impedance, which varies from one electrode to the other. Thus, DACs must
be used to generate different current values.
The goal is to fit as many stimulating circuits as possible, in a chip with fixed dimensions. To do
this, the area of the stimulator must be reduced. Usually the DAC is the circuit with the largest
area in the stimulator. We will study the possibility of reducing the area of the DAC by using the
multibias DAC concept proposed in [3]. The area reduction also depends on careful layout from
the designer. Thus, careful area-saving layout will also be a main objective in this thesis.
Furthermore, the positive and negative currents of the biphasic pulse must match. Thus,
another objective of this thesis is to minimize the mismatch between these currents. This mainly
depends on the Driver circuit, which will be similar to the biphasic output amplifier that is in [3].
In addition, the power consumption of the circuit must be reduced to the minimum possible.
To sum up, the objectives of the thesis will be:
Minimize the area of the components by using the multibias concept, and small
dimension transistors;
Minimizing the area of the circuit by using an area reduction oriented layout;
Match the positive and negative currents from the driver;
Keep power consumption as low as possible.
The technology is AMS 0.35 µm, with a power supply from 0 to 3.3 V.
The multibias DAC concept consists in using several bias voltages to generate the weights of
the currents, instead of a single one, used in common DACs. This will allow the transistors in
the DAC to be of unitary size, and greatly reduce the area of the DAC. Since the references are
voltages, all the DACs in the chip can share a single reference circuit. This allows a great area
reduction because there will be many stimulators (up to 1024) and only one biasing circuit.
What will determine the usability of this concept is, the area occupied by the chip and the power
consumption, which are the main requirements. Of course, monotonicity is necessary, and low
integral nonlinearity (INL) and differential nonlinearity (DNL) are desirable.
This study is needed because in [3] the DAC was implemented in 1.2 µm technology with a
power supply of V.
7
The final prototype should be composed of one reference circuit, sixteen multibias DACs,
sixteen Driver circuits, and a decoder (Figure 1.3, Figure 1.4). In Figure 1.3 is the representation
of one single electrode stimulator, while in Figure 1.4 is the diagram of the entire circuit of this
thesis. The decoder was not designed within this thesis; however, it is necessary to choose
which DAC is active.
Figure 1.4: Diagram of the circuit, including the 4-bit decoder.
1.4 Thesis Outline
In this thesis, a Neuronal Stimulator is presented. The Multibias DAC concept explained. The
DAC and Driver topologies and layout are explained.
In Chapter 2, the multibias DAC concept is explained, as well as the theory that is needed to
implement it, focusing mainly in the optimal current mirror topology.
8
In Chapter 3, there is an extensive explanation on how the circuit was realized, and the
difficulties encountered during the course of the project. Each of the three parts of the circuit are
explained separately.
In Chapter 4, the layout of the circuit is presented. Some considerations about what are the
mains issues that contribute to circuits non-idealities, and what can be done by the designer to
prevent these factors from changing the operation of the circuit, are made.
In Chapter 5, the results of both the simulation and testing of the fabricated circuit will be
presented and described. A section on future work will be presented. In the future work section
a consideration of what can be done in order to decrease power consumption will be made. In
addition, some topologies that minimize the mismatch between cathodic and anodic current will
be discussed.
In chapter 6, a brief study of a folded-cascode amplifier that could be used in future work, to
provide readings of the neuronal signals, after each stimulus of the neurons.
Chapter 2 DAC Design
2 DAC Design
A very common component of stimulation prostheses is a digital to analog converter. This
component is important because it is difficult, if not impossible, to know before implantation
what is the impedance that characterizes the electrode/cell interface in each section of the
tissue that will be stimulated by the prosthesis. Thus, a posterior tuning of the devices is needed
for the stimulation to produce physical results (i.e. produce movement on the limbs, produce
phosphenes in the visual cortex, etc). To tune the intensity of the stimulus, one needs a digital
to analog converter.
In this thesis, the objective is to produce a prototype for a DAC and Driver designed to stimulate
the neural visual cortex. The specifications are the following:
Biphasic output current with an amplitude between 0 and 100 A;
Minimum Area;
Monotonicity;
Low power consumption.
In this work, a current-mode binary-scaled topology is used. It is binary-scaled because it
combines a set of signals, currents in this case, that are related in a binary fashion.
In Figure 2.1 a five-bit current-mode DAC with the branches scaled in a binary fashion, is
illustrated. Commonly, in this type of converters, there is a reference current created by an
external circuit which is passed to a voltage reference circuit. This reference circuit will then
create the biasing voltages (one or more depending on the number of transistors in each branch
that need biasing) like Vbias and Vpcasc in the figure. These voltages will bias N branches (where
N is the number of bits) that are scaled in a binary fashion, W/L, 2W/l, 4W/L, 8W/L and 16W/L.
The result of the sum of the currents in each branch controlled by one of N bits will be the result
of the digital to analog conversion.
Figure 2.1: Five-bit current-mode DAC with binary weighted current sources.
11
These types of converters have a major disadvantage: a binary relation between the sizes of
each transistor, from one branch to the next. This can be a problem if it exceeds the area
specification of the application where the converter is to be used. This problem will be severely
aggravated if the DAC is to be replicated. Those are the cases when the application is a
neuronal implant. Of course, this limitation is aggravated when there is a need for more
resolution and consequently the DAC must have more bits, and therefore more branches.
In the next sections the multibias approach, which, as proposed by [3], eliminates the problem
of the quadratic relations between transistors size, will be explained and discussed. This
topology poses some constrains. These constrains and how they were overcome will be
explained.
After the topology is presented, the theoretical bases for the implementation of the multibias
DAC topology and for the Driver will be explained.
2.1 What is the multibias DAC concept?
In bio-medical applications, the circuit size is a major constrain in the project, so different ways
of achieving the same performance while using less area are proposed by different authors. In
this way, the multibias concept was proposed by DeMarco et al [3]. What they proposed was a
topology for a biasing circuit and a DAC, which will maximize the use of circuit area when the
application demands the use of a large number of converters.
2.1.1 Common binary weighted DAC vs. multibias DAC
(2.1)
The current of a MOSFET biased in the saturation region is given by (2.1).
In a binary weighted DAC (Figure 2.1), currents come from a shared MOSFET gate voltage that
is generated in a single branch (Vbias in Figure 2.1). This gate is connected to several DAC
branches so that they can reproduce the output currents. The relation between the branches,
binary in this case (power of two), is achieved using the devices geometry (dimensions) or the
number of transistors. The current in each branch (in) is related like this
, where is the reference voltage. n is the bit weight between .
This approach requires a DAC with transistors of size . The difference between the
typical approach and the multibias DAC is the replacement of the single MOS gate bias, with
multiple gate bias voltages (VbiasN-1, VbiasN-2, ..., Vbias1, Vbias0), and replace the transistors
with transistors of the same dimension. This way the drain current for the N-bit branch
becomes .
Because in this technique there are multiple bias voltages, it is referred as multibias DAC.
Consequently, bias voltages instead of geometry control the current. This technique allows the
branches to have one device of unitary dimensions that determines the current. Besides, the
12
relation between current and gate voltage is not linear but quadratic. This means that, to
achieve a binary relation between the current, in each branch, the voltage applied to the gate
does not have to increase in a binary fashion but linearly.
An example of the multibias DAC topology components is illustrated in figures 2.2 to 2.4.
In Figure 2.2 is the circuit that biases the bias generator. The way it works and why that
topology is used will be explained in the section 3.1.
The circuit in Figure 2.3 generates Vbias0 to VbiasN-1 from transistors of unitary dimensions
(dimension M). As part of the reference circuit, is instantiated only once. This circuit will also be
explained in section 3.1.
In figure 2.4 the multibias DAC with equally unitary sized transistors (dimension M) and the
multiple biasing voltages, is presented. This circuit will be explained in section 3.2.
In Figure 2.5 one can see a simplified schematic were all these three components are together.
This way, it is easier to understand the relation between each component. This figure will be
revisited in Chapter 3, to give an overview on what will be explained there.
Figure 2.2: Vbias, Vnbias and Vncasc generator.
Figure 2.3: Vpcasc Generator.
Figure 2.5: Simplified schematic of the multibias DAC topology
Apart from these three circuits, that are the building blocks for a multibias DAC, in [3] a topology
for a biphasic output amplifier (Driver in Figure 2.5) is also suggested. That is the driving circuit
to be used if the multibias DAC is instantiated in a stimulus circuit. Details about that circuit will
be given in Chapter 3.
2.1.2 Multibias DAC advantages
Having the above in mind, we get to the major advantage of this topology: it provides a DAC
with equally sized binary weighted current sources. This means that in a DAC with N bits the
transistors producing the current for the least significant bit (bit 0) have the same dimension as
ones in the most significant bit (bit N-1).
The number of bits can increase if there is enough voltage to bias the transistors in each
branch. The circuit’s area scales linearly versus number of bits instead of exponentially,
meaning that it is possible to have more stimulus circuits per chip area, thus, greater stimulus
resolution.
Another good feature of the multibias DAC is that it retains low integral nonlinearity and
differential nonlinearity. The INL error is defined to be the deviation from a straight line, that
usually is drawn using the endpoints of the converter’s transfer response, after both the offset
and gain errors have been removed. DNL is defined as the variation in analog step sizes away
from 1 LSB (typically, once gain and offset errors have been removed).
Of course seldom we come across with an innovation that brings only advantages, so, following
the rule, this concept has two major disadvantages that will be explained next.
2.1.3 Multibias DAC disadvantages
To achieve low power consumptions, the circuit’s power supplies are decreasing. This change
decreases the voltage that is available to bias the transistors. The multibias DAC is not optimal
in the use of voltage headroom and that is its first disadvantage. Since the number of bits that
can be used depends on the variation of VGS, this will limit the number of bits that can be used.
14
Although this idea will not be contemplated in this work, the limitation imposed by the voltage
headroom could be mitigated if a hybrid topology between the multibias DAC and the binary
weighted DAC is used. In this case, instead of having each branch’s transistors related in a
binary way, or the transistors in all the branches with the same sizes, one could use a limited
number (N) of branches with equally sized transistors to generate the first N bits and then an
equal number of branches with transistor 2N times bigger. If this technique is repeated it will still
save area, and the resolution would be limited only by the space available. If analogous bits
share the same voltages they will produce a current times higher than the corresponding bit
in the previous N set of bits. For instance, in a 10-bit DAC this approach will still be 3 times
smaller than the common binary weighted DAC.
The second disadvantage is related to the area of the reference circuit. To generate the
voltages to bias each of the branch’s transistors, the voltage reference circuit will necessarily be
bigger and more complex than it is in the binary weighted DAC. In this circuit, the transistors
that generate the reference currents will have their sizes binary related.
These disadvantages would not outweigh the advantage of having all the branches with the
same dimensions if it were not for the fact that there is only one biasing circuit and a number of
converters. The biasing circuit will be instantiated only once in the whole chip. VbiasN-1 to Vbias0
are for that reason generated and distributed to all the DACs throughout the stimulator. The size
of one bigger circuit is then diluted amongst those with smaller areas.
In the next section, the reasons for using two different kinds of current mirrors will be explained.
2.2 Current Mirrors
To design a five-bit DAC there is a need to generate five different values of current that will be
combined in a scale with possible values, in other words we need to create five current
sources. In this thesis the DAC does not need to be precise, granted that it provides a
monotonic scale. However, the biphasic pulse produced in the driving circuit must be highly
precise, meaning that the difference between the positive and negative pulse must be
minimized (in the order of nanoamperes if possible). This specification justifies considerable
investment in the choice of the current mirror.
Two different kinds of current mirrors are needed. A mirror that has maximum precision,
regardless of voltage swing and a mirror that provides a compromise between precision and
voltage headroom. The mirrored current should be independent from the output voltage.
The first kind of mirror is to be used in the voltage reference circuits. These circuits are not
connected to the output, thus do not need to allow a high voltage swing. The second kind is to
be used in the Driver (output circuit). It needs tolerate as much voltage swing as possible,
because the more it tolerates the higher will be the impedance that can be stimulated.
The design of current sources in analog circuits is based on “mirroring” currents from a
reference, assuming that there is one precisely defined current source available (Figure 2.7). In
15
this thesis we assumed that this reference current is created externally, using a variable
resistor, and then fed to the circuit. That copy is made using current mirrors. Since this is a very
important component in this project, deeper explanation is mandatory. Thus, this section is
dedicated to the understanding of the current mirrors.
Figure 2.6: Dimensions of a MOS transistor (analog integrated design fig 1.10 page 21) [12].
Revisiting equation (2.1) one can recall the linear relation between the current that crosses a
MOS transistor ( ) and its size, more specifically the quotient between its width and length (the
meaning of these distances is easily understood in Figure 2.5). Although there are several,
more complex, equations to describe the relation between the size of the transistor and its
current (like the ones used by CADENCE), equation (2.1) still provides a good insight on the
operation of a MOSFET in the saturation region, so it could still be used during this work. In this
equation K is a constant that differs from NMOS to PMOS and depends on the technology used
(170 for the NMOS and 58 in AMS 0.35 ). is the voltage between the gate
and source of the transistor. is the threshold voltage between the gate and the source that
must be surpassed to create the channel between source and drain.
To understand how the current is mirrored, the basic NMOS current mirror as represented in
Figure 2.8 will be explained.
Figure 2.7: Use of a reference to generate various currents( [13] page 136 figure 5.3).
Figure 2.8: Basic current mirror ( [13]
page 137 figure 5.5)
For a MOSFET, where denotes functionality of versus , thus,
. Therefore, if the same voltage is applied between the gate and source terminals of a
second MOSFET the result is . In other words, two identically sized MOS devices
that have equal gate-source voltages, and operate in saturation, will carry equal current.
The circuit on Figure 2.7 mirrors the current from M1 to M2. In general cases though, the
devices do not need to be identical. With the transistors in the saturation region and neglecting
channel length modulation we can write
(2.2)
(2.3)
(2.4)
This topology allows a copy of a current independent from VTH. The ratio between and
is given by the ratio of device dimensions (2.4), a quantity that can be controlled with
reasonable accuracy.
The mentioned topology already seems to fill all the requirements of a copying circuit. However,
one important detail must be stress: until now channel length modulation has been neglected, if
that effect is taken into account, we can write
(2.5)
(2.6)
(2.7)
While we can guarantee that , by connecting the drain to the gate, and ,
can be different from because it depends on the circuitry connected to the transistors
drain. This effect will result in significant error when copying currents, especially if transistors
with minimum length are used. The solution to this problem is to use a cascode current source
like the one on Figure 2.9. In this topology must be chosen so that , if that is the
case then IOUT will be a close copy of IREF. This happens because the cascode transistor shields
the bottom transistor from variations that may occur in node P. This protection and consequent
accuracy can exist at the cost of voltage headroom.
17
To generate one must have in mind that the objective is to make , so minus the
gate to source voltage must be equal to meaning that . A way to do that is
to add the gate-source voltage, of a transistor similar to M3, to , if we do that we can obtain
the wanted value for Vb. This can be done by adding another diode connected transistor, in
series with M1, thus creating , if the dimensions of the M0 transistor are chosen
properly (equal to M3 if the current is to be copied without scaling) we can correctly say that
apart from process mismatched . One can see such a circuit in Figure 2.9. In
addition, node N must be connect to the gate of M3 to get , so if
then and , this will still be true if M3 and M0
suffer from body effect.
This topology can guarantee not only high output impedance but also an accurate value for
however, it consumes substantial voltage headroom.
Neglecting the body effect then the minimum voltage that can be at node P so that and
M3 is in the saturation region is
(2.8)
(2.9)
(2.10)
(2.11)
(2.12)
That is two overdrive voltages plus a threshold voltage. However if we look at Figure 2.11 it is
easy to see that if would be chosen more freely one could have get as low as two
overdrive voltages and still, in theory, have M2 and M3 in saturation. As a result, this topology
Figure 2.10: Cascode current mirror ( [13] page 140 figure 5.9).
Figure 2.9: Cascode current source ( [13] page 140 figure 5.9).
18
wastes a threshold voltage, so to say. That happens because when we have a diode connected
transistor will necessarily be equal to ( ) when it was only required that
to keep M2 in saturation.
Knowing all of the above, we can now look at the circuit on the left in Figure 2.10 and can see
that if is chosen to allow the lowest possible value of the output current is not an exact
copy of IREF. That happens because, although M2 and M1 have equal , they will still have a
different On the other hand if we choose the topology on the right, maximum accuracy is
achieved at the cost of having minimum one threshold voltage higher.
As a note, one can say that this headroom (Figure 2.10) is too substantial for some parts of the
circuit, namely the biphasic current output amplifier because it will be in series with the
microelectrode placed on the brain cortex. Currents from 3 µA to 100 µA need to flow through
the electrode into the cortex creating a voltage drop; consequently, if the circuit itself requires
too much voltage headroom to generate a copy, then, the range currents that can be used will
be limited.
This topology was only when voltage headroom was not as significant as precision. When
precision and voltage headroom were equally important, another topology had to be studied.
In [13] the circuit on Figure 2.12 is suggested. It is very similar to the circuits above (Figure
2.11).
The dimensions of the transistors must be chosen in a way that the current is mirrored or
scaled. For that to happen, M1 dimensions needs to be related to M3 dimensions and M2 to M4
in the same way, aside from that there is no need for any other kind of relation between M2 and
M1 or M4 and M3.
Figure 2.11: Cascode current source with minimum headroom voltage (left), headroom consumed by a precise cascode current mirror (right) [13].
19
The relation that establishes the current is between M1 and M3 dimensions, and it is still the
one described in (2.7). M2 and M4 are still shielding M1 and M3 and need only to be in the
saturation region for the circuit to work properly. For them to work with minimum headroom Vb
must be chosen carefully and so have M2 and M4 dimensions, because Vb will determine the
overall voltage headroom. However, it is by controlling the dimensions of M2 that one can
control its gate to source voltage (VGS), and so the drain to source voltage (VDS) of M1 and
therefore of M3.
How can we choose so that M1 and M2 are both in saturation?
A few conditions have to be met: in order for M2 to be in saturation; and
to saturate M1. This creates an inequality with two boundaries
. (2.13)
It is only possible to find a solution if . Therefore, M2 must be sized in a way
that it will keep its overdrive voltage smaller than one threshold voltage. If that is done, then Vb
has been chosen correctly in order for the circuit to work with minimum voltage headroom but
maximum precision.
The next issue to solve is the creation of the biasing voltage . Once again it has to be
stressed that needs to be high enough to bias M2 and M1 into the saturation region, but also
not so high that it would make smaller than . After reviewing the matters
presented in this chapter the choice of a biasing circuit is between three very similar circuits, the
circuits are in Figure 2.13, Figure 2.14 and Figure 2.15.
The circuit in Figure 2.14, suggested in [12], was chosen because of its simplicity, and because
there were no disadvantages comparing to the other two. All three approaches were tried and
simulated and since none of them showed to be better in terms accuracy the simplest was
chosen. One thing that can be noticed is that they are very similar to each other, for instance in
the circuit in Figure 2.15, transistors M4 and M5 are playing the same role as transistor Q5 in
Figure 2.14. This happens because they are practically the same. The difference appears
Figure 2.12: Modification of a Cascode Mirror for low-voltage operation suggested in [13].
20
because when the rule of using a transistor like Q5 (if n is one, which is the case) is
applied, one will often come across with lengths that are too great. To prevent that, the
transistor can be divided in two that do the same but have smaller lengths. In this thesis, the
currents are in the range of tens of microamperes, the width and the length of the transistors
can be small, thus the problem of having a transistor that is too long does not exist.
In this chapter, all the necessary theory for the design of the DAC was covered. In the next
chapter is the report on what was done and the difficulties that where found during the project,
as well as the methods that were used to surpass them.
Figure 2.13: Circuit proposed in Design of Analog CMOS Integrated Circuits [13]
Figure 2.14: Circuit proposed in Analog integrated circuits design [12].
Figure 2.15: Circuit studied in lecture notes of the SIA course [19].
Chapter 3 Dimensioning and
22
3 Dimensioning and Implementation
Having chosen the current mirrors to use, there is still the need to create five different reference
voltages to produce the required current in the DAC, and to implement the output circuit that will
generate the biphasic pulse that will be drive the electrode.
The DAC has a resolution of 5 bit, and the maximum current is 100 µA therefore the least
significant bit must bear a current of 3.125. However, as will be explained in section 3.2 the
output circuit has a gain of four and so the LSB at the DAC’s output will be µA, which is
the value of the reference current fed to the circuit. The reason for having to use that value will
also be explained in section 3.2. The current of each one of the five bits can be seen in Table
3.1, allowing combinations in the scale of 0 to with steps of 3.128µA.
Table 3.1: Value of each of the five bits
Bit number DAC current Output current
1 0.782 3.128
2 1.564 6.256
3 3.128 12.512
4 6.256 25.024
5 12.512 50.048
Total 24.242 96.968
The following procedure allowed the scaling of the transistors in each branch:
1. Theoretically find the relation between W and L of each transistor using equation 2.1,
with a around 0.200 V and id equal to the current that is supposed to cross
that same transistor;
2. Use the smallest L that is adequate for the application and calculate the W based on the
quotient found above;
3. Simulate and verify if all the transistors are in the proper region (saturation in case of
current mirrors, triode in case of switches);
4. If not, check which of the saturation conditions has not been met and adjust the W and
L, changing their relation if needed;
5. After making sure that all the transistors are in the saturation region, run Corners
simulation and Monte Carlo to check if every transistor in the circuit is in the appropriate
region in all simulated conditions;
6. If not, check which situation broke the normal functioning of the transistors and adjust W
and L, this time the relation between W and L must be maintained to make sure the
transistors stays in the saturation region. Also, all the transistors that are geometrically
related to the one being adjusted should be adjusted proportionally;
7. Create the layout of the tested cell and simulate the circuit with the extracted capacities.
Summarizing, this project is composed of three different parts, the Reference circuits, the DAC,
and the Output stage that is a biphasic current amplifier. The reference circuits create all the
Chapter 3 Dimensioning and Implementation
23
biasing voltages that are needed throughout the chip whereas the DAC will convert from one to
five of these voltages into current depending on the controlling bits. Then the Driver amplifies
the current from the DAC and then feeds it to the electrode in the form of a biphasic pulse
controlled by two bits, one that controls the charge and the other the discharge.
In Figure 3.1 one can see a simplified squematic of an individual electrode stimulator. In this
squematic the biasing circuits are also included for the porpose of providing better
understanding of the circuit, despite of being shared by all the DACs and Drivers.
Figure 3.1: Simplified schematic of one electrode stimulator.
The next sections will describe the two different biasing circuits that were implemented for the
DAC, and the output amplifier.
(All the circuit schematics are available with better definition in the appendix chapter.)
3.1 The Biasing Circuits
In this section, two biasing circuits will be described, the DAC’s biasing circuit (Multibias
generator), and the reference circuit (Multibias bias). The second circuit also biases the Driver
circuit.
First, the DAC biasing will be described. This decision was taken for three reasons: because the
sizes of the transistors were calculated in a more typical way; because it is more directly related
to the DAC; and it is a simpler circuit. The second reference circuit, on the other hand, can be
performed in many different ways as long as it generates the voltages to bias the cascoded
transistors into saturation.
24
The circuit used to create the reference branches for the DAC is in Figure 3.2. This circuit is in
many ways similar to the one in [3], but it has a difference, each cascode transistor has its own
bias voltage. That was necessary because when sharing only one bias voltage (Vpcasc) the
cascode transistors where not optimally biased and would require a voltage headroom that
would prevent some of the transistor from being in saturation.
Voltages and that can be seen in Figure 3.2 are generated in the other
reference circuit that will be explained afterward.
The biasing voltages Vbias, from zero to four, are the voltages that will bias the transistors in the
DAC itself, so that the currents created here are mirrored to each of the DAC’s branches. What
happens is that the dimensions of the NMOS are sized in a binary fashion, and so, the same
voltage will generate binary related currents, much like a common DAC.
As one can see in Figure 3.2, there are transistors with different sizes; these dimensions can be
seen in Table 3.2. Referring to the NMOS though, to get the binary relation multiple devices
where connected in parallel. In the first branch, there is only one lower transistor and one
cascoded, in the second two of each kind, in the third four, in the fourth eight and in the fifth
sixteen. This way the use of different sized transistors is avoided. This measure benefits the
matching between transistors because they will suffer the effects of the fabrication process in
the same proportion. This will also enable the use of common centroid techniques. This circuit is
the common binary weighted DAC mentioned in Chapter 2.
The PMOS transistors have two different sizes; the upper transistors have a width of 3.75
and a length of 3 , while the cascode devices have a width of 6.55 and a length of
0.75 .
25
Table 3.2 : Dimensions of the biasing circuit for the multibias DAC.
Transistor Width [µm] Length [µm]
PMOS 3.75 3
Cascode NMOS 1.9 4
As for the NMOS, each column is related in a 1 to 2 fashion from left to right, so that the
currents could be binary scaled.
The width of unitary transistor, the one that bares the lowest current, is 1.9 µm and the length 4
µm. This multiple transistors were then connected in parallel emulating the operation of bigger
transistors. In Figure 3.2 and Figure 3.3, one can see how these parallel devices can be
connected in order for them to have the same behaviour as the bigger transistor. With the
sources connected to each other and the drains connected to each other the resulting width, in
this case where we have four transistors, will be four times the width of the connected devices
( ). However, the length of the composed transistor remains the same. This
happens because the shortest pass from one source to the closest drains is still one length (4
µm). Thus, the resulting transistor will have a length of 4 µm and a width of 7.6 µm, just like the
single bigger device.
To get to a 3.75 µm value for width and 3 µm for the length of the PMOS devices, equation (2.1)
was used. The chosen id for that dimensioning was the second in the scale. So using id =
0.782x2 and based on equation (2.1) a 1.34 value for the quotient between W and L was
Figure 3.3: Parallel transistors emulating a bigger device W=7.6, L=4
Figure 3.4: Single transistors W = 7.6, L = 4.
26
obtained. After that, a parametrical simulation was taken in order to find the best pair of values
to use. These values, should guarantee a compromise between precision and minimum area
usage. The results were a relation of 3.75 to 3, values that would give relation of 1.25 instead of
1.34.
For the cascoded transistors, the same approach was followed but it resulted in some of the p-
channel transistors not being in saturation. While analysing each branch we noticed that, as
higher values of current were used (i.e. the more significant the bit was), deeper in triode region
the transistors would be. Because of that, the width of the cascoded PMOS devices had to be
increased so that the gate to source voltage would decrease, but not too much, that it would
make impossible to use the minimum current. A compromise was found using a parametrical
simulation of the width.
The upper PMOS transistors have an L=3 µm because those are the transistors that will mirror
the current. Current mirrors are more precise if the transistors have longer lengths because it
helps to minimize the effects of channel length modulation.
For the cascode PMOS, a value close to two times the minimum length was chosen and then
trimmed so that minimum reasonable was obtained on the transistors above. By minimum
we mean the minimum value that would able all the transistors to go through corners and Monte
Carlo simulation without violating one of the conditions for saturation which are
and .
The W/L=1.9/4 in the NMOS devices was obtained by using minimum id = 0.782 and then
adjusting to make voltage room for the PMOS transistors. Once again, a considerable length
was used to minimize channel length modulation.
In the circuit of Figure 3.5 the references for the cascode devices are created. The circuit will
receive the reference current from an external source and generate the bias voltages. In this
circuit, there are five different types of bias voltages: three generated in the NMOS devices,
Vncasc and Vnsrc, which are generated in the first reference branch and Vncasc_driver that is
Figure 3.5: Reference circuit for the bias circuit.
27
generated in the last reference branch; and two generated in the PMOS, Vpcasc from 0 to 4
and Vpcasc_driver.
Vnsrc is responsible for mirroring the current that flows through the reference branch (I_REF) to
the current mirrors, both in this circuit and in the biasing circuit.
Vncasc biases the cascode transistors into saturation. The quality of this references has impact
in the whole circuit, thus, this is the circuit where precision is most important. That was taken
into consideration while choosing the dimensions for the transistors. According to it, a length of
4 µm was used for the NMOS, because bigger lengths favour precision and matching. Also,
instead of simply scaling the transistors in the other branches, multiple devices where used to
form ‘one’ transistor. This allows the use of a common centroid layout with the previous
reference circuit.
The other references created are the Vpcasc’s. As the name suggests these are the voltages
that bias all the cascoded transistors in the multibias DAC circuit. Vpcasc 0 to 4 bias the
branches of the DAC, whereas Vpcasc_driver will bias the P type devices in the output circuit.
This circuit has a peculiarity that must be noted: although each branch generates the voltage to
bias the cascode current mirror branches where a binary related current is flowing, the
transistors are not sized in a binary fashion, neither the currents that flow through each branch
are related in that way.
Recalling the circuit in Figure 2.14 (current mirror from [12]) where only one transistor is used to
bias the cascoded device, one can say that, since the transistor Q5 is used only to generate a
voltage it is possible to choose any combination of values for the current and dimensions as
long as the biasing voltage produced is the same. So one can find a compromise between the
lowest current possible, and the smallest dimensions, and still meet the requirements for
precision. That was done and the results for the dimensions of the transistors and respective
currents are as presented in Table 3.3 and Table 3.4
Table 3.3: Dimensions and Currents of the reference circuit's NMOS
Devices N0,1 N2,3 N4,5 N6,7 N8,9 N10,11 N12,13 N14,15 N16
Width [ 1.9 1.9 1.9 2
Length [ 4 4 4 4 4 4 4 4 6
Current [ 0.782 0.782 0.782 1.564 3.128 6.256 12.512 25.02 25.02
28
Table 3.4: Dimensions and Currents of the reference circuit's PMOS
Devices P0 P1 P2 P3 P4 P5 P6,7 P8,9
Width [ 1 1 1 1 1 3 8.1 8.1
Length [ 2.5 5 5 5 5 6 0.75 0.75
Current [ 0.782 0.782 1.564 3.128 6.2256 12.512 25 25
These dimensions allow the circuit to have less power consumption and smaller area while still
providing individual biasing for the cascode transistors in the reference circuit, the DAC and the
driver circuit.
The circuit for biasing the cascode transistors was not described in [3], thus its topology was
chosen according to the research done and explained in chapter 2. Although in [3] it is
suggested that a single biasing voltage is used for all the cascoded transistors, during the
development of this project using an individual bias for each individual transistor was found to
be a better choice. When that was the case, the circuit passed the corners and Monte Carlo
simulations. Of course, this has its cost in terms of power consumption. However, near the end
of the project, a topology that might be a better compromise between area, stability, and power
consumption, that had already been tested and failed, was adjusted and met the requirements
for this project. This matter will be addressed in the final chapter under Future Work.
3.2 The DAC
After implementing and simulating the reference circuits, designing the DAC was only a matter
of mirroring the currents from the PMOS transistors in the multibias generator to five different
branches.
The schematic of the DAC is in Figure 3.6. As one can see in the schematic, the tested circuit is
very similar to the one proposed in Figure 2.4. The only difference is in the representation of the
switches, which in this case are a pair of PMOS that have their gates connected to the bit
corresponding to their branch weight, or to the OUT terminal of an inverter, that inverts this bit.
The result produced by these connections, is that the transistor that mirrors the current will
either, have its gate connected to the bias voltage generated in the multibias generator, and
thus will be in saturation with the same current as the reference, or it will be connected to Vdd. In
the last case, VGS is equal to zero and the transistor is in the cut-off region, resulting in no
conduction between drain and source, thus no current in that branch.
This way to enable and disable each branch was chosen instead of the one in which the current
is driven to the output or to the ground because although the selected approach is slower it
saves a lot of power consumption.
29
The inverters used in this project were not those provided by the cadence library, but a new one
designed during this thesis to occupy less area and fit better amongst the other components.
The fitting may seem less important but it resulted in significant area reduction.
Aside from the above, there is another switch that was not present in Figure 2.4, the
ENABLE/DESABLE switch, which will allow us to choose which electrode will stimulate the
cortex while feeding the same bits to all the DAC’s.
One thing that was not mentioned in the previous section when explaining how the transistors
were sized was how difficult it is to keep all the transistors in saturation when the currents are
different from one branch to the other, but the width and the length are not. To do that one has
to keep in mind the involved variables and their relation with each other.
Looking at the saturation equation (2.1), the variables are Id, VGS, W/L, VTH and K. Since K is a
constant, nothing can be done with it. VTH depends on different factors that are not easy to
account for, therefore, we will consider it to be a constant and equal to 0.7 in some cases, and
0.5 in other cases (to choose between values we used the VTH returned by the simulation).
Having the above present and looking at the equation, we can easily see that if W/L, which are
the variables that one can control, increase, the current increases in a linear way, and if
increases, the current increases in a binary fashion (VGS can be controlled by changing the W/L
of the transistors in the biasing circuit). Therefore, if the W/L is too great it will be difficult to keep
the transistors in saturation in the least significant bits because VGS would be too low in those
transistors, despite the VGS needed for the most significant bits being near optimum. On the
other hand, if the W/L is reduced, the transistors in the branches with greater currents will need
a greater VGS and will fall out of the saturation region. This compromise is not difficult to be
found theoretically, however when simulating Monte Carlo often the circuit would fail and the
dimensions would have to be recalculated.
(2.1)
30
Another thing that has to be considered is that, although the current increases quadratically with
VGS, the variation is limited because the power supply voltage is limited to 3.3 V. With that
voltage, one needs to bias four transistors into the saturation region. This leaves us with 825
mV for each transistor’s drain to source voltage. Considering that the threshold voltage of the
transistors is 600 mV on average, and for security the minimum difference between the
threshold voltage and the gate-source voltage is 150 mV, one can use a variation of
. This means that the variation in current that can be achieved is from 0.0225
to 0.455 times
. In other words if the voltage is distributed equally for
each transistor, with the same dimensions the maximum variation achieved is of
times, i.e. if with the minimum voltage we have 3.125 , with maximum only 64 can be
reached. In this work a 100 current is needed.
After the above appreciation, it was concluded that designing a multibias DAC with a current
variation as high as 30 times would be difficult. Ergo, as will be explained in the next section, it
was decided that a current reference of 0.782 would be used to reach a maximum current of
12.50 µA in the most significant bit. This will provide a total of 25 µA, and will not only facilitate
the biasing of the transistors, but will also lower the area of the circuit and the power
consumption.
Still, 25 is not the maximum current that is requested by the project specifications. To reach
maximum current the output of the DAC will be multiplied by four in the biphasic output
amplifier. With this, a minimum significant bit with a current of 3.125 µA will be possible and a
maximum of 97µA can be achieved.
Now that it is known that the minimum significant bit in the DAC is 0.782 , to know how much
voltage variation will be needed to reach the 12.5 , a simple reasoning can be made. If one
Figure 3.6: Cadence schematic of the multibias DAC
31
needs 0.150 V to generate 0.782 , to generate 12.5, which is sixteen times greater, we will
need to increase the voltage to because the relation between current and
VGS is quadratic. Thus, the PMOS device that generates the highest current will need an
overdrive voltage of 0.6 V this means that the drain to source voltage (VDS) is considerably high.
It is also too high for the DAC to be used as an output stage. This makes the next section of the
circuit even more important because independent of the DAC output voltage headroom the
drivers voltage swing will stay the same. It can even be said that this multibias DAC approach is
only possible if an independent output stage is used.
3.3 The Output Amplifier
A very important part of this circuit is the driving circuit, because it will be connected to the
electrode and the visual cortex. This circuit will also shield the DAC from whatever is connected
to the circuits output. The requirements that this circuit must fulfil are the following:
Generate a biphasic pulse with 100 µA of amplitude;
Have high output impedance;
3.3.1 Biphasic Pulse
Referent to the first requirement, it can be said that, although different stimulation pulse shapes
have been studied, biphasic stimulation current pulses are preferred [14]. That is necessary
because when in a biological environment it is required to keep charge balance. Another
advantage of using a biphasic pulse is that it is faster to get the electrode to nominal potential
(the same potential as before any stimulation) due to the charge balance, in order for readings
to be taken. These readings are taken between two consecutive stimulation pulses and through
the same electrode used for stimulation.
Figure 3.7: Biphasic current pulse.
32
In Figure 3.7 a biphasic pulse can be seen. The biphasic pulse can be characterized with those
five parameters [14] and . All the time related characteristics of the impulse
signal are relatively easy to control and define precisely, if a digital circuit with a reference clock
is used. However, for the biphasic pulse to do what it is supposed to, maintaining the charge
balance that is, and must be the same, or else charges would accumulate in the tissue
and cause tissue damage, even leading to necrosis. That is difficult to achieve, however it is
also imperative. In this thesis, mechanism to compensate this mismatch was not used.
However, an effort was made to minimize this mismatch, by choosing the right current mirrors.
The mismatch between transistors, which is the main reason for the biphasic pulse mismatch,
will be addressed in the layout chapter.
3.3.2 Output Impedance
The output impedance should be infinite, for the DAC to be an ideal current source, so the
objective is to use a topology that is as close to an ideal current source as possible. For that to
happen it needs to be independent of other circuits variables and to have an output impedance
as high as possible, being the output impedance the impedance seen by the circuit connected
to the DAC towards the DAC.
3.3.3 Area
Since output amplifier is to be replicated up to a thousand units as part of the stimulation circuit,
the area it occupies is important. The transistors were dimensions as small as possible, without
harming the match between positive and negative current.
3.3.4 High Voltage Swing
In order for the circuit to be useful, it needs to not only produce the correct pulse with the correct
amplitude, or have high output impedance, but it needs to be able to work when different values
of impedances are connected to its output. Since it generates a current that will flow through
such impedance, necessarily a voltage drop will appear. As the tissue and the electrode will be
at a certain potential, the power supply is only of 3.3 V and the circuit must produce not only a
positive but also a negative pulse. The circuitry between the electrode potential and the ground
or the supply terminal will have to work with, less that the interval between 3.3V and the
electrode potential in case of positive stimulus, and the electrode potential and ground with
negative stimulus. So, to achieve maximum voltage swing, the right topology must be chosen.
3.4 Topology
The topology used can be seen in Figure 3.8. The design chosen is very similar to the one used
in [3] with the difference that, the gain is four instead of thirty because we needed 100
instead of 400 .
33
Figure 3.8: Biphasic current output amplifier
The current from the DAC is passed into the biphasic current output amplifier. As is illustrated in
Figure 3.8, M1 and M2 form the reference branch of the wide swing cascode mirror with M5 and
M6 for the negative pulse, and M3 and M4 for the positive pulse. The MOS in the output stage
M9, M10, M5, M6 are four times wider than their mirror pairs M7, M8, M1 and M2 respectively,
in order for them to be able to mirror the maximum current from the DAC from 25 to 100 .
The wide swing cascode current mirrors are used in the output stage to achieve maximum
output current per supply voltage, this can be done while maintaining all the transistors in
saturation.
The bias voltages Vpcasc_max and Vncasc are generated in the reference circuit (multibias
bias). This voltages are generated in a way that they biases the transistors for maximum
current (25 µA for M1, M2, M3, M4, M8 and M10 and 100 µA for M11, M9, M7, M6) with an
overdrive voltage of 300 mV, in order for the transistors to have at least 80mV when the
minimum significant bit is activated. The use of a gain at the end of the circuit, although creating
a small error, allows the transistors in the DAC and the reference circuit to be four times smaller.
The biphasic pulse is obtained through the control of the charge and discharge bits A and C that
open or close the switches connected to M4 and M6. This will activate the positive pulse or the
negative respectively.
It would have been possible to use an inverter and use only one bit, to control both switches.
However, that would prevent the possibility of having a period between the pulses in which none
of the currents is activated, during when measures could be taken. That would also prevent the
possibility of having both the switches activated, for purposes of knowing the difference
between pulses (this feature will probably not be used, but since this is a testing circuit, the
choice was to leave all the possibilities open).
This control is obtained using an external digital controller, external in the way that it is not part
of this work, but will be developed for the same project.
34
Regarding the precision, an effort was made to minimize the errors as much as possible, while
addressing to the other requirements. To understand the measures taken to prevent mismatch
one as to know what causes this mismatch. The mismatch in this component is independent
from the rest of the circuit, as long as all the transistors are in saturation. What will cause the
mismatch of the currents is the difference between the current mirrored from M2 to M4, and the
current mirrored from M2 to M6, and the error in the current mirroring from M7 to M9.
Considering the above, a cascode topology was used and, as explained in the previous section,
that is the most precise topology that could be used. In addition, when deciding the dimensions
of the transistors, bigger lengths (2 and 1.5 instead of the minimum length 0.35 ) were
used. This minimizes the effects of channel length modulation (will be addressed in the layout
section).The results of the simulation showed an error of less than 30nA between the positive
and the negative impulse, and although this has no real meaning, at least we can say that the
topology chosen is suited for this application.
Table 3.5: Sizes of the output amplifier devices.
MOS M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
Width 6 6 6 6 24 24 12 12 48 48
Length 2 2 2 2 2 2 1.5 1.5 1.5 1.5
Max. current
25 25 2 25 100 100 25 25 100 100
In this circuit, a wide swing topology is used. Theoretically, the wide swing topology allows the
voltage headroom to be two overdrive voltages. That would be around 400mV but this circuit will
use up to 600 mV, why dos that happen?
The main problem is that it is impossible to bias optimally a transistor for a variable current,
using a fixed voltage. What one can do is bias the transistors in order for it to be in the
saturation region for a determined current interval. This is possible if one chooses the minimum
Figure 3.9: PMOS section of the Output Stage.
Figure 3.10 NMOS section of the Output Stage
35
VOD for the minimum current and then dimensions the circuitry around that transistor to leave
enough voltage room for it to be able to bear the maximum current while in saturation.
In this case, the fixed voltage Vpcasc_max allows both transistors M9 and M10 (in Figure 3.9) to be
in saturation while driving the maximum current to the output.
As one can see in Table 3.6, M9 has a VOD of 0.345 V and a VDS of 0.390V meaning that is
close to the saturation limit, thus is not wasting voltage. M10 has a VOD of 0.362 V and a VDS of
0.396V when the output resistance is 9.7kΩ. Recalling, the overdrive voltage must be this high
in order for the transistors to generate the maximum current.
In the minimum voltage case, the circuit does not behave as well as with maximum current. The
overdrive voltage is much smaller but, because Vpcasc_max remains the same, M9 has a VDS
of 0.672 V this will waste a lot of voltage headroom. Therefore, this topology is far from optimal
in the field of voltage swing, at least with a fixed Vpcasc_max.
This non-optimal behaviour results in the circuit being able to polarize a much smaller range of
output resistances. These results are easy to understand in table 3.6 where one can see de
voltage overdrive that is needed and the VDS that the transistors use, and the maximum
resistance that can be polarized is presented.
In Figures 3.10 to 3.14 are the plots of parametrical simulations where the output resistance
increases. One can see clearly, when the transistors leave the saturation region and the
current decreases. With maximum current, that would happen around 9.7kΩ and with minimum
current around 285kΩ.
Transistor Id [µa] VOD [mV] VDS [mV] Resistance [kΩ]
M9 96.87 345 393 9.7
3.14 82.45 672 285
3.14 82 89 285
-3.127 64.55 158 285
-3.127 59.7 596 285
36
Current in blue, voltage in pink.
Figure 3.12: Output resistance parametric simulation with minimum positive output current.
37
In this chapter the dimensioning of the circuit as long as the reasons for that, were presented. In
addition the advantages and disadvantages of the chosen topology where stated.
In the next chapter, the layout will be shown and explained.
38
4 Layout
In this section, the process of creating the layout will be explained. The measures that were
taken so that process errors could be minimized are theoretically analysed and discussed. A
consideration about the common concerns of layout design, process errors, and parasitic
effects caused by the interaction between the components of the layout will also be presented.
The process of laying out the circuit’s components is a late step on the circuit’s project;
however, it is a very important one. It is so important that, since the very beginning of the
project, some details have to be considered. Namely, one must remember that the components
must be sized in a way that they geometrically fit into each other, and in a way that it is possible
to use some techniques to improve matching between components. This way it is possible to
minimize the area and maximize the matching between the simulations and the pr

Documents

Microelectronics Circuits for Neuronal Sensing and Stimulation