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M.E. (Hons.) Microelectronics
Course Description
Core Courses
MEL G611 IC Fabrication Technology [3 2 !
Material properties; crystal growth and doping; diffusion;
oxidation; epitaxy; ion implantation;
deposition of films using CVD, LPCVD and sputtering techniques;
wet and dry etching and cleaning;
lithographic process; device and circuit farication; process
modeling and simulation!
MEL G621 "L#I Design [3 2 !
"ntroduction to #M$% and CM$% circuits; #M$% and CM$% processing
technology; CM$%
circuits and logic design; circuit characteri&ation and
performance estimation; structured design andtesting; symolic
layout systems; CM$% susystem design; system case studies!
MEL G631 $hysics an% Mo%elling o& Microelectronic De'ices [3
2 !
Physics and properties of semiconductor ' a review; pn (unction
diode; ipolar transistor; metal
semiconductor contacts; )*+ and M+%*+; M$%*+ and scaling; CCD
and photonic devices!
MEL G632 (nalog IC Design [3 2 !
-asic concepts; -"CM$% process and technology; current and
voltage sources; differential and
operational amplifiers; multipliers and modulators; phase'loc.
techniques; D'to'/ and /' to'Dconverters; micropower circuits; high
voltage circuits; radiation resistant circuits; filter design
considerations!
MEL G6)2 "L#I (rchitectures [2 2 )!
$verview of C"%C processor architectures; "nstruction set
architecture of C"%C processor;
hardware flow'charting methods; implementing microprocessor
logic from hard'ware flowcharts;
0"%C instruction set architecture; Pipelined execution of 0"%C
instructions; pipeline execution unit
design; control ha&ards; design of memory hierarchy!
Elective Courses
C# G3 *econ&igurable Co+puting [!
Overview of Programmable Logics. FPGA fabric architectures.
Logic Elements and SwitchNetworks. esign and S!nthesis of
"ombinational and Se#uential Elements. Placement and$outing.
Pi%elining and other esign ðodologies. Fine'grained and
"oarse'GrainedFPGAs. Static and !namic $econfiguration.
Partitioning. (ardware)Software Portioningand Partial Evaluation.
S!stolic Architectures.
EEE F)3) Digital #ignal $rocessing [3!
"ntroduction; design of analog filters; design of digital
filters1 2""0 and *"03; structures for the
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reali&ation of digital filters; random signals and random
processes; linear estimation and
prediction; 4iener filters; D%P processor architecture; D%P
algorithms for different
applications!
EEE G1, *F Microelectronics [!
"ntroduction; application of 0* electronics in modern systems;
asic concepts in 0* circuit design,
active 0* components1 various 0* diodes and transistors and
their circuit models, matching and
iasing networ.s, 0* amplifier design1 low power, low noise and
roadand amplifiers, 0* oscillator
design; negative resistance oscillator; dielectric resonator
oscillators, phase noise! 0* Mixers1
-alanced mixers; low noise mixers; noise in 0* circuits,
microwave transmitters and receivers!
EEE G12 E+be%%e% #yste+ Design [3 1 )!
"ntroduction to emedded systems; emedded architectures1
/rchitectures and programming of
microcontrollers and D%Ps! +medded applications and
technologies; power issues in system design;
introduction to software and hardware co'design!
EEE G613 (%'ance% Digital #ignal $rocessing [!
0eview of stochastic processes, models and model classification,
the identification prolem,
some field of applications, classical methods of identification
of impulse response and transfer
function models, model learning techniques, linear least square
estimator, minimum variance
algorithm, stochastic approximation method and maximum
li.elihood method, simultaneous state and
parameter estimation of extended .alman'filter, non'linear
identification, quasi lineari&ation,
numerical identification methods!
EEE G626 -ar%.are #o&t.are Co/Design [)!
*P5/ and /%"C ased design, Low'Power echniques in 0 +medded
%ystems $n'chipnetwor.ing! 6ardware %oftware partitioning and
scheduling, Co'simulation, synthesis and
verifications, /rchitecture mapping, 64'%4 "nterfaces and
0e'configurale computing!
MEL G623 (%'ance% "L#I Design [!
Deep sumicron device ehavior and models, "nterconnect modeling
for parasitic estimation,
Cloc. signals and system timing''Digital phase loc.ed loop
design, memory and array structures,
"nput7output circuits design, /%"C technology, *P5/ technology,
6igh speed arithmetic circuits
design,'Parallel prefix computation, Logical effort in circuit
design, Low power VL%" circuits'
/diaatic logic circuits, Multi threshold circuits, Digital
-"CM$% circuits, Design of VL%" systems!
MEL G626 "L#I Test an% Testability [!
*ault models and types; automated test generation for
cominational logic; test generation for
sequential logic; need for adding testaility logic; design for
testaility; /dhoc D* methods;
structured D*; test generation for delay fault; issues in analog
circuit testing and testaility!
MEL G6)2 "L#I (rchitectures [2 2 )!
$verview of C"%C processor architectures; "nstruction set
architecture of C"%C processor;
hardware flow'charting methods; implementing microprocessor
logic from hard'ware flowcharts;
0"%C instruction set architecture; Pipelined execution of 0"%C
instructions; pipeline execution unit
design; control ha&ards; design of memory hierarchy!
