CNU EE 7.2-1

Microelectronic Circuits II

Ch 7 : Differential and Multistage Amplifiers

7.5 Differential Amplifier with Active load7.6 Multistage Amplifiers

CNU EE 7.2-2

Differential Amplifier w/ Active Load§ Differential output - It decreases the common-mode gain & increases CMRR : difference between the drain voltages remains

zero in response to a common-mode input signal- It increases the differential gain by a factor of 2 (6 dB) because the output is the difference between two

voltages of equal magnitude and opposite sign- the first stage in an IC op amp : differential-in, differential-out- differential transmission minimizes its susceptibility to corruption with noise & interference, which

usually occur in a common-mode fashion

§ Three-stage amplifier

- Two differential-in, differential-out stages, A1 & A2- A differential-in, single-ended-out stage A3 : output is referenced to ground§ Question : conversion from differential to single-ended

CNU EE 7.2-3

Differential to Single-Ended Conversion

§ Drain resistance RD à constant-current source- Much higher voltage gain- savings in chip area- active-loaded differential amplifier & converting the output from differential to single-ended

§Differential-to-Single-ended conversion- First stage output = differential à high CMRR- Beyond the first stage output à converted from

differential to single-ended

§ Simple but inefficient approach for differential to single-ended conversion- Ignore drain current signal of Q1- Eliminate its drain resistor- Take the output between drain of Q2 and ground- Lose a factor of 2 (6 dB) in gain as a result of

“wasting” the drain signal current of Q1- A better approach to utilize the drain signal current

of Q1

CNU EE 7.2-4

Active-Loaded MOS Differential Pair

§ Circuit at equilibrium w/ perfect matching- vG1=vG2=common-mode equilibrium value = 0V- Perfect matching à drain current of Q1 & Q2 = I/2 à fed to I/2 at Q3 à replicated I/2 at current mirror at Q4à zero current to flow out to the next stage or to a load

- If Q3 & Q4 are perfectly matched in equilibrium àdrain voltage of Q3 & Q4 = VDD-VSG3

- DC bias voltage at the output node is defined by afeedback circuit rather than by simply relying on thematching of Q4 & Q3

MOS differential pair by Q1 & Q2loaded by current mirror by Q3 & Q4

CNU EE 7.2-5

Active-Loaded MOS Differential Pair

§ Circuit with a differential input signal applied - Small signal operation à remove dc supplies & I- Ignore ro of all transistors- Virtual ground at common-source of Q1 & Q2- Drain signal current at Q1 : i=gm1vid/2- Equal but opposite current i at Q2- i is fed to the input of Q3 – Q4 mirror à replica i in

the drain Q4- Output current 2i- Factor of 2 by a current mirror action à conversion

of signal to single-ended form (i.e., between theoutput node and ground) with no loss of gain

- In the absence of a load resistance, the output voltage is determined by the output current 2i andthe output resistance of the circuit

CNU EE 7.2-6

- Take ro into account and derive differential gain vo/vid- Since circuit is not symmetrical, a virtual ground &

differential half-circuit are not able to use - Output equivalent circuit for differential input signalsà find the short-circuit transconductance Gm

the output resistance Rothe gain GmRo

§Determining short-circuit transconductance Gm- short-circuited the output to ground to find Gm- Nonsymmetrical original circuit + shorted output to the

ground à almost symmetrical circuit because the voltage between drain of Q1 and ground is very smalland low resistance between drain of Q3 & ground isalmost equal to 1/gm3

- Invoke symmetry and virtual ground appear at the source of Q1 & Q2 à (b) circuit

Differential gain of the Active-loaded MOS Pair

CNU EE 7.2-7

÷ø

öçè

æ-»÷÷ø

öççè

æ÷ø

öçè

æ-=2

||||12 3

113

313

id

m

moo

m

idmg

vggrr

gvgv

mmmmmidm

idm

id

m

mm

idmgmo

gggggcevg

vgvgggvgvgi

====

÷øö

çèæ+÷÷

ø

öççè

æ=÷

øö

çèæ+-=

2143

23

14234

&sin222

mvid

om gv

iGo

=º=0

§Determining short-circuit transconductance Gm- Replace the diode-connected transistor Q3 by its equivalent resistance [(1/gm3)||ro3]- voltage vg3 at the common-gate node at the mirror = product of the drain current of Q1 (gm1vid/2)

and total resistance between the drain of Q1 & ground

for ro1 & ro3 >> (1/gm3)

- vg3 controls the drain current of Q4à current of gm4vg3,

Differential gain of the Active-loaded MOS Pair

- Gm = gm of each of two transistors of differential pair- In the absence of the current-mirror action,

Gm would be equal to gm/2

à

Ground at the output node à currents in ro2 & ro4 = 0

CNU EE 7.2-8

1,2

1

22212

21

22

1122212

>>==»

÷÷ø

öççè

æ++=++=

ommmmo

om

mo

minomoino

rggggr

rggr

gRrgrRR

42424244

||2

22 oox

xo

o

x

o

x

o

x

o

x

o

x

o

xx rri

vRrv

rv

rv

rv

rvi

rviii ==+=+=+=++= >

( )42 || oomomid

od rrgRGv

vA ==º oomd ArgA 21

21

==ooo rrr == 42

where, Ao is the intrinsic gain of MOS transistor

Differential gain of the Active-loaded MOS Pair§Determining the Output resistance RO - i enters Q2 and exits at its S

- i enters Q1 and exits at D to feed Q3 – Q4 mirror- Since 1/gm3

CNU EE 7.2-9

- single-ended active-loaded MOS differential amplifier : low common-mode gain, high CMRR- vicm : common-mode input signal, RSS : output resistance of the current source I- Unsymmetrical circuit à split RSS equally between Q1 & Q2 (b) à Q1 &Q2 : Common Source transistor w/ a large source degeneration resistance 2RSS

- Q1 & Q2 with degeneration resistance 2RSS à equivalent circuit composed of a controlled sourceGmcmvicm & an output resistance Ro1,2 (c)

Common-Mode Gain and CMRR

CNU EE 7.2-10

§Determining Gmcm : - short circuit the drain to ground for Q1 à (d)- Since 2RSS // ro1, voltage at S = voltage divider of 1/gm & (2RSS|| ro1) :

- short-circuit drain current io = current through 2RSS :

(7.141)

- Output resistance Ro1 = Ro of a CS transistor with an emitter degeneration resistance

- Same result for Q2

( )( )SSomoSSo RrgrRR 22 1111 ++=

Common-Mode Gain and CMRR

( )( ) ( ) icmmoSS

oSSicms vgrR

rRvv »+

=11

1

1||2||2

ssicm

omcm

ss

icmo Rv

iGR

vi2

12

=º= >

( )( )SSomoSSo RrgrRR 22 2222 ++=

CNU EE 7.2-11

Since Ro2 >> ro4 & Ro1 >> ro3 , gm4 = gm3 by gm4ro3 >> 1ro3 = ro4

Since RSS >> 1, at least ~ ro, Acm is small, common-mode rejection ratio (CMRR) :

for ro2 = ro4 = ro & gm3 = gm

cascode current source & Wilson current source à a large CMRR

vgs3 by multiplying Gmcmvicm by the total resistance between the d1node & ground

(7.145)

Output voltage vo by the output node

Substituting from i4 from (7.145) & for Gmcm from (7.141)

÷÷ø

öççè

æ-===

331434344

1||||m

ooicmmcmmgmgsm grRvGgvgvgi

úû

ùêë

é÷÷ø

öççè

æ--=

3314

24 1||||12||

moom

ss

ooicmo g

rRgR

Rrvv

ssmomss

o

icm

ocm RgrgR

rvvA

333

4

21

11

2-»

+-ȼ

( )[ ][ ] ( )( )SSmomSSmoomcm

d RgrgRgrrgAA

CMRR === 342 2||

Common-Mode Gain and CMRR

÷÷ø

öççè

æ-=

3313

1||||m

ooicmmcmg grRvGv

042

4 =+++o

o

o

oicmmcm r

vRvivG

CNU EE 7.2-12

§Practical transistor amplifier : a number of stages connected in cascade- The first (or input) stage :

à a high input resistance in order to avoid loss of signal level when the amplifier is fed from a high–resistance source

à large common-mode rejection à differential amplifier

- The middle stage : à bulk of the voltage gain, conversion of the signal from differential mode to single-ended mode,à shifting of the dc-level of the signal in order to allow the output signal to swing both positive

and negative- The last (or output) stage :

à low output resistance in order to avoid loss of gain when a low-valued load resistance is connected to the amplifier,

à supply the current required by the load in an efficient mannerà source follower

- Analysis of multistage amplifiers : a two-stage CMOS op amp & a four-stage bipolar op amp

Multistage Amplifiers

CNU EE 7.2-13

§Two-stage configuration- Popular CMOS op amp- VDD & VSS : +/-2.5V (0.5-mm), +/-0.9V (0.18-mm) - Reference bias current IREF- Current mirror Q8 & Q5 supplies

differential pair Q1-Q2 (PMOSinput stage) with bias current I

- W/L ratio of Q5 à I/IREF- Active load Q3 & Q4- 2nd stage Q6 : CS amplifier

loaded w/ current-source Tr. Q7- CC : negative-feedback path- No low-output-resistance stageà output resistance = (ro6||ro7)à not suitable for driving low-

impedance loadà drive a small capacitive load- Simple, good quality, very small

chip area

A Two-Stage CMOS Op Amp

CNU EE 7.2-14

§ Voltage gain- Voltage gain of 1st stage : A1 = -gm1(ro2||ro4)- 2nd stage current-source-loaded, common-source amplifier : A2 = -gm6(ro6||ro7) - Dc open-loop gain = product of A1 & A2 § Input offset voltage- Device mismatches in input stage à input offset voltage : random offset- systematic offset : another type even if all appropriate devices are perfectly matched- Systematic offset occurrence in two-stage CMOS op amp : two input terminals à ground- If input stages are perfectly balanced, the same drain voltage Q4 & Q3, (-VSS+VGS4) à (- VSS+VGS4) is fed to the gate of Q6 = VGS4 appears between G & S of Q6

- Drain current of Q6, I6 is related to drain current of Q4 (= I/2)

- In order for no offset voltage to appear at the output, I6 = current supplied by Q7, I7

- Condition for making I6 = I7 :

- If this condition is not met, a systematic offset will result

A Two-Stage CMOS Op Amp

( )( ) ( )24

66 ILW

LWI =

( )( ) ILW

LWI

5

77 =

( )( )

( )( )5

7

4

6 2LWLW

LWLW

=

CNU EE 7.2-15

§ Bias circuit that stabilizes gm- Bias current independent of both the supply voltage and the

MOSFET threshold voltage- Transconductance gm biased by the circuit is determined only by a

single resistor & the device dimension - Deliberately mismatched transistors, Q12 is 4 times wider than Q13- RB is connected in series with the source of Q12- RB determines bias current IB & transconductance gm12à should be accurate & stable :: off-chip resistor

- In order to minimize channel-length modulation effect on Q12, cascode transistor Q10 & matched diode-connected transistor Q11are included to provide a bias voltage for Q10

- p-channel current-mirror Q8 & Q9 replicates IB back to Q11 & Q13,and provides a bias line for Q5 & Q7

A Two-Stage CMOS Op Amp

CNU EE 7.2-16

( ) ( ) ( )( )( )

( )( )( ) ÷

÷ø

öççè

æ-=

÷÷ø

öççè

æ-=+=

12

2

1222

13

12

12

2

13

122

121213

LWLW

ILWCR

LWLW

RLWCIRI

LWCI

LWCI

BoxnB

BoxnBBB

oxn

B

oxn

B

m

mmm

>

>

§ Circuit operation- Current mirror (Q8, Q9) à same current at Q13 & Q12, IB (=IREF)

- Gate-source voltage of Q12 & Q13 : VGS13 = VGS12 + IBRB- Subtracting Vt from both sides

IB is determined by dimension ofQ12 , RB and ratio of dimension ofQ12 & Q13

A Two-Stage CMOS Op Amp

( ) ( )21313

212

12 21

21

tGSoxntGSoxnB VVLWCVV

LWCI -÷

øö

çèæ=-÷

øö

çèæ= mm

- gm12 is determined by RB and ratio of the dimension of Q12 & Q13- Since gm ~ , gm of each transistor whose bias current is derived from IB = a multiple of gm12- ith n-channel MOSFET ith p-channel MOSFET

- The above bias circuit employs positive feedback à Instability is avoided by making Q12 wider than Q13

( ) ( )( ) ÷÷ø

öççè

æ-== 122

13

12121212 LW

LWR

ggILWCB

mmBoxn >m

( )LWID( )( )12

12 LWILWI

ggB

iDimmi = ( )

( )1212 LWI

LWIgg

Bn

iDipmmi m

m=

CNU EE 7.2-17

§ Four-stage bipolar op amp- 1st stage : differential-in,

differential-out input stage Q1 &Q2 is biased by current source Q3

- 2nd stage : differential-in, single-ended output Q4 &Q5 is biased bycurrent source Q6 à loss of gainby a factor of 2 à active load

- 3rd stage : pnp transistor Q7 àshifting the dc level of the signal

- signal at C of Q5 is not allowedto swing below the voltage at Bof Q5 (+10V), and signal at C ofQ7 can swing negatively

: level shifting- 4th stage : output stage, emitter

flower Q8- Output operates around zero

volts

A Bipolar Op Amp

CNU EE 7.2-18

- b >> 1, |VBE| ~ 0.7V, Q6 =4 x area of Q3 & Q9 àignore base current

- i through diode-connectedQ9 = 0.5mA = i @ Q3, i @ Q6 = 2mA

- Q5 feeds differential pairQ1 & Q2 with 0.25mA àC of Q1 & Q2=[+15-0.25X20] = +10V

- E of Q4 & Q5 = [+10-0.7] =9.3V, Q4 & Q5 are eachbiased at 1mA à C of Q5 =[+15-1x3] = +12V à E ofpnp transistor Q7 = +12.7V,iE of Q7 = (+15-12.7)/2.3 = 1mA

- iC of Q7=1mA à C of Q7 =[-15+1X15.7]=+0.7V

- E of Q8 is 0.7V below B àoutput terminal 3 = 0V àiE of Q8 = [0-(-15)]/3 =5mA

A Bipolar Op Amp