Microcontroller: UART

Amarjeet Singh

February 12, 2012

Logistics

List of presentation topics on the course website List of project extensions on the course website Assignment-4:

Feedback Demo next week

SPI: Modes of Operation

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SPI vs I2C

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SPI more suited for applications that are thought as data streams (as opposed to reading/writing address locations in slave devices)

Gains efficiency in applications that take advantage of its duplex capability e.g. codec (that requires sending samples in and out)

Due to lack of built-in device addressing, SPI requires more hardware resources when more than one slave device is attached

But SPI more efficient and simpler in point-to-point links Cost and complexity of I2C does not scale with number of devices

With its collision detection and acknowledgement scheme, I2C is a

true multi-master bus

PIC24F: SPI

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Each device in the family supports 3 SPI modules (jointly called SPIx) Module supports operation in two modes

Standard mode – data is shifted through a single serial buffer

Standard Mode

PIC24F: SPI

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Each device in the family supports 3 SPI modules (jointly called SPIx) Module supports operation in two modes

Standard mode – data is shifted through a single serial buffer Enhanced buffer mode – data is shifted through 8-level FIFO

buffer

Enhanced Mode

PIC24F: SPI Standard Mode Master

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If using interrupts: Clear the SPIxIF bit in the respective IFSx register. Set the SPIxIE bit in the respective IECx register. Write the SPIxIP bits in the respective IPCx register to set the

interrupt priority.

Write the desired settings to the SPIxCON1 and SPIxCON2 registers with the MSTEN bit (SPIxCON1<5>) = 1.

Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission

(and reception) will start as soon as data is written to the SPIxBUF register.

PIC24F: SPI Standard Mode Slave

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Clear the SPIxBUF register. If using interrupts:

Clear the SPIxIF bit in the respective IFSx register. Set the SPIxIE bit in the respective IECx register. Write the SPIxIP bits in the respective IPCx register to set the

interrupt priority.

Write the desired settings to the SPIxCON1 and SPIxCON2 registers with the MSTEN bit (SPIxCON1<5>) = 0.

Clear the SMP bit. If the CKE bit is set, then the SSEN bit (SPIxCON1<8>) must be set to

enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).

PIC24F: SPI based WiFi Interface

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Interface with Microchip ZG2100 module over SPI and use the TCP/IP stack provided by Microchip

PIC24F: SPI based Ethernet Interface

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Interface with Microchip ENC28J60 module over SPI and use the TCP/IP stack provided by Microchip

PIC24F: SPI based 802.15.4 Interface

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Interface with Microchip MRF24J40 module over SPI and use the MRF module interface provided by Microchip

More about this interface when we discuss Zigbee

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Serial I/O: UART

UART: Universal Asynchronous Receiver Transmitter Translates data between parallel and serial form Universal designation indicates that the data format and transmission

speeds are configurable Actual electric signaling level and methods are typically handled

by a driver circuit external to UART USART: UART that can also communicate synchronously I/O interface converting parallel data from microprocessor for serial

communication and serial data on line to parallel for microcontroller

What typical hardware logic will be useful for serial/parallel conversion?

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Serial I/O: UART

No common clock but still need a way to detect bit boundaries: e.g. How do we differentiate between “00” and “000”

A clock transmitted along with data stream Useful where we need to send one character at a time and the

interval of time between each byte may vary Typical transmission format is 1 start bit in the beginning, 0/1 parity

bit after the data and 1 or 2 stop bits in the end of each character Receiver synchronizes its clock upon receiving the start bit and

samples the data (7 or 8 bits) If stop bits are received in correct sequence, receiver assumes

successful reception else an error is declared

If a UART is receiving 1 character (8 bits) per second transmitted with 1 parity and 2 stop bits, what is the bit rate on serial output?

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UART Examples

Multiple standards for voltage signaling RS-232 RS-485

Some signaling schemes do not use electrical wires Infrared Signal (IrDA) Bluetooth (in Serial Port Profile – SPP)

Error detection using parity bits A match of parity bit implies the transmission was correct What are different types of parity? What is the maximum number of bit errors that we can detect

with 1-bit parity?

CRC algorithm for more complex bit error correction and detection

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RS-232

Recommended Standard 232 Works for cable lengths up to 25 meters and data rates up to 38.4

kbps First introduced in 1962 RS-232 compatible serial port was a standard feature for serial

communication with many external devices attached with computers in 1990s

Replaced with USB these days Originally designed for connecting Data Terminal Equipment (DTE) to

Data Communication Equipment (DCE) DTE has a pin based connector DCE has a hole based connector

Either uses a 25-pin or 9-pin connector 9-pin connector more common

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RS-232 Signals

Standard signals – Tx (3), Rx (2), RTS (7), CTS (8), DTR (4), DCE Ready (6), Data Carrier Detect (1), Ring Indicator (9), Signal Ground (5)

Many of these signals are intended for modem control To form a simple signal between computer and a terminal, only

Tx, Rx and SG are required

Do you use any device that has RS-232 connection?

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Handshaking provides a flow control mechanism – prevents transmitter to send data at a rate higher than what receiver can handle

After transmitting a byte (or data packet) transmitter waits for receiver to send the signal confirming it is ready for next data

RTS (Request to Send) and CTS (Clear to Send) used for handshaking in RS-232

When the transmitter wishes to send, it asserts RTS indicating there is pending data

If the receiver is ready, it asserts CTS in response RTS/CTS added to make a minimal 5-wire serial interface with

hardware flow control Software handshaking (XON/XOFF) used when it is not possible to

have hardware hand shaking Uses two characters to represent “suspend transmission” (0x13)

and “clear to resume” (0x11)

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Implementing RS-232 Interface

RS-232 is unbalanced implies voltage levels are referenced to an internal ground

Logic high for RS-232 is signal voltage between -5 to -15 V Logic low is signal voltage between +5 and +15 V

Most microcontrollers, including xMega, PIC24F and AVR32 consists of UART within the chip

Need an external level shifter to convert the signals to/from RS-232 levels e.g. MAX3222

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RS-232: Signal Levels

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Using Serial Port as Power Supply

Some of the pins from RS-232 can be used to parasitically power embedded system from the host

Most signals can supply moderate amount of current (~50 mA)

What is the function of Diode? What chip do we use if the microcontroller is to be run by 5 V supply? What are other familiar components?

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RS-422

Uses difference between two lines (twisted pair/differential pair) to represent the logic level

Not referenced to local ground (unlike RS-232) Any noise will effect both the lines equally – hence can transmit

over long distances and at high speed (Support lengths up to 1200 meters) –

Used in MACs as serial port until 1998 (replaced by USB starting

iMAC)

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Implementing RS-422

Wide variety of RS-422 interface chips available E.g. using MAX3488

Connect Tx/Rx pairs of MAX3488 to UARTs within each embedded system

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RS-485

Variation of RS-422 to allow multiple systems to exchange data over single twisted pair

Based on master-slave architecture: Transactions initiated by master and a slave will transmit only when instructed to do so

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Interfacing RS-485

Use MAX3483 (RS-422 transceiver with enable inputs) Pins A and B to interface with twisted pair on network side Data Input (DI) and Receiver Output (RO) connected to Tx/Rx of

microcontroller respectively

What is the benefit of having transmitter enable as active high and receiver enable as active low?

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Implementing RS-485

Half-duplex mode

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Implementing RS-485

Full-duplex mode

To avoid the possibility of two nodes transmitting at the same time, designate one node as master and rest as slaves

Typically a maximum of 32 nodes are possible per network

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xMega: USART Module

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AVR32: USART Module

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PIC24F: UART Module

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Infrared Data Association (IrDA)

Point to point protocol using asynchronous serial transfer over short distances

Serial interface using pulses of infrared light to transmit data Common in laptops, PDAs and cellphones Also used for remote control of electronics IrDA is a consortium of over 150 companies that maintain and

develop the standard Assume that only two devices will be communicating and their

proximity will exclude interference from other IrDA devices Does not deal with collision and error detection issues

Overall guiding principle is that it should be cheap to implement IrDA specification 1.0 supported data rates between 2400 bps and

115.2 kbps over distances of 1 meter Devices negotiate the data rate up or down depending on their

capabilities – How is it different from RS-232?