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COE 381 MICROPROCESSORS
UNIT 4
INTEL PROCESSOR BASICS
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Chapter Objectives
Microprocessor Fundamentals
Major
Components of aComputer
MPU ModelLength of
Instructions Memory Map
Memory
Devices
Memory Readand Write Control
Signals
Input and Output
Cycles
Memory MappedIO and Separate
I/O Mapping
Address DecodingData Buses and
Tristate LogicMemory Access
Timing
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Chapter Objectives
The 8086/8088 Microprocessors, Interrupts and DMA
The 8088Microprocessor inCircuit
8086/8088 Memory andI/O Cycles
Interrupts
Direct MemoryAccess
Micro ComputerPerformance
Considerations
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MICROPROCESSORFUNDAMENTALS
SECTION 1:
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Outline of the Rest of Course
MPU Register set and Internal Architecture
MPU buses
Memory Considerations
MPU interfacing: Interrupts and DMA
Intel 8086 Architecture Serial interface
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MPU Fundamentals
For Simplicity look at a simple model of an
MPU
8-bit
64K address space
Intel style interface
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Simplified Block Diagram of a Microcomputer
MPU
MAINMEMORY
I/ODEVICES
(Ports)
Data Bus
Control Lines (Bus)
Address Bus
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Diagram of a Generic Microprocessor
Memory Addr Reg
GeneralRegisters
Program Counter
Stack Pointer
Internal Data Bus
Accumulator Temp Reg
ALU
C
Z
N
InstructionRegister
InstructionDecoder
Control Unit
RESET
Clock
IOR# IOW# MEMR# MEMW# INTR INTA#
ExternalDataBus
External Address Bus
MPU
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General Registers
Small set of internal registers - temporary data
storage
CU ensures that data from the correct register
is presented to the ALU
CU ensures that data is written back to correct
register
Accumulatorusually holds ALU result
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Status or Flags Register (Example)
O I T S Z A P C
Overflow Flag
Interrupt Flag
Trap Flag
Sign Flag
Zero Flag
Carry Flag
Parity FlagAuxiliary Flag
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Program Counter Register
Points to the next register to be executed
Called Instruction Pointer in Intel x86Architecture
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Stack Pointer
STACK: Part of memory where program data can be
stored by a simple PUSH operation
Restore data by a POP
Stack is in main memory and is defined by theprogram
Stack Pointer (SP) keeps track of the next location
available on the Stack Organised as a FILO Buffer
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Stack Exercise At the start of the following sequence the Stack Pointer has the value C000h.
The following code is executed
PUSH AL ; Push 8 bit accumulator data
PUSH PSW ; Push 8 bit flags register
What is the value of the SP at this point?
The following instructions are executed without any further stack activity in the
meantime
POP PSW ; Restore 8 bit flags register
POP AL ; Restore 8 bit accumulator data
What is the value of the SP at this point? Note how the POP order is the
reverse of the PUSH order.
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Simple Microprocessor Model
MPU Model8-bit
ProcessorClock
Reset
Address Bus16-bit
Uni-directional
Data Bus8-bit
Bi-directional
IOR#IOW#
MEMR#MEMW#
INTRINTA#
HLDA#
HOLD
I/O ReadI/O Write
Memory ReadMemory Write
InterruptControl
DMAControl
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Fetch-Decode-Execute
FETCH
DECODE EXECUTE
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Fetch-Decode-Execute (Memory)
MPUProgram
Memory MPUProgram
Memory MPUProgram
Memory
Address (IP) is sent to
memory via the address
bus
Instructiom Op Code is
read into the IR register
via the data bus for
decoding
Instruction is executed
Address Bus Address Bus Address Bus
Data Bus Data Bus Data Bus
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Instruction Cycle Examples
The following code fragment starts execution at address 0000h:
Machine
Code
Address Assembly Code Comments
F8 0000 CLC ;Clear Carry FlagA00040 0001 MOV AL, [4000h] ; Move contents of 4000h to Acc
A20020 0004 MOV [2000h], AL ; Move the Accumulator to 2000h
Execution Sequence: IP is the Program Counter in this example
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Memory MapAddress Bus: 16 bits, 216= 64K locations.
Data Bus: 8 bits (1 byte)
0000h
FFFFh
1 byte
64K possible locations,each one is 1 byte wide
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Simple Memory Devices (8K PROM & RAM)
8K bytes
OECE
Data
D0..D7
Address
A0..A12
(P)ROM
8K bytes
OECE
Address
A0..A12
RAM
Data
D0..D7
WE
Chip EnableOutput Enable
Chip Enable
Output Enable
Write Enable
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Memory Read and Write Cycles
Hardware Control lines used by the CPU to
Control reads and Writes to Memory
Active low signal RD# asserted for a Read
Cycle
Active Low signal WR# indicates a write
RD# and WR# signals supply timing
information to memory device
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Read Cycle
8K bytes
OECE
Address
RAM
DataD0..D7
WE
Chip Enable
Output EnableWrite Enable
Processor puts out
address on the AddressBus, e.g. 50000 0000 0000 0101(A)
Processor asserts theMemory Read signalMEMR# - (B)
Processor reads thecontents of the data bus(C)
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Read Cycle Timing Diagram
Program Address Data Address
Clock
AddressBus
RD#
DataBus
OpCode Operand
Valid Data
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Write Cycle
8K bytes
OECE
Address
RAM
DataD0..D7
WE
Chip Enable
Output EnableWrite Enable
Processor puts outaddress on the AddressBus, e.g. 90000 0000 0000 1001(A)
Processor asserts theMemory Write signalMEMW# - (B)
Processor writes the datato the RAM via the databus(C)
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Write Cycle Timing Diagram
Program Address Data Address
Clock
AddressBus
WR#
DataBus
Write
Data
Valid Data
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Input and Output Cycles
Intel Architecture processors have an I/O addressspace, separate from memory (Code and Data)
Allow I/O devices to be decoded separately frommemory devices
Use IOR# and IOW# signals for Input & Output
Exercise: Draw Input & Output Cycles following thememory cycle examples
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I/O Instructions
Separate I/O instructions cause the IOR# or
IOW# signals to be asserted MOV AL, (400Fh) ; instruction provides 16-bit address
IN AL, 2Ch ; instruction provides an 8-bit address
Some processors only support a single address
space - I/O devices are decoded in the
memory map
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Advantages of Memory Mapped I/O
I/O locations are read/written by normal
instructions - no need for separate I/O
instructions
Size of instruction set reduced
Memory manipulations can be performed
directly on I/O locations
No need for IOR# and IOW# pins
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Advantages of Separate I/O Mapping
All locations in memory map are available formemory
No block removed for I/O
Smaller, faster instructions can be used for I/O
Less Hardware decoding for I/O
Easier to distinguish I/O accesses in assemblylanguage
Which mapping system is preferable? Why?
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Processor with Multiple Memory
Devices
Processor
ROM0 ROM1 RAM0 RAM1
ADDRESS BUS
DATA BUS
CONTROL BUS
Microprocessor Systemwith ROM and RAM
How do you allow manymemory devices to drivethe same bus?
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Device Selection and Data Buses
A PC board may have many memory devices, allattached to the same data bus
When the processor reads data from the bus, it is
essential that only one device drives data ontothe bus
The other memories must be electrically
disconnected from the bus while the selecteddevice drives it
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Device Selection and Data Buses (2) Use Address Decoding to ensure only one device is
selected at a time
Use Tristate buffers to disconnect unselecteddevices from the data bus
Unselected devices have their outputs placed inthe HIGH IMPEDANCE STATEits as if theiroutputs were switched off
All outputs, except those of the selected deviceshould be in the High Impedance state
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TriState Buffers and Transceivers Simplest buffers have an Input, an Output and an Enable
Input
Enable signals may be active high or low
When Enable signal is active the output follows the input
When the Enable signal is inactive the output of the buffer
is effectively disconnected from the circuit
When the output is in High Impedance other devices can
drive the bus in question
Bidirectional buffers (transceivers) are essentially two
back-to back buffers
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TriState Buffers and Transceivers(2)
CPUs, RAMs and ROMs all have tristate-able bufferson their data buses
Microprocessors normally have tristate-able address
and control buses as well
Discrete buffer devices and transceivers can drivemore devices (loads) than RAMs and ROMS
74AC244 and 74AC245 are typical buffers andtransceivers
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TriState Buffer (1/8 74AC244)
OutputInput
Enable#
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Address Decoding
Processor
ROM0 ROM1 RAM0 RAM1
ADDRESS BUS
DATA BUS
CONTROL BUS
Microprocessor Systemwith ROM and RAM
How do you select justone memory device?
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Address Decoding
Need external decoding hardware to ensure that only one
device is accessed at any one time
Simple techniques enable the Chip Enable of just one device,
based on the address bus contents
Implement this system, consisting of 4 x (16K x 8) memories:
ROM0 - 0000h - 3FFFh
ROM1 - 4000h - 7FFFh
RAM0 - 8000h - BFFFh
RAM1 - C000h - FFFFh
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Simple Address Decoding exampleA15
/A15
A14
/A14
/CS_ROM0
/CS_ROM1
/CS_RAM0
/CS_RAM1
0000h
3fffh
ROM0
4000h
7fffh
ROM1
8000h
bfffh
RAM0
c000h
ffffh
RAM1
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Discrete Address Decoder
RAM0
A0..A13
D0..D7
/CE
/OE
/WEROM0
A0..A13
D0..D7
/CE
/OE
ROM1
A0..A13
D0..D7
/CE
/OE
RAM1
A0..A13
D0..D7
/CE
/OE
/WEMPU
A0..A13
D0..D7
/MEMR
/MEMW
A15
/IOR
/IOW
A14
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74AC138: 3-to-8 Decoder
Logic Diagram
Outputs
A
B
C
E1
E2
E3
138
0
1
2
3
4
5
6
7
Select
Inputs
Enable
Inputs
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Example: Fairchild 74AC138
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Address Decoder With 74AC138
0000h
3fffhROM0
4000h
7fffhROM1
8000h
bfffh
RAM0
c000h
ffffhRAM1
A14
A15
/CS_ROM0
/CS_ROM1
/CS_RAM0
/CS_RAM1
74AC138
/Y7
/Y6
/Y5
/Y4
/Y3
/Y2
/Y1
/Y0
C
B
A
E3
/E2
/E1
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Address Decoder With 74AC138
RAM0
A0..A13
D0..D7
/CE
/OE
/WEROM0
A0..A13
D0..D7
/CE
/OE ROM1
A0..A13
D0..D7
/CE
/OE RAM1
A0..A13
D0..D7
/CE
/OE
/WEMPU
A0..A13
D0..D7
/MEMR
/MEMW
A15
/IOR
/IOW
A14
74AC138
/Y7
/Y6
/Y5/Y4
/Y3
/Y2
/Y1
/Y0
C
B
A
E3
/E2
/E1
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Cascading 138s for MoreComplex Decoding
74138 generates a unique output for a givenbinary input
You can cascade 138s for more complex andprecise decoding
Each stage has a propagation delay associated
with it May affect your timing budget
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Cascaded 74138s
A
BC
E1
E2
E3
138
0
1
2
3
4
5
6
7
A
BC
E1
E2
E3
138
0
1
2
3
4
5
6
7
A
BC
E1
E2
E3
138
0
1
2
3
4
5
6
7
OUT A000
OUT A001
OUT A002
OUT A003
OUT A004
OUT A006
OUT A007
OUT A005
IN A000
IN A001
IN A002
IN A003
IN A004
IN A006
IN A007
IN A005
Log i c
High
Log i c
High
A13
A14
A15
SEL1
SEL5
SEL7
Log i c
High
MEMR
MEMW
A0
A1
A2
A0
A1
A2
SEL0
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Modern Decoding
Decoding in Motherboards is often done using
Custom devices or PLDs
Custom devices usually have 74138s as a
Library part
(P)ROM
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8K bytes
OECE
DataD0..D7
AddressA0..A12
( )
Address Input
CE#
DataOut Valid Data
ta
Valid dataavailable
Memory Access Timing
d l ( )
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Read Cycle (No Wait)
Address Input
DataOut
Valid Data
ta
CE#
MEMR#(= OE#)
Valid Memory Address
Memory Cycle Timee.g. 20ns
Set up Timetsu
l
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Example: ST EPROM 27C256
R d C l (W it St t )
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Read Cycle (Wait States)
Address Input
Data
OutValid Data
ta
CE#
MEMR#
(= OE#)
Valid Memory Address
Memory Cycle Time
e.g. 50ns
A Wait state has been
inserted in the processor
cycle to allow the memory
more time to respond
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8086/8088 MICROPROCESSORS;INTERRUPTS AND DMA
SECTION 2
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P BASED Computer Systems
Memory
SystemsMicroprocessor I/O System
Buses
Dynamic RAM (DRAM)
Static RAM (SRAM)Cache
Read-Only (ROM)
Flash Memory
EEPROM
8086
808880186
80286
80386
80486
Pentium
Pentium ProPentium II
Printer
Hard disk driveMouse
CD-ROM Drive
Keyboard
Monitor
Scanner
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Memory Transient Program Area
(TPA) 640Kb
System Area
384 Kb Extended Memory System
(XMS) over 4MB
Extended
Memory
System Area
384K bytes
TPA640K bytes
15M bytes in the 80286
31M bytes in the80386SL/SLC
63M bytes in the
80386EX
4095M bytes in the
80386DX, 80486, and
Pentium64G bytes in the Pentium
Pro and Pentium II
1M bytes of real
(conventional) memory
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Transient Program Area (TPA)
Free TPA
MSDOS Program
COMMAND.COM
Device Drivers such as MOUSE.SYS
IO.SYS Program
DOS communications area
BIOS communications area
Interrupt Vectors
9FFFF
9FFF0
08490
08E30
01160
02530
00500
00700
00400
MSDOS Programs
00000
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Transient Program Area (TPA)
Programs that control computer system
(Operating Systems)
Also contains data, drivers, and application
programs
Consists of RAM, ROM, EEPROM, and Flash
Memory
DOS controls memory organization and some I/O
devices
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Transient Program Area (TPA)
Interrupt Vectors contain addresses of interruptservice procedures
BIOS (Basic I/O system) area controls I/O devices
IO program allows use of keyboard, video display,printer, etc.
Command program controls operation ofcomputer through keyboard
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System Area
MSDOS Program
Free Area
Hard disk controller ROM
LAN controller ROM
Video BIOS ROM
Video RAM (Text area)
Video RAM (Graphics area)
FFFFF
F0000
E0000
C8000
B0000
C0000
A0000
BASIC language ROM (earlier PCs)
FFFF
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I/O Space
Addresses I/O ports
Up to 64K 8-bit devices
I/O Expansion Area
COM1
Floppy Disk Controller
LPT1
Hard disk Controller
COM2
8255 (PIA)
FFFF
03F8
03D0
03F0
0320
0378
02F8
CGA Adapter
0060
Timer (8253)
Interrupt controller
DMA Controller
0040
0020
0000
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Microprocessor
Data transfer between itself and memory or I/Osystem
Using data, address, and control buses
Simple arithmetic and logic operations Add, Sub, Mul, Div, AND, OR, NOT, NEG, Shift, Rotate
Data width: byte (8-bit), word (16-bit), and doubleword (32-bit)
Program flow via simple decisions Zero, Sign, Carry, Parity, Overflow
Why is it so important?
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Computer System Block Diagram
P
Address Bus
Read-onlyMemory
ROM
Read/Writememory
RAM
Keyboard Printer
MWTC
MRDCIOWC
IORC
Data Bus
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Computer System
Bus is a common group of wires for
interconnection
Address Bus: 16-bit for I/O and 20 to 36-bit for
memory (20 for 8086)
Data Bus: 8 to 64-bit, the wider the bus, the
more data can be transferred (16 for 8086)
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Computer System
Control Bus: contains lines that selects the
memory or I/O to perform a read or write
operation
Four main control lines
MRDC (memory read control)
MWTC (memory write control)
IORC (I/O read control) IOWC (I/O write control)
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Intel Microprocessor Architecture Operation Modes
Real: uses 1stM byte of memory in all versions
Protected: uses all parts of memory in 80286 andabove
Register Types Program Visible: used during application programs
Program Invisible: not directly addressable, but usedby system
Program Visible Registers 4 Data Registers, 4 Pointer/Index Registers, 4-6
Segment Registers, Instruction Pointer, and Flags
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Compatibility is a successful strategy
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Compatibility is a successful strategy
Register A may be used as 8-bit (AH and AL), 16-bit
(AX), and 32-bit (EAX) for the later Pentium processors
e.g. ADD AL, AH; ADD DX, CX; ADD ECX, EBX
Instructions only affect the intended part of a register
Later P versions support earlier version codes
Some registers are Multipurpose, some are Special
Purpose
Segment Registers generate memory addresses
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Intel 8086/8088 Microprocessors
Intel 8086 and 8088 Microprocessors are the
basis of all IBM-PC compatible computers(8086 introduced in 1978, first IBM-PC released in 1981)
All Intel, AMD and other advanced
microprocessors are based on and are
compatible with the original 8086/8
At Power Up and Reset time, Pentiums,Athlons etc all look like 8086 processors
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Intel 8086/8088 Microprocessors
Intel 8086 is a 16b microprocessor: 16b data registers, 16b ALU
Width of external data bus: 8086: 16b
8088: 8b
Width of external address bus: 16b+4b=20b
Some techniques to optimise the CPU performancewhen its executing programs
Segment: Offset memory model
Little-Endian Data Format
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8086/8088 (1)
Original IBM PC used 8088 microprocessor
8088 is similar to the 8086, but it has an external 8b
data bus & only 4B-deep queue
For cost reduction reasons
We can consider 8086 and 8088 together
PC clones often used 8086 for better performance
8-bit bus reduces performance, but meant cheaper
computers
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8086/8088 (2)
Remember the Fetch-Decode-Execute cycle?
Fetching from EXTERNAL MEMORY is SLOW
The 8086/8 used an instruction queue to speed
up performance While the processor is decoding and executing
an instruction, its bus interface can be reading
new instructions, since at that time the bus isnot actually in use
8086/8088 Functional Units
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8086/8088 Functional Units
Execution Unit
(EU)
Bus Interface
Unit(BIU)
Fetches Opcodes,Reads Operands,
Writes Data
8086/8088 MPU
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8086/8088 (3)
8086/8088 consists of two internal units
The execution unit (EU) - executes the instructions
The bus interface unit (BIU) - fetches instructions,reads operands and writes results
The 8086 has a 6B prefetch queue
The 8088 has a 4B prefetch queue
8086/8088 Internal Organisation
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/ g
Temporary
Registers
ALU
Flags
EU
Control
AH AL
BH BL
CH CL
DH DL
SP
BP
DI
BI
CS
DS
SS
ES
IO
InternalCommunications
Registers
SUMMATION
Address Bus 20 bits
Data Bus
BusControl
1 2 3 4
Instruction Queue
8088
Bus
EU BIU
IP
BIU Elements
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BIU Elements
Instruction Queue: the next instructions or data can be
fetched from memory while the processor is executing thecurrent instruction
The memory interface is slower than the processor execution time so
this speeds up overall performance
Segment Registers: CS, DS, SS and ES are 16b registers
Used with the 16b Base registers to generate the 20b address
Allow the 8086/8088 to address 1MB of memory
Changed under program control to point to different segments as a
program executes
Instruction Pointer (IP) contains the Offset Address of the
next instruction, the distance in bytes from the address given
by the current CS register
8086/8088 20-bit Addresses
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8086/8088 20 bit Addresses
16-bit Segnment Base Address 0000
16-bit Offset Address
20-bit Physical Address
CS
IP
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Exercise: 20-bit Addressing
1. CS contains A820h,IP contains CE24h.
What is the resulting physical address?
2. CS contains B500h, IP contains 0024h.
What is the resulting physical address?
8086/8 In Circuit (1)
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8086/8 In Circuit (1)
8086/8 microprocessors need supportcircuits in a microcomputer system
8086/8 multiplex the address and data
buses on the same pins
This saves pins but at a price:
Demultiplexing logic is needed to build upseparate address and data buses to interface
with RAMs and ROMs
MAXIMUMMODE
MINIMUMMODE
1 40GND Vcc
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1 40
20 21
8086
GND
AD14
AD13
AD12
AD11AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
AD15
A16,S3
A17,S4
A18,S5A19,S6
/BHE,S7
MN,/MX
/RD
/RQ,/GT0
/LOCK
/S2
/S1
/S0
QS0
QS1
/TEST
READY
RESET
/RQ,/GT1
HOLD
/WR
IO/M
DT/R
/DEN
ALE
/INTA
HLDA
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MAXIMUMMODE
MINIMUMMODE
1 40
20 21
8088
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
A15
A16,S3
A17,S4
A18,S5
A19,S6
MN,/MX
/RD
/RQ,/GT0
/LOCK
/S2
/S1
/S0
QS0
QS1
/TEST
READY
RESET
/RQ,/GT1HOLD
/WR
IO/M
DT/R
/DEN
ALE
/INTA
HLDA
high /SS0
MAXIMUM
MODE
MINIMUM
MODE
1 40
20 21
8086
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
AD15
A16,S3
A17,S4
A18,S5
A19,S6
/BHE,S7
MN,/MX
/RD
/RQ,/GT0
/LOCK
/S2
/S1
/S0
QS0
QS1
/TEST
READY
RESET
/RQ,/GT1HOLD
/WR
IO/M
DT/R
/DEN
ALE
/INTA
HLDA
8086/8 I Ci i (2)
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8086/8 In Circuit (2)
In Maximum Mode the 8086/8 needs atleastthe following: 8288 Bus Controller,
8284A Clock Generator, 74HC373s and
74HC245s
With the aid of these devices the 8086
begins to look like the idealmicroprocessor we looked at earlier
i8086 Circuit - Maximum Mode
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74LS245
x2
8284A
Clock
Generator
RDY
Vcc
8086
CPU
CLK
READY
RESET
MN/MX#
S0#S1#S2#
8288
Bus
Controller
MRDC#
MWTC#
AMWC#IORC#
IOWC#
AIOWC#
INTA#
CLK
74LS373
x3ADDR/ DATA
LEOE#
ALE
DENDT/R#
BHE#
AD15:AD0
A19:A16
74LS245
x2
EN#DIR
D15:D0
A19:A0,
BHE#
ADDR/Data
INTR
i8086 Circuit - Maximum Mode
8086/8 M i M d
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8086/8 Maximum Mode
In maximum mode, the 8288 uses a set of
status signals (S0, S1, S2) to rebuild the normal
bus control signals of the microprocessor MRDC#, MWTC#, IORC#, IOWC# etc
Equivalent to MEMR# etc
RESET# Si l
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RESET# Signal
The Active low RESET# signal puts the 8086/8 into a
defined state
Clears the flags register, segment registers etc. Sets the effective program address to FFFF0h
(CS=0F000h, IP=0FFF0h)
8086/8 Programs always start at FFFF0H after Reset
has been asserted and removed
Continues into latest generation CPUs
BHE# Si l (8086 O l )
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BHE# Signal (8086 Only) The 8086 processor can address memory a byte
at a time
Its data bus is 16b wide
It uses the BHE# signal and A0 (sometimes
called BLE#) to address bytes using its 16b bus
Use of BHE#/A0(BLE#)
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/ ( )
FFFFFFFFFD
FFFFB
FFFF9
00005
00003
00001
ODD Addresses (8086)
FFFFEFFFFC
FFFFA
FFFF8
00004
00002
00000
EVEN Addresses (8086)
A19..A1 A19..A1
D15:D8 D7:D0
FFFFFFFFFE
FFFFD
FFFFC
00002
00001
00000
Byte-Wide addressing(8088)
BHE# A0/BLE#
U f BHE#/BLE#
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Use of BHE#/BLE#
BHE# A0/BLE# Selection
0 0 Whole word (16-bits)
0 1 High byte to/from odd
address
1 0 Low byte to/from even
address
1 1 No selection
ALE d Add /d t B M lti l i
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ALE and Address/data Bus Multiplexing
8086/8 Multiplexes the Address and Data
signals onto the same set of pins
Need off-chip logic to separate the signals
Transparent latches designed just for address
demultiplexing
ALE and 74HC373 Transparent Latch
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p
Address
Time
Clock
Address/
Data
Bus
Data Time
ALE
Output of
74HC373Microcomputer AddressBus
LE
OE#
ALE
Address/
Data Bus
System Address BusIn0:In7 Q0:Q7
74HC373 or equivalent
TriState Control signal,
OE#, shown connected to
GND for simplicity
U f ALE (Add L h E bl )
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Use of ALE (Address Latch Enable)
ALE is used with an external latch (74HC373) to
demultiplex the address and data lines
74HC373 is transparent when its LE input(connected to ALE) is high
When ALE goes low, the 373 holds the last data
until ALE goes high again
8288 Bus Controller and Bus
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Transceivers
8288
Bus Controller
DIR
DEN#DT/R#
74HC245
EN#
74HC245
EN#
DIR
DIR
CPU [D15:D8]
CPU [D7:D0]
Buffered [D15:D8]
Buffered [D7:D0] To
MemoryandI/O
Systems
8288 Bus Controller also
generates Direction andEnable signals for Bi-
Directional Transeivers
Supports Buffering the
System Data Bus
8086 Read Cycle
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yT1 T2 T3 T4
Address Status
001 or 101
Address Valid Datafloat float
Valid Address
CLK
/S0, /S1, /S2
A16..A19, /BHE
ALE
AD0..AD15
A0..A19
S3..S6
DT/R
DEN
/MRDC or /IORC
8086 Write Cycle
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yT1 T2 T3 T4
Address Status
010 or 110
Address Valid Data
Valid Address
CLK
/S0, /S1, /S2
A16..A19, /BHE
ALE
AD0..AD15
A0..A19
S3..S6
DT/R
DEN
/MWTC or /IOWC
8086 Read Cycle (1 Wait State)
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T1 T2 T3 Tw
Address Status
001 or 101
Address Valid Datafloat float
Valid Address
CLK
/S0, /S1, /S2
A16..A19, /BHE
ALE
AD0..AD15
A0..A19
S3..S6
DT/R
DEN
/MRDC or /IORC
T4
8284 RDY
READY
8086/8088 Summary
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8086/8088 Summary First Generation (introduced June 1978)
One of the first 16b processors on the market
16b internal registers
16/8b external data bus
20b address bus (1MB addressable)
Used in 1stgeneration IBM PCs (1981)
80186/80188
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80186/80188
Evolution of 8086/808880186/80188
Increased instruction set
On-chip system components (Clock generator,DMA, Interrupt, Timers)
Unsuccessful in PCs
Popular in embedded systems
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Interrupts
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Interrupts
Used to Halt the normal flow of instructions
Exceptions can be due to Hardware or Software
Hardware Interrupts are asynchronous to the
processor
Could be asserted by an external device requestingaction, e.g. a port ready to transfer data
Interrupts can be globally masked by the processors
Interrupt Enable Flag (IE or I) IE is set by STI and reset by CLI (or equivalent)
Maskable & Non Maskable Interrupts
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Maskable & Non Maskable Interrupts
Maskable interrupts can be enabled/disabled using aflag (usually in the flags register
Non Maskable Interrupts (NMI) are top priorityinterrupts that cant be masked out
NMIs often used for Parity Errors, Power fails etc
NMI Example
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Power FailMonitor
Parity ErrorDetector
MPU
NMI
INTR
I/ODevice
Interrupts
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Main Program
Complete Current Instruction
PushFlags Register onto StackPush Instruction Pointer onto Stack
Clear Interrupt Enable Falg
Trap to Start of ISR
Interrupt Receiv ed
Pop f lags from the stack
Pop Instruction Pointer f rom the stack
Resume at restored IP address
Main Program
Resumes
Operations shown in
boxes are carried
automatically by MPUhardware
ISR
Push Registersonto the Stack
BODY of the ISR
Pop Registers
from the Stack
Return From Interrupt
Interrupt with Fixed ISR
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Interrupt with Fixed ISR
Interrupt with Fixed ISR
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Interrupt with Fixed ISR
Vectored Interrupt
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Vectored Interrupt
Vectored Interrupt
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Vectored Interrupt
DMA
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DMA
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Determining Source of Interrupt
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Determining Source of Interrupt
Real Mode Memory Addressing
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Real Mode Memory Addressing
Location = Segment + Offset
Segment address located in a
segment register; always
appended with 0H
Segments always have length of
64 Kb
64K byte
segment
Real mode memoryFFFFF
1FFFF
1F000
10000
00000
1 0 0 0
Offset = F000
Real Mode Memory Addressing cont
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Real Mode Memory Addressing cont
Offset or displacement selects locationwithin 64 Kb of segment
e.g. 1000:2000 gives location 12000H
Default Segment and Address Registers
e.g. code segment and instruction pointerCS:IP and stack segment and stack pointer
SS:SP
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Protected Mode Memory Addressing
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y g
Accessed via segment and offset address, but Segment register contains a selector
Selector selects a descriptor from descriptor table
Descriptor: memory segment location, length, and
access right
Addressing Modes
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g
Data Addressing Modes
Intel family supports 8 data addressing modes
Modes differ in the location of data and
address calculations
All modes involve physical address generation
Addressing Modes cont
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g
Consider MOV opcode as example: MOVAX, BX
Opcode or operation code tells P which
operation to perform
Source operand is to the right
Destination operand is to the left
Addressing Modes
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g
Register Addressing: MOV CX, DX Copy content of source register to destination register
Source and destination must be of the same size
Immediate Addressing: MOV AL, 22H
Transfer the immediate data into destination register
This is called constant data, but data transferred from
a register is a variable data
Addressing Modes
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g
Direct Addressing: MOV CX, LIST
Move a byte or word between a
memory location and a register
Memory address, instead of data,
appears in the instruction
Addressing Modes
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g
Register Indirect Addressing: MOV AX, [BX] Transfer data between a register and a memory
location addressed by a register
Sometimes need using special assemblerdirectives BYTE PTR, WORD PTR, DWORD PTR,when size is not clear
FOR example MOV DWORD PTR [DI], 10H insteadof MOV [DI], 10H
Addressing Modes
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g
Base-plus-index Addressing: MOV [BX+DX], CL Transfer data between a register and a memory
location addressed by a base register and an index
register
Register Relative Addressing: MOV AX, [BX+4]
Move data between a register and a memorylocation addressed specified by a register plus a
displacement
Addressing Modes
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g
Base relative-plus-index Addressing:
MOV AX, ARRAY[BX+DI]
Transfer data between a register and a memory
location specified by a base and index register plusa displacement
Another example is MOV AX, [BX+DI+4]
Addressing Modes
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g
Scaled-index Addressing: Not used by 8086 (used by 80386 and later
processors)
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Program Memory-Addressing Modes
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Three forms, used with JMP and CALLinstructions
Direct Program Memory Addressing:
JMP Label
Like GOTO or GOSUB in BASIC language
Allows going to any location in memory for nextinstruction
Program Memory-Addressing Modes
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Relative Program Memory Addressing: JMP [2] Jump relative to instruction pointer (IP)
Indirect Program Memory Addressing: JMP AX Jump to current code segment location addressed
by content of AX
Other examples: JMP [DI+2[] and JMP [BX]
Stack Memory-Addressing Modes
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Stack is a LIFO (last-in, first-out memory) Data are place by PUSH and removed by POP
Stack memory is maintained by stack segment register(ss) and stack pointer (sp)
When a word is pushed, high 8 bits are stored at SP-1low 8 bits are stored at SP-2, the SP is decremented by2
When a word is poped, low 8 bits are removed from
location addressed by SP, high 8 bits are removedfrom location addressed by SP+1, then SP isincremented by 2
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Instruction Encoding
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Assembler translates assembly code intomachine language
Machine language is the native binary code P
understands
WD
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First byte of instruction: opcode
First 6 bits of instruction are the binary opcode
Direction bit (D) determines the direction of data
flow
Width bit (W) determines data size: 0 for byte, 1
for word and double word
Opcode
Second byte of instruction: MOD-REG-R/MMOD REG R/M
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MOD specifies addressing mode for instruction and
whether displacement is present
If MOD=11, then register addressing mode, else
memory addressing mod In register addressing mode, R/M specifies a register
In memory addressing mode, R/M selects a mode
from table
If D=1, data flow to REG from R/M, if D=0 data flow to
R/M from REG
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Intel Family Instruction Set
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PUSH and POP for stack operations
Load Effective Address LEA loads a 16- or 32-bit register with offset address
LDS, LES, LFS, LGS, and LSS load a 16- or 32-bit registerwith offset address and a corresponding segmentregister DS, ES, FS, GS, or SS with a segment address
String Data Transfer Uses destination index (DI) and source index (SI)
registers
Two modes: auto-increment (D=0) and auto-decrement (D=1)
Intel Family Instruction Set cont
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By default DI access data in extra segment and SI in
data segment
LODS loads AL, AX, or EAX with data addressed by SI indata segment and increments or decrements SI
STOS stores AL, AX or EAX at the extra segmentaddressed by DI and increments or decrements DI
REP STOS repeats the instruction the number of timesstored in CX, i.e. terminates when CX=0
Intel Family Instruction Set cont(2)
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MOVS is the only instruction that transfers databetween memory locations
INS transfers data from I/O device into extra segment
addressed by DI; I/O address is in DX register
OUTS transfers data from data segment memoryaddressed by SI to an I/O device addressed by DX
For inputting or outputting a block of data INS and OUTSare repeated
Intel Family Instruction Set cont(3)
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Miscellaneous Data Transfer Instructions
XCHG exchange contents of a register with any
other register or memory location
IN and OUT instructions perform I/O operations
Two I/O addressing modes: fixed-port and variableport
Intel Family Instruction Set
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Segment Override Prefix May be added to any instruction to deviate from
default segment
Arithmetic and Logic Instructions
ADD simply adds two numbers and sets the flags
ADC adds also the carry flag (C) INC adds one to a register or memory location
Arithmetic and Logic Instructions
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SUB subtracts two and sets the flags
SBB subtract-with-borrow also subtracts (C) fromdifference
DEC subtracts one from a register or memorylocation
CMP is a subtract that only changes the flag bits;this is normally followed by a conditional jumpinstruction
Arithmetic and Logic Instructions
cont
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cont
Multiplication can be unsigned (MUL) or signed(IMUL)
Division can also be unsigned (DIV) or signed
(IDIV)
Basic logic instructions are AND, OR, XOR, NOT
TEST is like CMP, but for bits zero flag Z=1 if bit is0 and Z=0 if bit is 1
Arithmetic and Logic Instructions
cont(2)
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cont(2)
TEST performs AND operation, so TEST AL,1tests the first bit and TEST AL,128 tests the
last bit of a byte in AL
NOT is logical inversion or ones complement
NEG is arithmetic sign inversion or twoscomplement
Intel Family Instruction Set
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Shift and Rotate Instructions
SHL and SHR are logical shift left and right thatinsert 0 and put one bit in the carry flag C
SAL and SAR are arithmetic shift operations; SAL issimilar to SHL, but SAR is different than SHRbecause it inserts the sign bit instead of 0
Rotate instructions rotate data from one end toanother, ROL (rotate left) and ROR (rotate right),or through the carry flag (RCL and RCR)
Intel Family Instruction Set cont
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String Data Comparing String scan instruction SCAS compares register A
with memory
Compare string instruction CMPS compares two
memory locations