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Micro-RDCMicroelectronics Research Development Corporation
A Programmable Scrubber forFPGAs
ACKNOWLEDGMENT OF SUPPORT: This material is based upon work supported by the United States Air Force under Contract No. FA9453-08-M-0096. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the United States Air Force.
G. Alonzo [email protected]
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Summary of reported solutions
Commonly implemented: Blind scrubbing NASA/GSFC Radiation effects analysis group V4 scrubber (06/2007)
Some examples of read, detect, scrub Sandia-Xilinx Virtex FPGA SEU experiment on the International
Space Station. Cross scrubbing between V4 and V5. LANL flight experiment for Virtex I and its derivations BYU ICAP-based scrubber. Uses picoblaze Radix4 configuration scrubber Aeroflex Scrubber, an implementation of 989 XAPP 714: self scrubber, not longer supported XAPP 779: V2 scrubber XAPP 988: V4 scrubber XAPP 989: lastest supported solution from Xilinx (V2/V4)
Commercially available solutions
Radix4 consulting Works only for VirtexII family Can be implemented as a peripheral or as stand alone Mitigate SEUs and SEFIs Uses 8-bit SelectMAP or ICAP
Ref.: Radix4 Configuration Scrubber datasheet
Commercially available solutions
Aeroflex Implements Xilinx's scrubber (XAPP989) on an Eclipse RadHard
FPGA For Virtex 4 family Corrects and detect SEU Uses 8-bit SelectMAP Uses single CRC32
for the whole bitstream Identifies SEFI's Scrubs by pulling down
PROG_B (whole device) Doesn't support frame-based
scrubbing
Ref.: Aeroflex's XRTC 2009 presentation
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Design specification
Read/Write access to a memory-like configuration storage.
Error detection and correction using SECDEC or alternative.
Small footprint (originally thought as a “self-scrubber”).Flexibility to implement different scrubbing rates and
strategies, support different families and interfaces.Deal with scrubber's own susceptibility to SEU (TMR?).Others: Heartbeat signal, status and statistics on errors
reporting capabilities, re-programming.
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Architecture
Femto: 8 bit, single cycle, micro-coded, “controller”
“small footprint ...”
“error detection ..”
“flexibility ...” “read/write access ...”
FemtoCntrl: instructions
FemtoCntrl: Program example
PROM organization for Femto
Femto Flow
S-ASIC for rad-hard implementation
A Low-Cost Solution for Low-Volume, Advanced Radiation-Hardened IC’s
MPW Reticle → 10 Die w/Various Features
Femto's numbers
It currently occupies ~522 slices XAPP989: ~ 200 to 1200 slices. Others ??
Time to scrub ~ 0.2 sec (8bits @20 MHz for 32Mbit PROM) Instruccion memory: 256 instructions CRC16 code book : 1024
Agenda
RequirementsOther reported solutionsDesign specificationExtended FeaturesStatus and testing plan
Scrubber extended features
Selective scrubbing: flexible to implement different scrubbing rates and strategies
Scrubber extended features
Flexible deployment
Scrubber extended features
Support for other FPGA families or other devices (e.g. memories?)
Scrubber extended features
data
0 0 0Q0 Q1 Q2
D D D QQQ_Q
_Q
_Q
clock
data
1 0 1Q0 Q1 Q2
D D D QQQ_Q
_Q
_Q
clock
data
0 0 0Q0 Q1 Q2
D D D QQQ_Q
_Q
_Q
clock
data
1 0 1Q0 Q1 Q2
D D D QQQ_Q
_Q
_Q
clock
time = 0
FPGA had its configuration just loaded and the registers are at reset
time = XFPGA have been working for a while
and the shift register has valuable data on it.
Shift register implemented with Distributed RAM (SRL)
time = YFPGA has its configuration reloaded
due to the presence of an upset. The shift register contents are reset, content
is lost. Time = X is required to recalculate contents
time = Y
Alternative solution. FPGA has its configuration reloaded. Scrubbing
is used to set the shift register value to predefined state.
State reloading
Agenda
Summary of reported solutionsDesign specificationArchitectureExtended FeaturesStatus and testing plan
Agenda
RequirementsOther reported solutionsArchitectureExtended FeaturesStatus and testing plan
Testing Plan
Supporting components: Formal verification plan for software components (flow) and RTL (Q3-09)
Static testing: Fault injection / scrubbing automatic test (Q3-09)
Dynamic testing Synthetic : Fault injection / detect / scrub / error
monitoring (Q4-09) Proton testing: radiate / detect / scrub / error
monitoring (Q1-10)
