7
JOM • September 2005 24 Phase Transformations Overview Editor’s Note: A hypertext-enhanced version of this article is available on-line at www.tms.org/pubs/journals/JOM/0509/Chen- 0509.html. This article presents an overview of the recent developments in the fundamental understandings and microelectronics applications of metal silicides. The syn- thesis and characterization of nanoscale silicides with potential applications in nanotechnology are reviewed. INTRODUCTION Metal silicide thin films are integral parts of all microelectronics devices. They have been used as ohmic contacts, Schottky barrier contacts, gate elec- trodes, local interconnects, and diffusion barriers. With advances in semiconduc- tor device fabrication technology, the shrinkage in line width continues at a fast pace. The International Technol- ogy Roadmap for Semiconductors (ITRS) predicted that in 2005, in the 90 nm generation devices, the gate length and thickness of silicide at the contact window would be 32 nm and 20 nm, respectively. In the year 2007, for the 65 nm generation devices, these numbers are predicted to further decrease to 25 nm and 17 nm, respectively. 1 In addition, more transistors will be incorporated in one chip. However, owing to the demand for increased integration level, the sur- face area will not be adequate to meet Metal Silicides: An Integral Part of Microelectronics L.J. Chen the interconnect demand. Multi-level interconnections provide flexibility in circuit design and a substantial reduction in die size and, thus, chip cost. Figure 1 shows a scanning electron microscope (SEM) cross section of a six-level metal backend structure. Electrical connec- tion between the various metal layers is provided by vertical interconnects commonly referred to as vias. See the sidebar for device application details. SILICIDE FORMATION The impetus for the study of silicide formation on silicon was stimulated by the expectation of device applica- tions of silicides in the late 1970s and early 1980s. Two review chapters have succinctly summarized the knowledge accumulated up to the early 1980s. 6,7 This article focuses on the most important developments in recent years. Solid-State Amorphization In device applications, interfacial reactions of metal thin films with silicon are rather peculiar in that polycrystalline metal film reacts with single-crystal sili- con. The substrate is covalently bonded and the thin film is metallic. As a result, the microstructure of the silicide film and orientation of the substrate may play an important role in influencing the reaction. Some silicides can form at a temperature as low as 100°C. The mechanism for the break up of silicon bonds at such a low temperature is rather intriguing. 7 Fur- thermore, the silicide phases formed at relatively low temperature are apparently related more to the growth kinetics than they are dictated by the thermodynamic consideration. The formation of an amorphous interlayer (a–interlayer) by solid-state diffusion in diffusion couples has been one of the most challenging problems in condensed matter physics in recent years. The a-interlayer has been found to occur in all refractory metal/silicon and a number of rare-earth (RE) metal and platinum-group metal and crystalline silicon systems. A systematic survey and review of extensive studies on the subject in the past years showed: A negative heat of mixing provides the driving force for the reaction and fast diffusion of one component in the other preempts the formation of crystalline compounds The growth follows a linear law at the initial stage with activation energy around 1–1.5 eV for refrac- tory metal/silicon systems and 0.5 eV for RE metal/silicon systems The dominant diffusing species is silicon The stability of the amorphous inter- layer depends on the composition Multiphases are present simultane- ously in the initial stage of metal/ silicon interaction Good correlations exist between physical parameters and kinetic data From the investigation of amorphous interlayers, mechanisms of roughing of epitaxial RE silicide/(001)silicon interface, formation of stacking faults, and pinholes in RE silicides have gained Figure 1. A cross-section scanning electron microscope image of a six-level metal backend structure. (Courtesy UMC.) 2 μm

Metal silicides: An integral part of microelectronics

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Page 1: Metal silicides: An integral part of microelectronics

JOM • September 200524

Phase TransformationsOverview

Editor’s Note: A hypertext-enhanced version of this article is available on-line at www.tms.org/pubs/journals/JOM/0509/Chen-0509.html.

This article presents an overview of the recent developments in the fundamental understandings and microelectronics applications of metal silicides. The syn-thesis and characterization of nanoscale silicides with potential applications in nanotechnology are reviewed.

INTRODUCTION

Metal silicide thin fi lms are integral parts of all microelectronics devices. They have been used as ohmic contacts, Schottky barrier contacts, gate elec-trodes, local interconnects, and diffusion barriers. With advances in semiconduc-tor device fabrication technology, the shrinkage in line width continues at a fast pace. The International Technol-ogy Roadmap for Semiconductors (ITRS) predicted that in 2005, in the 90 nm generation devices, the gate length and thickness of silicide at the contact window would be 32 nm and 20 nm, respectively. In the year 2007, for the 65 nm generation devices, these numbers are predicted to further decrease to 25 nm and 17 nm, respectively.1 In addition, more transistors will be incorporated in one chip. However, owing to the demand for increased integration level, the sur-face area will not be adequate to meet

Metal Silicides: An Integral Part of Microelectronics

L.J. Chen

the interconnect demand. Multi-level interconnections provide fl exibility in circuit design and a substantial reduction in die size and, thus, chip cost. Figure 1 shows a scanning electron microscope (SEM) cross section of a six-level metal backend structure. Electrical connec-tion between the various metal layers is provided by vertical interconnects commonly referred to as vias. See the sidebar for device application details.

SILICIDE FORMATION

The impetus for the study of silicide formation on silicon was stimulated by the expectation of device applica-tions of silicides in the late 1970s and early 1980s. Two review chapters have succinctly summarized the knowledge accumulated up to the early 1980s.6,7 This article focuses on the most important developments in recent years.

Solid-State Amorphization

In device applications, interfacial reactions of metal thin fi lms with silicon are rather peculiar in that polycrystalline metal fi lm reacts with single-crystal sili-con. The substrate is covalently bonded and the thin fi lm is metallic. As a result, the microstructure of the silicide fi lm and orientation of the substrate may play an important role in infl uencing the reaction.

Some silicides can form at a temperature as low as 100°C. The mechanism for the break up of silicon bonds at such a low temperature is rather intriguing.7 Fur-thermore, the silicide phases formed at relatively low temperature are apparently related more to the growth kinetics than they are dictated by the thermodynamic consideration. The formation of an amorphous interlayer (a–interlayer) by solid-state diffusion in diffusion couples has been one of the most challenging problems in condensed matter physics in recent years. The a-interlayer has been found to occur in all refractory metal/silicon and a number of rare-earth (RE) metal and platinum-group metal and crystalline silicon systems. A systematic survey and review of extensive studies on the subject in the past years showed: • A negative heat of mixing provides

the driving force for the reaction and fast diffusion of one component in the other preempts the formation of crystalline compounds

• The growth follows a linear law at the initial stage with activation energy around 1–1.5 eV for refrac-tory metal/silicon systems and 0.5 eV for RE metal/silicon systems

• The dominant diffusing species is silicon

• The stability of the amorphous inter-layer depends on the composition

• Multiphases are present simultane-ously in the initial stage of metal/silicon interaction

• Good correlations exist between physical parameters and kinetic data

From the investigation of amorphous interlayers, mechanisms of roughing of epitaxial RE silicide/(001)silicon interface, formation of stacking faults, and pinholes in RE silicides have gained

Figure 1. A cross-section scanning electron microscope image of a six-level metal backend structure. (Courtesy UMC.)

2 μm

Page 2: Metal silicides: An integral part of microelectronics

2005 September • JOM 25

DEVICE APPLICATIONS For metallization of integrated circuit (IC) devices, transition metal silicides, including near-noble and refractory metal silicides, are used. The general requirements are: low resistivity; good adhesion to silicon; low contact resistance to silicon; appropriate Schottky barrier height or Ohmic with heavily doped silicon (n+ or p+); thermal stability; appropriate morphology for subsequent lithography and etching; high corrosion resistance; oxidation resistance; good adhesion to and minimal reaction with SiO

2; low

interface stress, compatible with other processing steps such as lithography and etching, minimizing metal penetration; high electromigration resistance; and formability at low temperature. The requirements are rather stringent and at present, only three silicides, TiSi

2, CoSi

2, and NiSi, are being considered for metal contacts for advanced devices.2

PtSi and Pd2Si were used early on for metal contacts to lower the contact resistance

of aluminum alloys as well as to serve as a diffusion barrier layer between aluminum alloy fi lm and silicon. In the early 1980s, as the linewidth decreased to about 1 μm, many refractory metal silicide fi lms, such as MoSi

2, WSi

2, TiSi

2, and TaSi

2 were used by

different manufacturers. For the 0.25 μm technology, TiSi2 was almost used exclusively.3

For devices with linewidth of 0.18 μm or smaller, TiSi2, CoSi

2, and NiSi are possible

candidate contact materials.4,5 Many different deposition techniques can be used to deposit metal thin fi lms. Currently, sputtering is used almost exclusively to deposit metal layers for contacts or in the self-aligned silicidation (salicide) process. Figure A shows a self-aligned TiSi

2, which was

formed on source, drain, and gate simultaneously. On the other hand, chemical vapor deposition of WSi

x and tungsten fi lms is the dominant method to form gate electrodes or

local interconnects and metal plugs, respectively. The usual steps to form a silicide begin with the cleaning of the wafers consecutively by organic solution, dilute hydrochloric acid (HF), and deionized water. The wafers are blown dry with a nitrogen gun or in a “spin-rinse-dry” process. An alternative is to dip the wafer in dilute HF then blow dry with a nitrogen gun or “spin dry.” The wafers are immediately placed in the metal deposition chamber and the surface is sputter-cleaned by argon ions if necessary (argon sputtering may cause particle issue). Next, metal thin fi lms are deposited on silicon at room temperature or at a higher temperature, and fi nally, the wafers are heat treated either by traditional furnace annealing or by rapid thermal annealing to form silicides. Prior to the deposition of metal thin fi lms, a 1.5-nm to 2-nm-thick SiO

2 layer was

usually present at the silicon substrate surface following the etching of the thermal oxide. It is necessary for the contact metal layers to penetrate the thin oxide layer to react with the silicon to form silicides. Titanium and nickel atoms are capable of penetrating through the thin oxide. On the other hand, cobalt atoms have diffi culty forming silicide with silicon if a thin oxide layer is present at the interface. An argon ion sputter-cleaning step is usually required. Since CoSi

2 is widely used in devices with linewidths of 0.18

μm or smaller, the formation of CoSi2 is used as an example to illustrate the steps to

form silicides on silicon. The deposition of cobalt thin fi lms by sputtering is kept at room temperature. A mixture of Co

2Si and CoSi is formed at 300°C. CoSi

2 forms at 550°C.4

For rapid thermal annealing, the fi rst-step and second-step annealings are conducted at 500–550°C for 30–60 s and 700–850°C for 30–60 s, respectively.

in basic understanding. The insight led to successful growth of a pinhole-free epitaxial RE silicide layer on (111)Si. Furthermore, the enhanced formation of technologically important C54-TiSi

2 by

high-temperature sputtering, a thin inter-posing molybdenum layer, and tensile stress can all be explained involving some aspects of the amorphous interlayers.8

The First Nucleated Phase and Simultaneous Occurrence of Multiphases

In the transition metal-silicon binary phase diagrams, three or more silicide phases usually can be found. However, only selective phases are detected after thermal annealing of metal thin fi lms on silicon. From x-ray diffraction and Ruth-erford backscattering spectrometry data, it was concluded initially that only one phase grows at a time for a clean system. This is consistent with the assertion that the formation of silicides is determined more by the growth kinetics than by ener-getics. However, more refi ned analysis by high-resolution transmission-electron microscopy (HRTEM) in conjunction with the fast Fourier transform analysis as well as auto-correlation function analysis indicated that formation of multiphases occurred in a number of refractory metal/silicon systems.8–11 In the Ti/Si system, Ti

5Si

3, located at

the Ti/a–interlayer interface was identi-fi ed to be the fi rst nucleated phase.9 Ti

5Si

3,

Ti5Si

5, TiSi, and C49-TiSi

2, along with

an amorphous interlayer, were observed to be present simultaneously in samples annealed at higher temperatures.10 Examples are shown in Figures 2 and 3.

Similar results were obtained for many refractory metal-silicon systems.8 For the near-noble silicides, a complex forma-tion sequence was also found recently. The complex sequence of nickel silicide

formation has been observed with the sheet resistance measurements combined with in-situ x-ray and light-scattering measurements in a synchrotron radiation facility.5

Figure A. A cross-sec t ion t rans-mission electron microscope image of a 0.1 μm TiSi2 salicide structure. 100 nm

Figure 2. A TEM image of amorphous interlayer at the Ti/(001)Si interface in an as-deposited sample.

3 nm

Ti

a

Si

Page 3: Metal silicides: An integral part of microelectronics

JOM • September 200526

Growth Kinetics of Silicides

Kinetic data are crucial for a basic understanding of interfacial reactions between metal thin fi lms and silicon. Most silicides are formed at a tem-perature far lower than the eutectic temperature. The growth is often dif-fusion controlled or interface-reaction controlled. The thickness of the silicide is proportional to the square root of time t and t, respectively. The presence of contaminating or doping impurities was found to infl uence the growth rate. For platinum fi lms deposited in ultrahigh vacuum, the growth rate of PtSi was found to increase signifi cantly. However, the growth law remained the same.12

Cross-section transmission electron microscopy (XTEM) has been demon-strated to provide direct and accurate kinetic data, such as the sequence of phase formation, the dependence of the phase growth, and morphology of phase and interface structure in the growth of silicides on silicon.13

In TiSi2, CoSi

2, NiSi

2, and a number

of RE silicides, the silicide formation took place within a narrow temperature range and nucleation was suggested as a controlling mechanism.14 The nucle-ation effects are eliminated when these phases are formed on an amorphous layer.15 The importance of nucleation effects in silicide formation has been discussed extensively by d’Heurle.14 The fi lms produced from nucleation-limited reactions are often rather rough.

Dominant Diffusing Species

In the silicide formation, metal atoms diffuse across the metal/silicide interface, silicon atoms diffuse across the silicide/silicon interface, or both. In order to determine the dominant diffus-ing species, it is common to introduce an inert marker. In thin fi lm reactions, the

markers are usually tens of nanometers in size and should not infl uence the growth kinetics of silicide formation. Ideally, the markers should be inert and remain immobile as the diffusing species streams by. An additional constraint is that the marker should be located in the silicide layer to avoid possible infl uence due to the presence of the interface.7

From the marker experiments, it was revealed for metal-rich silicides such as M

2Si, the dominant diffusing species are

mostly metal atoms. On the other hand, in the formation of monosilicide and disilicide, silicon atoms are generally the dominant diffusing species. However, there are exceptions. Important silicides in ultralarge-scale integrated-circuit technology, the dominant diffusing species in the growth of TiSi

2, CoSi

2,

WSi2, and NiSi are Si, Co, Si, and Ni,

respectively.6,7,14 For the TiSi2 salicide

process, if the temperature, time, and ambient for the rapid thermal annealing were not optimized, C49-TiSi

2 and/or

C54-TiSi2, which are not easily removed

by ammonia and peroxide solution, are prone to form on the dielectric sidewall between the poly-gate and source/drai. This results in the so-called bridging problem, which may lead to device failure. Since cobalt is the dominant dif-fusing species in the formation of CoSi

2,

the bridging problem is less troublesome in the CoSi

2 salicide technology.

Epitaxial Growth of Silicides

Epitaxial silicides belong to a special class of silicides that exhibit a defi nite ori-entation relationship with respect to the silicon substrate. A silicide is expected to grow epitaxially on silicon if the crystal structures are similar and the lattice mismatch between them is small. The impetus for the study of epitaxial silicides mainly stemmed from several favorable characteristics of epitaxial silicides in

comparison with their polycrystalline counterparts, including greater stabil-ity and a lower stress at the interface, alleviation of grain boundary effects, as well as conductivity enhancement.16

NiSi2 and CoSi

2 can be grown in

single-crystal form on silicon.17 Many hexagonal RE silicides have been grown on Si(111) for the almost perfect lattice matches between RE silicide (0001) and Si(111) planes. Furthermore, on top of the silicide layer, a single-crystal silicon layer can be grown. An example of the Si/TbSi

2/Si heterostructure is shown in

Figure 4.18 On the other hand, almost all transition metal silicides can be grown epitaxially on silicon to a certain extent. In particular, FeSi

2 and TiSi

2 can be

grown to tens of micrometers in grain size.16

Initial studies on the epitaxial growth of silicides on silicon were mostly on the growth of silicides on a large area. However, in device applications, silicides were grown on laterally confi ned silicon. Lateral confi nement was found to exert signifi cant infl uence on the epitaxial growth of NiSi

2 and CoSi

2 on silicon.19–21

The epitaxial silicides were relevant to the device applications as the contact size shrank to sub-100 nm. In an Ni/(001)Si system, low-resistiv-ity NiSi is at the center of attention in device applications. In nickel on blank (001)Si, NiSi is formed and stable at 350–700°C.6 It has been reported that dopants do not affect NiSi formation.22 However, striking effects of B+ and BF

2+ implanta-

tion on the growth of epitaxial NiSi2 on

silicon were observed. As a result of ion

Figure 3. A schematic diagram showing the formation of multiphases in a Ti/Si sample.

Figure 4. An atomic resolution TEM image of Si/TbSi2/Si heterostructure with simulated images pasted for direct comparison.

2 nm

Si

Si

TbSi2

Page 4: Metal silicides: An integral part of microelectronics

2005 September • JOM 27

implantation into (001)Si, epitaxial NiSi2

was found to grow at 200–280°C instead of the usual formation temperature of about 800°C on blank (001)Si. Both boron and fl uorine atoms introduced by ion implant into silicon were found to promote the epitaxial growth of NiSi

2 on

silicon at low temperatures. Good cor-relation was found between the atomic size factor and the resulting stress and NiSi

2 epitaxy at low temperatures. The

fi nal structure of the silicide layer was found to depend critically on the thick-ness of the starting nickel overlayer and the annealing temperature. The amorphicity of the substrate apparently played an important role in promoting the formation of polycrystalline NiSi

2 at

low temperatures.23–25

NANOSILICIDES

Nanoscale silicides are named nanosil-icides. As the integrated circuit industry moves into the nano-era, metal silicide contacts are naturally falling into this category. On the other hand, many efforts have been made to fabricate nanosilicides employing the bottom-up approach without elaborate microlithography.

Nanodots

Quantum dots are envisioned to be useful in devices such as single-electron transistors, high-density memories, light emission, semiconductor lasers, and tunnel diodes.26 In principle, any ultrathin (~ 1 nm) silicide forming metal fi lm may react with silicon substrate to form sili-cide nanodots under appropriate anneal-ing conditions. Other means, such as ion implantation of metal ions into silicon

nanowires followed by annealing, may also produce silicide nanoparticles.27 To meet the requirements of microelectron-ics and optoelectronics, it is imperative to control the size, density, and ordering of the dots. Self-assembly is an attractive nano-fabrication technique because it pro-vides the means to precisely engineer structures on the nanometer scale over large sample areas. Self-organizing nanocrystal assemblies have already shown the degree of control necessary to address the challenges of building nanometer-scale technologies.28

Self-Assembled Low-Resistivity Metal Silicide Quantum Dot Arrays on Epitaxial Si0.7Ge0.3 on (001)Si

Si1–x

Gex/Si heterostructures are used

to fabricate high-speed transistors that

extend the range of applications of sili-con technology.29 Self-assembled NiSi quantum-dot arrays have been grown on relaxed epitaxial Si

0.7Ge

0.3 on

(001)Si.

The formation of the one-dimensional (1-D) ordered structure is attributed to the nucleation of NiSi nanodots on the surface undulations induced by step bunching on the surface of SiGe fi lm. This results from the miscut of the wafers from normal to the (001)Si direction. The two-dimensional (2-D), pseudo-hexagonal structure was achieved under the infl uence of repulsive stress between nanodots. Since the periodicity of surface bunching can be tuned with appropriate vicinality and misfit, the undulated templates promise to facilitate the growth of ordered silicide quantum dots with selected periodicity and size.30

Figure 5 shows a planview TEM micrograph of an Ni(2 nm)/a-Si(2 nm)/Si

0.7Ge

0.3 sample revealing the ordered,

equally spaced NiSi dot arrays, oriented along the [110 ] surface direction. The apparent 1-D alignment and less ordered 2-D arrangement features rule out the direct infl uence of the misfi t-dislocation strain. The average size of nanodots and spacings between adjacent arrays are about 15 nm and 20–40 nm, respectively. In contrast, NiSi nanodots in Ni/a-Si/Si(001) samples were found to be ran-domly distributed. It indicated that the use of an Si

1–xGe

x/Si heterostructure

template induces the highly ordered alignment of NiSi dots. A close look at the Si

0.7Ge

0.3/(001)Si

and Ni(2 nm)/a-Si(2 nm)/Si0.7

Ge0.3

sur-faces with HRTEM indeed revealed the

50 nm

Figure 5. A plan-view TEM image of an Ni(2 nm)/a-Si(2 nm)/Si0.7Ge0.3 sample annealed at 600°C for 1 h.

200 nm

Figure 6. A planview TEM image of an Ni(7 nm)/a-Si(13 n m ) / S i 0 . 7 G e 0 . 3 sample annealed at 500°C for 1 h.

Page 5: Metal silicides: An integral part of microelectronics

JOM • September 200528

presence of the atomic steps, about 5–20 nm in spacing and 10 nm in average spacing. The HRTEM images further showed that the irregularity in step spac-ing indicating the presence of step bunching. In a particular instance, the nanodot arrays, about 100–800 nm apart, were found to align with the cross-hatch pattern in a 500°C annealed Ni(7 nm)/a-Si(13 nm)/Si

0.7Ge

0.3 sample, as shown in

Figure 6. The nanodots tended to be connected along individual arrays. The alignment of nanodots is apparently under the infl uence of the strain fi elds associated with the cross-hatch patterns. It is conjectured that the alignment with the cross-hatch pattern is most prominent in places where step bunching is of low density and exerts weak infl uence on the formation of nanodot patterns. Similarly, CoSi

2 and TiSi

2 nanodot arrays were

formed.31

Formation of Epitaxial β-FeSi2 Nanodot Arrays on Strained Si/Si0.8Ge0.2 (001) Substrate

Epitaxial β-FeSi2 nanodots were

grown on strained Si/Si0.8

Ge0.2

(001) substrates by the solid-phase epitaxy method. High-quality β-FeSi

2 nanodots

were grown at 800°C by employing strained Si/Si

0.8Ge

0.2 substrates, owing

to a decrease of the in-plane lattice mismatch between the lattice spacing of the β-FeSi

2 [001] and [010] directions

and that of a silicon substrate. Ordered β-FeSi

2 arrays along <110> direction

were observed to form on surfaces of strained Si/Si

0.8Ge

0.2 substrate. It is shown

that dislocation slip originating from

compositionally graded Si1–x

Gex layers

can produce local surface-strain and local thickness variation. The surface features are used for the fabrication of epitaxial β-FeSi

2 nanostructures on strained Si/

Si0.8

Ge0.2

substrate.32

First Nucleated Phase and the Dominant Diffusing Species

Atomic resolution techniques have been successful in studying nanoscale sil-icides. A particularly pertinent example is seen in the identifi cation of Ti

5Si

4 as

the fi rst nucleated phase in submonolayer titanium deposited on the Si(111)-7×7 surface by ultrahigh vacuum scanning tunneling microscopy in conjunction with atomic-resolution TEM. The direct observation of the formation of clusters surrounded by the heavily damaged silicon lattice strongly suggested that silicon is the dominant diffusing species in forming the silicide. An example is shown in Figure 7.33

Nanowires

One-dimensional building blocks, such as nanowires and nanotubes, are especially attractive candidates around

which to develop a bottom-up paradigm for nanotechnology-enabled architec-tures. As opposed to zero-dimensional nanocrystals, which have been the sub-ject of intense study but are challenging to contact electrically, nanowires and nanotubes can act both as interconnects for the transport of charge carriers as well as active device elements.34,35 Nanowires are intrinsically suitable as highly sensi-tive sensor elements, due to their high surface/volume ratio and the extreme sensitivity of 1-D transport to gating fi elds or adsorbates.

Self-Assembled Nanowires

Self-assembled silicide nanowires are envisioned to possess advantages of perfect single crystallinity, metallic resistivity, compatibility with silicon device processing, and high thermal stability. A large number of self-assem-bled epitaxial silicide nanowires were investigated in the past.36–44 Many RE silicide nanowires were grown on silicon substrates. These RE nanowires are commensurate with nearly perfect lattice match in their long direction and are limited in their ability to grow coherently

20 nm

Figure 7. A scanning tunneling microscope image (100 nm × 100 nm) of sub-monolayer titanium deposited on Si(111) 7×7 surface at 700°C.

2 μm

1 μm

Figure 8. An SEM image of NiSi2 nanowires on blank (001)Si substrate by reactive deposition epitaxy at 730°C.

Figure 9. An SEM image of NiSi2 nanowires on nitride-capped (001)Si substrate by reactive deposition epitaxy at 730°C.

Page 6: Metal silicides: An integral part of microelectronics

2005 September • JOM 29

with the substrate in the lateral direction). For PtSi on Si(001), the long direction is aligned with [001]PtSi direction in parallel with the Si(220) plane with smaller lattice mismatch.45 On the other hand, for the growth of C49-TiSi

2, the

range of structural variants argues against a simple interface-energy explanation.40 It is, however, interesting that TiSi

2

nanowires are incommensurate (8%) in their long direction.46 However, the interface structure for the nanowires may not be the same as that inferred from the bulk lattices. For systems of isotropic lattice mis-match, such as Ni/Si and Co/Si systems, the aspect ratio of nanowires in these systems was generally small and unsat-isfactory for practical applications.42–44 Strained epitaxial layers may form while the interface between the overlayer and the substrate is commensurate. These layers are inherently unstable and have interesting properties, which are of importance in semiconductor devices. Two kinds of strained relief mechanism were recognized: one is the formation of dislocations and the other is shape transition. In recent years, it has been recognized that shape changes such as island forma-tion constitute a major mechanism for strain relief.42,47,48 Tersoff and Tromp reported that a strain-induced shape transition may occur. Below a critical size, islands have a compact symmetric shape. For larger sizes, they adopt a long thin shape that allows better elastic relaxation of the island’s stress.47 Experimental data on silicide island formation [e.g., Au

4Si/Si(111)48 and

CoSi2/Si(100)]48 also exhibited the elon-

gated island growth. For the Ti/Si system, a series of phase transformations was reported in thin-fi lm reactions.49 Tita-nium silicide islands of various shapes

were observed.50 The shapes were found to depend on the thickness of titanium deposition and the thermal treatment process. A previous work showed that the formation of CoSi

2 nanowires

involved the mechanism of “endotaxy.”44 The twinning relationship with the sub-strate breaks the symmetry of the surface and leads to the asymmetric growth of islands. By combining the methods of reactive deposition epitaxy and nitride-mediated epitaxy, the formation of high-aspect-ratio NiSi

2 nanowires can be

achieved. Examples are shown in Figures 8 to 10.51 The nanowires were success-fully grown with high aspect ratios despite the four-fold symmetric epi-

Alternative Growth of Silicide Nanowires

Alternative approaches have been adopted to grow nanowires without relying on the mismatch between the nanowires and the substrate. Wu et al. prepared single-crystal metallic NiSi nanowires using free-standing silicon nanowires as the tem-plate. NiSi nanowires were produced by annealing the nickel-metal-coated silicon nanowires at 550°C. They also prepared NiSi/Si nanowire heterostructures with NiSi formed using crossed Si/SiO

2 core-

shell nanowires as masks to defi ne the lengths of the unreacted silicon regions. Electrical measurements show that the single-crystal nickel silicide nanowires have ideal resistivities of about 10 μΩcm and remarkably high failure current den-sities. In addition, the nickel silicide/sili-con (NiSi/Si) nanowire heterostructures have been used to produce fi eld-effect transistors in which the source–drain contacts are defi ned by the metallic NiSi nanowire regions.33 On the other hand, carbon-coated NiSi nanowires were prepared in a radio-frequency-induction heating chemical vapor deposition reac-tor. The growth of the NiSi nanowires and the coating of the nanowires with carbon layers simultaneously took place in the reaction. The nanowires were more than 10 μm long and with an average diameter of 20–40 nm. The resistivity of individual NiSi nanowire was about 370 μΩcm at room temperature, indicating the presence of considerable impuri-ties and/or defects.54 Nickel silicide nanowires were also grown on nickel surfaces by decomposition of silane at 320–420°C. Depending on the growth conditions, single-phase Ni

2Si, Ni

3Si

2,

and NiSi nanowires were formed. It has been demonstrated that directed growth of silicide nanowires can be achieved with the aid of applied electric fi eld.55

Xiang et al. used a vapor-phase deposi-tion method to grow TiSi

2 nanowires on

silicon wafers. Field emission and cath-odoluminescence measurements reveal the potential applications in vacuum microelectronics.56

TaSi2 nanowires have been synthe-

sized by annealing FeSi2 thin fi lm and

nanodots grown on silicon substrate in an ambient containing tantalum vapor. The TaSi

2 nanowires are formed in three

Figure 10. Plots of length and width of NiSi2 islands versus island area.

10

1

10–1

10–2

10–3 10–2

Surface Area (μm2)

■ ■ — Length▲ ▲ — Width

Leng

th a

nd W

idth

(μm

)

10–1 1

■■■■■■

■■■▲▲ ▲ ▲ ▲▲▲▲▲▲ ▲

■■

■■■

■■

▲▲

▲▲▲▲▲▲

The self-assembly

of nanowires usually

requires that the

substrate be

crystalline,

precluding their

use for many

potential applications.

taxial relationship between NiSi2 (of

cubic CaF2 structure) and silicon (of

diamond cubic structure). Nitride-medi-ated epitaxy was presented by Chong et al. to complement the use of oxide medi-ated epitaxy in promoting epitaxial growth of CoSi

2 on (001)Si.52,53 The thin

amorphous interlayer acts as a physical barrier to control the fl ux of metal atoms on the silicon substrate. Such a concept was used in the growth of self-assembled silicide nanowires to control the kinetic process during the growth. A similar effect is expected to be applicable to other strained epitaxial layer systems. The challenges for self-assembled silicide nanowires are the control of aspect ratio and location. In addition, the self-assembly of nanowires usually requires that the substrate be crystalline, precluding their use for many potential applications.

Page 7: Metal silicides: An integral part of microelectronics

JOM • September 200530

steps: segregation of silicon atoms from the FeSi

2 underlayer to form a silicon

base, epitaxial growth of TaSi2 nanodots

on a silicon base, and elongation of the TaSi

2 nanowire along the growth direc-

tion. Strong fi eld emission properties promise future electronics and optoelec-tronics applications.57

ACKNOWLEDGEMENTS

The research was supported by the Republic of China National Science Council through grant No. NSC 93-2215-E-007-011 and Ministry of Education grant No. 91-E-FA04-1-4.

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L.J. Chen is Ministry of Education National Chair Professor of the Department of Materials Science and Engineering at National Tsing Hua University in Hsinchu, Taiwan.

For more information, contact L.J. Chen, National Tsing Hua University, Department of Materials Science and Engineering, Hsinchu, Taiwan, +886-3-573-1166; fax +886-3-571-8328; e-mail [email protected].