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Memory Interface
CEN433
King Saud University
Dr. Mohammed Amer Arafah
Mohammed Amer Arafah2CEN433 - King Saud University
Address Decoding
n Memory devices interfaced are usually of smaller storage capacity than the full address space of the processor
n For example, the 2716 is 2 K x 8 memory device has 11 (= 1 + 10) address inputs (A0-A10).
n When interfaced to a microprocessor with 20 address signals there is a mismatch.
n The extra 9 address pins (A11-A19) are decoded using a decoder such that they select the memory device for a unique position in the memory map of the processor.
n Here the mP address space is 29
times the size of the memory chip
n Decoding A11-A19 and using them for selecting the memory chip fixes the position of the memory locations in the mP address map
19 11 10 0
LS (11 bits)MS (9 bits)Memory
chip
11 Address bits
A10-A0
9 to 1 Decoder
CS/
BA0-19
9 Selector bits
29 = 512 times
...
211 = 2048
0
510
1
000000001 xxxxxxxxxxx
511
00000H
FFFFFH
LS (11 bits)MS (9 bits)
mP Memory Map
00800H
High Memory(ROM)
Low Memory(RAM)
00FFFH
Mohammed Amer Arafah3CEN433 - King Saud University
Example 1: Exhaustive Address Decoding (Simple NAND Gate Decoder)
Memory locations:FF800H-FFFFFH
Mohammed Amer Arafah4CEN433 - King Saud University
Example 2: Exhaustive Address Decoding
Mohammed Amer Arafah5CEN433 - King Saud University
Example 3: Exhaustive Address Decoding (Simple NAND Gate Decoder)
n 32 K x 8 memory device: 15 bit address: 215 locations
n Selector address: 20 – 15 = 5 bits
n If we want the memory locations to start at 10000H, What is the selector address to decode?:
n Start Address00010000000000000000 = 10000H
n End address 00010111111111111111 = 17FFFH
n Selector 5 bits: 00010 (Remain fixed)
n Check: These are 7FFF+1 = 8000H = 215 locations
BA15
BA16
BA17
BA18
BA19
CS/
U1
74LS30
1234
561112
8
U2A
74LS04
1 2
U2B
74LS04
3 4
U2C
74LS04
5 6
U2C
74LS04
5 6
Mohammed Amer Arafah6CEN433 - King Saud University
Exhaustive Address Decoding (74LS138 – 74LS139)
Mohammed Amer Arafah7CEN433 - King Saud University
Example 4: Exhaustive Address Decoding (74LS138)
Memory locations:F0000H-FFFFFH
Module 0:1111 000X XXXX XXXX XXXX
1111 0000 0000 0000 0000to
1111 0001 1111 1111 1111
Module 7:1111 111X XXXX XXXX XXXX
1111 1110 0000 0000 0000to
1111 1111 1111 1111 1111
.
.
.
Mohammed Amer Arafah8CEN433 - King Saud University
Example 5: Exhaustive Address Decoding (74LS138)
64 KB EPROM Starting at F0000H
Answer:
à F0000 – FFFFFH.
à BA0-BA15: Location Addressing.
à BA16-BA19: Space Addressing.
BA16BA17
BA18BA19
CS/
U1A
74LS20
12
45
6
Assume that 64 KB EPROM is not found!
We can replace it with 8 of 8KB EPROM.
Starting address is F0000H.
Answer:
à BA16-BA19: Space Addressing.
à 8KB EPROM
à BA0-BA12: Location Addressing
à BA13-BA15: 8KB Module Addressing
BA16BA17
BA18BA19
BA13BA14BA15
CS0/CS1/CS2/CS3/CS4/CS5/CS6/CS7/
U1A
74LS20
12
45
6
U2
74LS138
A1
B2
C3
G16
G2A4
G2B5
Y015
Y114
Y213
Y312
Y411
Y510
Y69
Y77
Mohammed Amer Arafah9CEN433 - King Saud University
Example 6: Exhaustive Address Decoding (74LS139)
64 KB EPROM Starting at F0000H
Answer:
à F0000 – FFFFFH.
à BA0-BA15: Location Addressing.
à BA16-BA19: Space Addressing.
BA16BA17
BA18BA19
CS/
U1A
74LS20
12
45
6
Assume that 64 KB EPROM is not found!
We can replace it with 4 of 16KB EPROM.
Starting address is F0000H.
Answer:
à BA16-BA19: Space Addressing.
à 16KB EPROM
à BA0-BA13: Location Addressing
à BA14-BA15: 8KB Module Addressing
BA17BA16
BA18BA19
CS1/CS2/CS3/
CS0/BA14BA15U1A
74LS20
12
45
6
U2A
74LS139
A2
B3
G1
Y04
Y15
Y26
Y37
Mohammed Amer Arafah10CEN433 - King Saud University
Exhaustive Address Decoding (PLD Decoders )
n Many modern systems use programmable logic decoders in place of integrated decoders
n They give total freedom in decoding different addresses for individual memory devices
n Programmable logic devices have may be called:¨ PLDs: Programmable logic devices¨ PLAs: Programmable logic array¨ PALs: Programmable array logic¨ GALs: Gate Array Logic¨ SPLDs: Simple programmable logic devices¨ CPLDs: Complex programmable logic devices
n They are all programmable logic devices. Nowadays they can be programmed using VHDL (Verilog Hardware Definition Language)
n Some types are programmed only once (fused links), similar to PROMs
n Some types are erasable like EPROMs
n The next slide shows one of the most common low cost devices: the PAL16L8
Mohammed Amer Arafah11CEN433 - King Saud University
PAL16LR
Mohammed Amer Arafah12CEN433 - King Saud University
PAL16LR
x
y
x x y y
z
z z
xxxxx
F = (xyz)+(xyz)
xyz xyz
Mohammed Amer Arafah13CEN433 - King Saud University
Example 7: Exhaustive Decoding
Mohammed Amer Arafah14CEN433 - King Saud University
Example 7: Exhaustive Decoding
library ieee;use ieee.std_logic_1164.all;entity DECODER_10_17 isport (
BA19, BA18, BA17: in STD_LOGIC; Input declarationROMCS/, RAMCS/ : out STD_LOGIC; output declaration
);end;architecture V1 of DECODER_10_17 isbegin
ROMCS/ <= not BA19 or not BA18 or not BA17; ROMCS/ = 0 for BA19BA18BA17 = 111
RAMCS/ <= A17 or A18 or BA19; RAMCS/ = 0 for BA19BA18BA17 = 000
end V1;
Mohammed Amer Arafah15CEN433 - King Saud University
Example 8: Exhaustive Decoding
E8000-EFFFF F8000-FFFFFF0000-F7000
32 K x 8 32 K x 8 32 K x 8
A19 A18 A17 A16 A151 1 1 0 1
A19 A18 A17 A16 A151 1 1 1 0
A19 A18 A17 A16 A151 1 1 1 1
Mohammed Amer Arafah16CEN433 - King Saud University
Interfacing EEPROM (Flash) Memories
n Main Flash memory applications:
¨ Used when contents need to be changed only infrequently, e.g.:
n Storing system BIOS
n USB pen drives
n MP3 audio players
n Similarities with SRAMs:
¨ Both need the 3 basic memory control inputs: CE, OE, and WE
n Differences with SRAMs:
1. EEPROM needs an additional programming controls and programming (erasing) supply voltage. Used to be 25 or 12V, now 5 or even 3.3V.
2. EEPROM is much slower to write (erase) a byte: 0.4 s Versus 10nsfor SRAM
Mohammed Amer Arafah17CEN433 - King Saud University
Example 9: Interfacing EEPROM
Additional controls for Flash memory.
Used for programming (erasing)
Enable Power down mode
Programming supply voltage
Address:Start: 10000000000000000000End: 11111111111111111111i.e. 80000H to FFFFFH
In the word mode:256 K x 16
18-bit address starting with A1
00000H
FFFFFH
7FFFFH80000H
Flash occupies the top Half of the memory map
28F400Flash
Memory
512K x 8(In the Byte
Mode)
In Byte operation,DQ15 is an inputaccepting A0 address bit.
Select Byte (not Word) operation
Mohammed Amer Arafah18CEN433 - King Saud University
Example 10: Exhaustive Decoding
Interface a 16KB RAM and a 64KB EPROM to an 8088 buffered system. Assume the starting address of the RAM is 0H and the starting address of the EPROM is F0000H. Use NAND gates, as needed, to generate the chip selects.
Mohammed Amer Arafah19CEN433 - King Saud University
Solution of Example 10:
Mohammed Amer Arafah20CEN433 - King Saud University
Example 11: Exhaustive Decoding
Interface a 4KB RAM and an 8KB EPROM to an 8088 buffered system.Assume the starting address of the RAM is 0H and the last address of the EPROM is FFFFFH. Use NAND gates, as needed, to generate the chip selects.
Mohammed Amer Arafah21CEN433 - King Saud University
Solution of Example 11:
Mohammed Amer Arafah22CEN433 - King Saud University
Example 1: Partial Decoding
Ignoring both BA18 and BA19
Mohammed Amer Arafah23CEN433 - King Saud University
Example 2: Partial Decoding
Ignoring both BA17, BA18 and BA19
Mohammed Amer Arafah24CEN433 - King Saud University
Example 3: Partial Decoding
Ignoring both BA17 and BA18
Mohammed Amer Arafah25CEN433 - King Saud University
Example 4: Partial Decoding
Ignoring BA16, BA17 and A18
Mohammed Amer Arafah26CEN433 - King Saud University
Example 5: Partial Decoding
Assume that the 1M memory space is divided into 16 blocks. One of these blocks is used, and the rest are ignored. The block is divided further into 4 segments. The first segment is used only by a 2KB RAM, the second and the third segment are left for future expansion, and the fourth segment is used only by an 8KB EPROM. Interface both 2KB RAM and 8KB EPROM to the 8088 system using partial decoding.
Mohammed Amer Arafah27CEN433 - King Saud University
Solution of Example 5:
Mohammed Amer Arafah28CEN433 - King Saud University
Interfacing 16-bit Memory to the 8086, 80286, and 80386SX
n Main differences: 8086 from the 8088:¨ The M/#IO replaces the IO/#M control signal
¨ The data bus is now 16 bits not 8 bits
¨ A new control output, BHE/ [Bus (byte) High Enable]
¨ A0 has a special use as BLE/ [Bus (byte) Low Enable]
n Main differences between 8086/186 and 80286/386SX:¨ 80286/386SX has 24-bit address bus (A23-A0)
¨ The M/#IO, RD/, WR/ are replaced with MRDC/, MWTC/, IORDC/ and IOWTC/- more specific signals
Mohammed Amer Arafah29CEN433 - King Saud University
16-Bit Wide Memory
n 16-bit wide memory is organized in two separate 8-bit wide memory banks: ¨ Low bank (even-numbered byte locations: 0, 2, 4, 6, …) à low 8 bits of the data bus (D0-D7): LS Byte
¨ High bank (odd-numbered byte locations: 1, 3, 5, 7, …)à high 8 bits of the data bus (D8-D15): MS Byte
n Processor must be able to access any 16 or 8 bit locations
n Banks are selected by the microprocessor through bank selection (Bank Enable) signals
n On the 8086, these byte selection signals are - The BLE/ (A0) signal selecting low bank- The BHE/ signal selecting high bank
n Only with writes…. For Reads, the processor will take the byte it wants and no need to enforce byte (bank) selection
Mohammed Amer Arafah30CEN433 - King Saud University
16-Bit Wide Memory
Low Bank
(Even Bank)
High Bank
(Odd Bank)
0000000001
0000200003
0000400005
..
..
..
FFFFAFFFFB
FFFFCFFFFD
FFFFEFFFFF
No banks enabled11
Low bank enabled for an 8-bit transfer01
High bank enabled for an 8-bit transfer10
Both banks enabled for a 16-bit transfer00
FunctionBA0BBHE/
Mohammed Amer Arafah31CEN433 - King Saud University
16-Bit Wide Memory
Encoding Separate Write Signals
n Why consider this only with write access (not Reads)?
Because the processor can choose only the byte(s) it wants to read from the full 16-bit data placed on the data bus by the 2 banks. So always enable both banks for READs.
Mohammed Amer Arafah32CEN433 - King Saud University
Example 1: 16-Bit Wide Memory
If start byte address is 060000, Last address is 06FFFFHSEL = A23 + A22 + A21 + A20 + A19 + #A18 + #A17 + A16
(active low)
32K x 832K x 8
No bank selection for READsCommon to both banks
High bank data bits
Low bank data bits
Low Bank High Bank
Common CE for both banks
Active Low (one decoder)
Write Enable for low
bank
Write Enable
for high bank
Note: A1 not A0
Mohammed Amer Arafah33CEN433 - King Saud University
Example 1: 16-Bit Wide Memory
library ieee;use ieee.std_logic_1164.all;entity DECODER_10_28 isport (
A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC;SEL, LWR, HWR: out STD_LOGIC
);end;architecture V1 of DECODER_10_28 isbegin
SEL <= A23 or A22 or A21 or A20 or A19 or (not A18) or (not A17) or A16;LWR <= A0 or MWTC;HWR <= BHE or MWTC;
end V1;
Mohammed Amer Arafah34CEN433 - King Saud University
Example 2: Memory Interface to 8086n We want to interface 64 KB RAM and 64KB EPROM chips to 8086
microprocessor according to the following assumptions:¨ The starting address of the RAM is 0H.¨ The last address of the EPROM is FFFFFH.¨ Exhaustive decoding is used.¨ The RAM and EPROM chips are organized as following:
Mohammed Amer Arafah35CEN433 - King Saud University
Example 2: Memory Interface to 8086
Mohammed Amer Arafah36CEN433 - King Saud University
Example 3: Memory Interface to 8086
n We want to interface 64 KB RAM to 8086 microprocessor according to the following assumptions:¨ The starting address of 64 KB RAM in the memory space is 0H.¨ Exhaustive decoding is used.¨ The RAM chips are organized as following:
Mohammed Amer Arafah37CEN433 - King Saud University
Example 3: Memory Interface to 8086
RAMHCS/
BA1-15
MEMR/
HWR/
BD8-15
RAML3CS/
BA1-14
MEMR/LWR/
BD0-7
MEMR/LWR/
RAML1CS/BD0-7
BA1-13
MEMR/LWR/
RAML2CS/BD0-7
BA1-13
03FFF
32K × 8RAM
8K × 8RAM
16K × 8RAM
00000
04000
07FFF
08000
0FFFF
00000
0FFFF
8K × 8RAM
BA0 = 0BBHE/ = 0
74LS139
RAML1CS/RAML2CS/
RAML3CS/
BA14
BA15
RAMHCS /
A B
G